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Hi Vladislav, As u told that optoisolator dosen't support high clock frequency . Are there any other alternatives to replace a opto isolator so that i can work at higher frequency. rgds, prav Vladislav Vasilenko <vlad@comsys.ntu-kpi.kiev.ua> wrote in message news:<402B57CA.9FD9FF73@comsys.ntu-kpi.kiev.ua>... > prav wrote: > > > Hi all, > > > > I was studying some board schematics. In this there are some clocks > > coming from external world . Before these clocks are connected to the > > FPGA pins they pass through an opto isolator.Could any body help me > > out why the opto isolators are really required . > > > > They usually required when the signal source has the > different ground potencial than FPGA has. > Often it occurs when the signal source is far from FPGA > and the signal and ground wires make a pair to prevent > noise errors. > In the medical installation it is the usual practice > because of voltage shield of patients. > > But the opto isolator usually does not support > the high clokck frequency. > > A.Ser.Article: 66151
gregs@altera.com (Greg Steinke) wrote in message news:<5c1de958.0402121458.4c1cc566@posting.google.com>...
> tal_h@elbit.co.il (tal_h) wrote in message news:<7fc7c85.0402110004.797bdc7f@posting.google.com>...
> > Hi,
> > I have a problem in configurating altera devices in my board.
> > my configuration scheme is as follows:
> > 1 EPC16 device connected in PPS mode to:
> > A stratix device connected to Data0 (EP1S20) & 2 cyclone devices
> > (EP1C12) connected to Data1 & Data2 of the EPC16…
> > When I power-up the board => the Configuration isn't done.
> > I've looked on the nSTATUS & CONF_DONE signals and they look fine!
> > the CONF_DONE stays LOW all the time. the nSTATUS goes HIGH ~85mSec
> > after power is stable.
> > the DCLK signals stays LOW all the time! (there isn't DCLK)
> > I've tried an external OSC to the EPC16 => still the same phenomenon.
> > Please Advice!
> > Tal
>
> Hi Tal,
> The EPC16 should be driving out the DCLK signal, so figuring out why
> this does not happen is key. However it's hard to say exactly what is
> the problem based on this description. Here's a few things to try:
>
> 1. Make sure that the MSEL pins are set correctly on the FPGAs. PPS is
> the acronym for Passive Parallel Synchronous - but the setup where one
> EPC16 drives multiple FPGAs in parallel like this is called Concurrent
> Configuration, and each FPGA should be set to Passive Serial as each
> is receiving a serial stream.
>
> 2. Make sure the PGM pins are set correctly on the EPC16 to show which
> page of data you want to access. If you are not doing anything special
> like storing multiple configurations, they should be set to 0.
>
> 3. There are some external connections that must be made on the EPC16.
> The F-RP# pin must be connected to the C-RP# pin. And the F-WE# pin
> must be connected to the C-WE# pin. This connection is because the
> EPC16 actually has two dice in it - a Flash and a controller. During
> the production test, the Flash pins are driven to 12 V, but the
> controller cannot handle this, therefore the connection cannot be made
> in the package.
>
> 4. The FPGA VCCINT must be powered before the POR on the EPC16
> expires. The POR can be set to 2 ms or 100 ms by using the PORSEL pin
> - if you drive PORSEL low, then the POR is 100 ms. If this is not
> done, then the EPC16 will never start configuration and you will not
> see DCLK toggle.
>
> Hopefully one of these solves the problem. If not, please check out
> the FPGA Configuration Troubleshooter found on this web site:
> http://www.altera.com/cgi-bin/ts.pl?fn=configuration
>
> And if that doesn't work, then you may need to call the distributor,
> FAE, or AE for some more assistance as the problem debug starts to get
> very specific.
>
> Sincerely,
> Greg Steinke
> Altera Corporation
> gregs@altera.com
Hi Greg,
Thank you for your reply.
Here are some more facts regarding to my board:
1. the VCCINT is stablized in about ~1mSec after power-up. the POR is
configured to 100mSec.
2. all of the MSEL & PGM pins are configured correctly.
3. the EPC16 Flash interface pins (address. data etca) are connected
to a HOST. first, I had problems in programing the EPC16 through
ByteBlaster, So I've disbled the HOST permentlay (all of its pins are
HIGH-Z always) & the programing worked!
4. I forgot to connect the nIO_PULL pin of the EP1S20 device to GND /
VCC, I can't connect it because it hasn't got a VIA on the PCB, So it
left un-connected.
5. I've tried power-sequencing:
a. I've powered the EPC16 VCC before the FPGA's VCCINT & VCCIO & the
configuration worked!
b. I've tried also the opposite sequence. first, I've powered the
FPGA's
VCCINT & VCCIO and then I've powered the EPC16 VCC and the
configuration
ALSO WORKED!!!!
c. when I don't have power-sequnce the configuration isn't
working!!!!!!
I've talked with my distributer & he hasn't got a clue....
please advice next...
Thanks,
Tal
Article: 66152Peter Alfke <peter@xilinx.com> writes: > 11C90, 10/11 ECL variable modulus prescaler, memories of the early > 'seventies...It's amazing that we could build frequency synthesizers > running close to a GHz at that time. Lots of power though, and tricky > pc-board layout. Now it's so much more integrated, and one can easily > recover from design mistakes. I love FPGAs ! > > The trouble with a fast front-end in our FPGAs is that almost everything > has gotten much faster ( and more sophisticated ) in the past 5 years, > but the raw toggle frequency of a LUT+flip-flop has not doubled from the > 400 MHz we could do 5years ago in XC4000XL. The flip-flop is much > faster, but the routing, although flexible, is less direct. That's why I > have given up doing it that way. > > The MGTs in Virtex-II Pro can receive 3.125 gigabits/sec, which means > 1.5 GHz. > And there is an easy way to bypass lots of stuff, and represent 20 > incoming bits in parallel. The rest is just design at 150 MHz. Not difficult. > > Anybody need a counter with resolution between 1.5 and 5 GHz ? Not a counter, but I need to generate edges with subnanosecond timeresolution, and also measure the precise position of edges with the same resolution. Regards, Thomas HellerArticle: 66153
www.pcitree.de The program can read/write config/memory space in winxp/nt/2k. Now I can get back to VHDL. Regards, LC "Kang Liat Chuan" <liat-chuan_kang@agilent.com> wrote in message news:1076580017.344075@cswreg.cos.agilent.com... > Dear experts in this area, > > I am trying to configure a PCI board plugged into my PC, running Windows > 2000 sp3. > This board is the Memec PCI development board, with a Spartan II-200 FPGA > connected to the 32-bit PCI bus. > > I figured that either BIOS or Windows configures the PCI board at bootup, > and assigns > the BAR0 etc. I am using an FPGA with the Xilinx PCI32 LogiCore. Hence, the > Command and Status Register bit 2 (Bus Master) is '0' at startup. How can I > set it > to '1' after startup? > > For those of you familiar with the Xilinx PCI32 LogiCore, I've thought about > hard > setting the CFG_SELF bit to '1', which will fool the core to initiate master > transactions. > But in simulation, I see that the ADIO bus does not get the date from the AD > bus! > A more tedious way is to self configure the PCI core to master, but I am > seeking an > easier way. My firmware colleague told me I have to make use of the > "pci.sys" driver > in Windows. > > I am not a programmer, and am not familiar with the "pci.sys" driver. Is > there an easier > way to do this? > > Thanks and regards, > LC > >Article: 66154
You can usually do mixed language if you are prepared to pay lots of money for licenses. But if your doing Xilinx, or maybe something else, then have a look at the second method outlined here http://www.enterpoint.co.uk/techitips.html . You can synthesis with XST in both Verilog and VHDL. I can't confirm if you can do both at once in one project I would need to check that. If I was doing on a design that is big enough to warrant 2 languages I would usually break it down into some kind of increment / modular flow anyway. You can also use ISE toolset to write out a module in another language. It is there mainly for simulation but you can use it otherwise. John Adair Enterpoint Ltd. This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Remis Norvilis" <Norvilis.spam@charter.net.fake> wrote in message news:102of4grl3t4n38@corp.supernews.com... > I wonder if it is possible to synthesize on one chip VHDL and Verilog IP > cores. I suppose the VHDL to Verilog or vice versa translator could be > used. > Ideas are welcome. > > Remis > -- > > ************************************************ > To reply, remove >.spam< and >.fake<Article: 66155
Hi, I have big problem to move my project (NIOS + some hardware) from CYCLONE to APEX20K200. During fit, I have masg: Error: Logic cell ref_16_system:inst|cpu:the_cpu|cpu_pipeline:the_cpu_pipeline|cpu_compact_alu:the_cpu_compact_alu|cpu_adder_logic_lock_region:the_cpu_adder_logic_lock_region|cpu_aluadder:the_cpu_aluadder|cpu_hidden_lcell_4CEF:carryout_reg|regout requires 5 secondary signals of types non-global clock, non-global clock enable, non-global clear, non-global synchronous clear, and non-global synchronous load, but the selected device allows only 4 signals Quartus HELP remarks, that I have to switch Auto Global Clock and Signals "ON". I did it, but error still keep. What I can do? Best regards Leszek leszekd@itam.zabrze.plArticle: 66156
I would like to use the "locked" output of a DLL to make sure that my internal logic (ie. FSMs) doesn't start-up until a stable system clock is available. I'm not sure if the "locked" signal is already a synchronous one, or if I better use a 2-stage synchronizing circuit to move it to my system-clock domain. Anyone knows ? Many thanks, Guy.Article: 66157
(snip) > I tried this: > > NET "CLK*" TNM_NET = "CLK"; > NET "CLKEN" TNM_NET = "CLKEN"; > NET "NSI*" TNM_NET = "NSI"; > > TIMESPEC "TS_CLK" = PERIOD "CLK" 3.57 ns HIGH 50 %; > TIMESPEC "TS_CLK_NSI" = FROM "CLK" TO "NSI" "TS_CLK" * 1; > TIMESPEC "TS_CLK_CLKEN" = FROM "CLK" TO "CLKEN" "TS_CLK" * 2; > > > but ISE tries to constrain the "other" logic with the carry chains to the > 280MHz clock instead of the 140MHz CLKEN domain - and timing fails. I can now answer my own question... :-) Problem is that ISE 5.2.03i will not recognise "CLKEN*" but WILL recognise "clken*" and correctly analyse the paths that use the internally generated clken. Seems ISE has a problem with case mismatches for signals specified in ucf using wildcards....ISE manages case insensitive matches for signals without wildcards though. Cheers, KenArticle: 66158
In article <c0hjkr$dqg$05$1@news.t-online.com>, Antti Lukats <antti@case2000.com> wrote: >"Austin Lesea" <austin@xilinx.com> wrot >> http://www.xess.com/ >> >> Has some very nice inexpensive platforms. These are used for >> universities, colleges, and schools. They are inexpensive enough that a >> student can buy a simple one for about the price of a textbook. >you better re-check XESS offerings, as ASFAIK they have dropped __all__ low >cost Xilinx boards. No, according to http://www.xess.com/ho04000.php3 you can still get a XC2S50 or XC2S100 board for $149 or $249 respectively. Or are you claiming they just keep the Web site up to mislead passing travellers? The difference between the XESS and the Parallax board is basically the choice between interesting peripherals and on-board large memories and multipliers; whilst DSP trickery sounds fun, I suspect it would probably be more sensible to get the board with peripherals to start with. TomArticle: 66159
Thanks for your replies, As it turned out, the main (!) problem was timing related..but simply clocking the controller and memory card with opposite clock edges seemed to solve the problem..both in simulation and hardware :) Once again many thanks for your comments, -Antti "db" <javaguy11111@yahoo.com> wrote in message news:903bda3b.0402110541.30e4d887@posting.google.com... > I did something similar several months back with a Spartan IIE. > Watch out for termination issues. In my case it appeared as > double clocking. I was able to work around it because the Spartan > allowed me to reduce the drive current and edge rise times. > Once I did that, the strange behavior I ran into during hardware > testing > went away. > > Also as mentioned in other posts, use the micron dram models and be > sure your controller works exactly as you expect in the simulator > before even thinking about trying it for real. Otherwise you are in > for a lot of frustration and head scratching. > > "Antti" <antti1000@yahoo.com> wrote in message news:<%m%Vb.8944$g4.183754@news2.nokia.com>... > > Hi, > > > > I've implemented an sdram controller on an fpga (to micron 128 MB memory) > > and tested it with a sequence of write and subsequent read bursts. In around > > 1 in 5 attempts, the correct read data appears on the dq[31..0] data bus, > > otherwise the memory read just returns 0xFFFFFFF. Could someone please give > > pointers to why might this be? > > > > Thanks, > > AnttiArticle: 66160
> The MGTs in Virtex-II Pro can receive 3.125 gigabits/sec, which means > 1.5 GHz. > And there is an easy way to bypass lots of stuff, and represent 20 > incoming bits in parallel. The rest is just design at 150 MHz. Not difficult. > > Anybody need a counter with resolution between 1.5 and 5 GHz ? YES! I really would like to use a fast Deserializer (preferably 10GHz) without clock and data recovy. Just give me sample data from the input pins in raw form in a slower parallel format. The sample frequeny should be a multiple of the local reference clock and the phase should not be pulled by input transitions. My information from about a year ago is that the Virtex-II-Pro SERDES could not be operated in a dumb mode like that. In principle this should be simpler than the usual operating mode. The question is only if there is a way to turn of all the unwanted functionality. If you have found a way to do that, please tell me. Kolja SulimmaArticle: 66161
Hi, I have a question concerning the intelligence of the compiler in QuartusII software: Of course I can use FIFO structures that can be uses as templates which only have to be instantiated. The contol logic has to be built around that template. But what if I write my own FIFO VHDL code, does the compiler "recognize" it to a certain degree and does the compiler then use memory bits instead of logic ressources? I have written my own module in which there is a fifo function with additional logic around it. But the compiler does only use logic ressources. Is there something I have to bear in mind if I want the compiler to use memory bits or even fifos ? Thank you very much Kind regards Andrés Vázquez Guntermann & Drunck System DevelopmentArticle: 66162
rickman <spamgoeshere4@yahoo.com> wrote in message news:<402C6ABD.2A9E6871@yahoo.com>... > Steve wrote: > > > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<402ABE46.861C779A@yahoo.com>... > > > > > Hey Steve, why don't you get off the soapbox. What you are doing is not > > > getting you anywhere and is starting to tick me off. Until you give a > > > call to your distributor and *ask* what price you can get, I don't want > > > to listen to your rants. > > > > So far in this thread I've been accused of not understanding > > economics, pricing or capitalism; seemingly just because I've had the > > audacity to question Xilinx's low quantity prices. Basically, if > > they're going to patronise me then I'm not going to just sit here > > quietly and take it. > > You are not making any sense. By definition X and A have an oligopoly. > So what is your point? I was responding to Peter Alfke's comments about X and A not being an oligopoly: "The Columbia Encyclopedia describes oligopoly as: ...the control of supply by a few producers...or by agreements among members of an industry to restrain price competition... Does that describe your impression of the relationship between X and A ? Wow !" > Your questions have no point. Your statments > are about the obvious. From: http://www.xilinx.com/prs_rls/silicon_spart/03142s3_pricing.htm "The 3S50, 3S200, and 3S400 Spartan-3 devices with 50,000, 200,000, and 400,000 system gates respectively, are available for less than $6.50*. The 3S1000 Spartan-3 device with 1 million system gates is also available for under $12.00*." The cheapest XC3S400 (400k gates) in small quantities here: http://www.plis.ru/price.html?ID=126 is $28.90, that's 4.45 times as expensive. The difference will narrow when production is ramped up to maximum, but how much will it narrow to? Three times the price, twice the price? > You are not telling anyone here anything they > don't already know. Oh, so you don't mind paying highly inflated prices? Fair enough. > You are just acting like a spoiled brat throwing a > tantrum because he can't have dessert. To be perfectly honest the only person ranting round here is yourself. > Are you just trolling or do you have a point? I've made my point and I can't be bothered to make it again. -- SteveArticle: 66163
Austin Lesea <austin@xilinx.com> wrote in message news:<c0g97i$f971@cliff.xsj.xilinx.com>... > Steve, > > Question away. I think the thread has allowed folks to vent a little, > and to learn why selling FPGAs is not as simple as they may have > thought. I've still not read a good reason why your highest volume products are so expensive in small quantities. The reasons that have been given up to now have been that small companies should pay the same for support costs as large customers whether or not they use the support. The simple solution to that would be to charge small companies 75 cents per minute when they ring up for support, and let the larger companies have their support unchanged. The other reason that has been given is that distributors have to earn a living. My heart bleeds for the poor loves... I believe there are ways that Xilinx could improve their service to smaller companies such as significantly increasing the number of distributors to increase competition. Peter Alfke said: "But rest assured that we are seriously looking at ways to improve the plight of the low-volume customer. Some of your complaints did not fall on deaf ears." so only time will tell, and it'll be interesting to watch the price of Spartan 3's over the next year or so... > Those that are paranoid, I am afraid we can not help. > Regardless, others benefit from an open and frank discussion. I quite > often take a mildly extreme position to help focus the discussion and to > entertain (after all, why would anyone read this stuff if it wasn't > somewhat entertaining?). Anything I have said is not to be taken as an > accusation, but rather as a challenge to explain your views (which you did). I admit accusation was too strong a word. > If I offended, I apologize, as that was never my intent. No offence taken. -- SteveArticle: 66164
Hy all! Since an view days I am using the EDK 6.1i from Xilinx. Now I tried to use their reference design "opb_ssp1_v1_00_a". It's a design for the Virtex II pro with an OPB-slave with interrupt support. But when I try to generate the bitstream, I get an error like this: - Running XST synthesis opb_core_ssp1_wrapper (opb_core_ssp1) - X:\v2p\opb_ssp1_v1_00_a\system.mhs:243 - Running XST synthesis ERROR:Xst:807 - E:/Programme/edk/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 189: arguments of 'and' operator must have sa me lengths. ERROR:MDT - HDL synthesis failed! ERROR:MDT - platgen failed with errors! Hm, I am not very familiar with VHDL and the EDK and I have no idea what to do! Thank you - DirkArticle: 66165
"Pablo Bleyer" <pbleyerN@SPAMembedded.cl> wrote in message news:402c61d2_2@nova.entelchile.net... > Hello group. > > We would like you to share with us your comments and opinions about a > product we are planning to launch. Your feedback will be very helpful to > determine the interest in this kind of product, and important to establish > its development path and features (including, of course, price, so by > helping us you may be helping yourself ;^) > > This is a low cost, low power little board (3"x2") we designed to use in our > own custom control & data acquisition projects, but the concept turned out > so nice and nifty that we are evaluating the possibility to commercialize it > as a line product. It currently has an AT91M42800A MCU from Atmel (ARM7TDMI > with an external bus), up to 1MB RAM, 1MB to 8MB Flash, integrated power > supply and a Xilinx SpartanIIe FPGA (XC2S50E or XC2S100E) with a > programmable clock oscillator. Expansion headers are provided for all > important board signals (120, including power pins), with top and bottom > stack mount capability. > > Most MCU and FPGA pins are shared to provide a flexible interfacing > architecture. The FPGA can be used for logic interfacing, data processing, > video output and LCD interface, hardware UARTs and other kind of > communications, etc. > > We would like to introduce this first as a basic kit with all the necessary > tools to get one started (core module, adapter board with serial > transceivers, wiggler-like JTAG programmers, software). The board itself is > a wonderful combo-kit for learning about embedded systems with the ARM > architecture and FPGAs. Most of the software and applications will be > provided as open source and a web site with useful information (application > notes, code and FPGA cores) will be set up. An eCos profile for the board > will be made available too. > > We also have designs for a backplane and auto-configuring add-on modules > with analog and digital IOs, Ethernet interface, IrDA and RF transceivers, > CompactFlash interface, etc. Our idea is to make them available once we can > reinvest and verify enough demand for each kind of device. > > The board can be configured for 1V-3.6V input operation using an efficient > step-up regulator, targeted mainly for battery powered applications. > Another configuration allows not installing the FPGA and using a cheap LDO > regulator for cost-sensitive applications where the FPGA is not necessary > and power efficiency is not of concern. > > You can take a look at some pre-production kit items at > http://www.embedded.cl/gallery/ARMermelator > > In particular, you would help us a lot with your answers and suggestions for > the following: > - How much will you be willing to pay for a kit like this. How much for core > boards in quantities? > - Do you think the FPGA configuration (ie, FPGA present on the board) will > be useful for you? Would you choose this board over other similar products > because of its FPGA functionality? > - Concerning the kit, do you think a base board with integrated programmers, > serial transceivers and prototyping area would be more useful to you than an > adapter board and separated programmers? > - What kind of applications and solutions to your needs do you envision > using a board like this? > - Without knowing further details, your overall impression about this > product. > > Well, thank you very much in advance. Sorry for the long post and sorry if > the content of this post sounded too much like marketing instead of > technical matters -- we are not trying to offend anyone but to help us all. > > Warmest regards. > > > -- > PabloBleyerKocik / > pbleyer /"Simplicity is prerequisite for reliability." > @embedded.cl / -- Edsger Wybe Dijkstra I think the FPGA does separate it from most of the pack, though it is still not alone. The size is quite attractive, making it lean towards a powerful minaturized mobile application. However, the FPGA is not incredibly power-efficient; some applications might require all the flip-flops, but a low-power CoolRunner variation might be something to consider. They are quite inexpensive and can fit a surprising amount of logic, I have a four-axis (8 coil) bipolar microstepping translator and driver project that so far fits into 128. The processor itself would probably be able to handle many of the tasks you would use all the flip-flops for, anyway. The CPLD also won't need to be reloaded every power cycle. I think you what need to do is identify your competitors. In this case, I think your main competitor is the Pocket PC series of devices, which get up to a full day's worth of battery life, have an integrated LCD controller and LCD, standard interfaces to memory and expansion cards, and with a 200MHz processor and 64 megabytes of RAM can be had for less than $200. Your device needs to make up its shortcomings in the display, memory, and standard interface department, by pushing the programmable device aspect and large number of high-speed user I/O. Price the device in a range where customers won't choose instead to build their own CompactFlash interface card with a CPLD, and end up with a more powerful system for less money. If you target this to engineers in a production environment, you could possibly get away with a price near $400-$500, if you have a lot of options and good support (you've also got to compete against the popular PC104 systems, and low-power options probably won't be a selling point). If you target to hobbyists, I think a $175 to $250 range would be realistic though they will always buy something cheaper if they can. Basically find a cheap ARM board and a cheap FPGA board, and add the prices together.Article: 66166
Reconfigurable Anonymous is cool...It's a new concept...I am willing to join. We Singapore has the best environment for holding international meetings...We have tropical white beaches, world class meeting facilities, places of interests...Tungsten-W and Kelvin@SG welcome you to come and experience the Asian metropolitan life...:) I will experiment a trick to tackle my design, as the top-level is really complicated... When I try active module implementation on the reconfigurable modules (which uses two separate BUFGs), there are few hundred wires on the fixed module side, basically DCM and 12 BUGs...Now I am writing a "initial" top-module for the reconfigurable modules without any of the extra DCM & 12 BUFGs...basically make a top-level with only RM and Bus Macros inside...In this way I can create the two RMs clean without any addition routing of the DCM & 12 BUFGs...Vice versa, for fixed module, I only include DCM & 12 BUFGs... Now in assembly, the conflict of routing is minimized... Kelvin "Sean Durkin" <23@iis.42.de> wrote in message news:402ba490$1@news.fhg.de... > John Williams wrote: > > Hi Sean, > > > > Thanks for your response. It confirmed a few things I was starting to > > think, but it's nice to know I'm not alone! > Us partial reconfigurators sure are a rare species. We should stick > together, or have some "RA" (Reconfigurators Anonymous) meetings some > time... :) > > > I found the problem - I had disobeyed golden rule #465 of having a > > non-module IOB "above" a module area location... I was secretly hoping > > there might be some edge-following routing resources that would let me > > get away with it, but it seems not... > Yeah, should've thought about that, I think that must've been what > caused it in my case, too... But I notice that this only produces errors > when you use ISE6. ISE5 routes the thing without warning, which of > course leaves you with a useless design. > > So did that solve the problem with the corrupt .NCD as well? > > -- > Sean Durkin > Fraunhofer Institute for Integrated Circuits (IIS) > Am Wolfsmantel 33, 91058 Erlangen, Germany > http://www.iis.fraunhofer.de > > mailto:23@iis.42.de > ([23 , 42] <=> [durkinsn , fraunhofer])Article: 66167
John Williams wrote: > Yes and no - I can generate a bitstream, but only if I turn off the DRC. > If I leave the DRC on, it generates errors (not warnings) deep in the > microblaze core, which is odd since I'm not doing anything in there.. Yes, I have that problem, too. I'm beginning to think this is normal... The FATAL_ERRORS and INTERNAL_ERRORS I get are also always inside the MicroBlaze-core, which I am not touching... > I had to put that aside and move onto some other stuff, i'll be back on > it when i get the chance. But at least I have built a modular/partial > microblaze system, so it's a proof of concept if nothing else. So, do you use EDK to generate the module with the Microblaze? If so, have you ever tried exporting the MicroBlaze-system with a flat netlist? That's another thing that will not work whatever I try, it's always got to be hierarchical, otherwise I get some error about "This forces two components to be combined into one, I will now go to hell and take you with me" or something. I would think this has something to do with equivalent registers or unused logic being optimized away, but even when I change the corresponding settings for XST/map, it still doesn't work. Not that I really mind working with a hierarchical netlist, it just takes awhile to find out how to fix the problem.... -- Sean Durkin Fraunhofer Institute for Integrated Circuits (IIS) Am Wolfsmantel 33, 91058 Erlangen, Germany http://www.iis.fraunhofer.de mailto:23@iis.42.de ([23 , 42] <=> [durkinsn , fraunhofer])Article: 66168
"Austin Lesea" <austin@xilinx.com> wrote in message news:c0h575$a6f1@cliff.xsj.xilinx.com... > http://www.xess.com/ > > Has some very nice inexpensive platforms. These are used for > universities, colleges, and schools. They are inexpensive enough that a > student can buy a simple one for about the price of a textbook. > > Austin Austin, you better re-check XESS offerings, as ASFAIK they have dropped __all__ low cost Xilinx boards. AnttiArticle: 66169
Jim Granville <no.spam@designtools.co.nz> writes: > Just to give you a target, to fully challenge the grey matter, :) > this company offers 10 digits/second ($2K), and 12 digits/second > models($3K). Could you explain what "10 digits/second" means? I have no idea... Thanks!Article: 66170
Thomas Womack <twomack@chiark.greenend.org.uk> wrote in news:Hxu*DCYcq@news.chiark.greenend.org.uk: > In article <c0hjkr$dqg$05$1@news.t-online.com>, > Antti Lukats <antti@case2000.com> wrote: >>"Austin Lesea" <austin@xilinx.com> wrot > >>> http://www.xess.com/ >>> >>> Has some very nice inexpensive platforms. These are used for >>> universities, colleges, and schools. They are inexpensive enough >>> that a student can buy a simple one for about the price of a >>> textbook. > >>you better re-check XESS offerings, as ASFAIK they have dropped >>__all__ low cost Xilinx boards. > > No, according to http://www.xess.com/ho04000.php3 you can still get a > XC2S50 or XC2S100 board for $149 or $249 respectively. Or are you > claiming they just keep the Web site up to mislead passing travellers? Yes, we continue to make and sell these boards and will for at least a few more years. Last year we halted production of some boards based on the older XC9500 CPLDs and XC4000XL FPGAs after the boards passed their five-year product lifetime. > > The difference between the XESS and the Parallax board is basically > the choice between interesting peripherals and on-board large memories > and multipliers; whilst DSP trickery sounds fun, I suspect it would > probably be more sensible to get the board with peripherals to start > with. You can always use distributed arithmetic to commit DSP trickery. Multipliers are sexy and easier to use right out of the box, but DA is still a handy technique to know and understand. > > Tom -- || Dr. Dave Van den Bout XESS Corp. (919) 363-4695 || || devb@xess.com PO Box 33091 || || http://www.xess.com Raleigh NC 27636 USA FAX:(919) 367-2946 ||Article: 66171
Hi, I'm working on a Cyclone FPGA with NIOS project, which contains an onchip bootrom. I want to use a makefile to generate the contents of this bootrom. At first I used a single .C file which worked fine, but now I'm using a makefile and I can't get it to work. Can't find anything about it in the Altera documentation or website. My makefile is very simple and only contains one line to nios-build a bunch of C files. The command I use is "make -f %2/myproject.make" but it terminates with a strange error. Anyone any experience with this? JeroenArticle: 66172
"Mainak Sen" <mainak@umd.edu> wrote in news:c0h3jg$8dr$1@grapevine.wam.umd.edu: > I was trying to load data values in the 8Mb SDRAM of the xsa-50 board. > Can someone please let me know how I can do that ? The GXSLOAD utility that XESS provides has the capability of downloading/uploading data to/from the SDRAM and Flash on the XSA Board in addition to downloading bitstreams to the FPGA. There is a section in the XSA manual (http://www.xess.com/manuals/xsa-manual-v1_2.pdf) that shows how to use GXSLOAD to download data to the SDRAM. -- || Dr. Dave Van den Bout XESS Corp. (919) 363-4695 || || devb@xess.com PO Box 33091 || || http://www.xess.com Raleigh NC 27636 USA FAX:(919) 367-2946 ||Article: 66173
I've just been going through the same process. The older parallel cable is not supported under linux in ISE 6.1. Apparently we'll have to wait for 6.2. There are some previous posts on this matter. Sorry it's only bad news Andy Fouad wrote: > Hi all, > > I have installed ISE 6.1.03i, and I can't get impact to program my > development board, using the parallel port... in the cable setup all > the options other than the serial interface is unavailable. the board > and parallel interface work under windows.. and with VMWare... Thanks > for your help > > Fouad -- Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, UK Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 433224 Web: www.bioinspired.comArticle: 66174
Hi Pablo, Interesting product. Some comments: > We would like to introduce this first as a basic kit with all the necessary > tools to get one started (core module, adapter board with serial > transceivers, wiggler-like JTAG programmers, software). The board itself is > a wonderful combo-kit for learning about embedded systems with the ARM IMHO, this board is a bit complicated for introductory embedded learning purposes. And I expect it will be a bit too expensive. You'll be competing with sub-$200 boards from Atmel and sub-$100 ARM boards based on other ARMs. Maybe it's better marketed as a poor-man's-ASIC :) > - How much will you be willing to pay for a kit like this. How much for core > boards in quantities? I would personally pay up to about $300 for the board and documentation. I wouldn't pay extra for a parallel port wiggler, etc. because I already have these tools. For "production", I would only be willing to pay around half that price for a board including FPGA. I would suggest preloading Angel or (better) RedBoot in ROM, not including JTAG tools with the appliance, and letting people use it the good old way with a serial cable. > - Do you think the FPGA configuration (ie, FPGA present on the board) will > be useful for you? Would you choose this board over other similar products > because of its FPGA functionality? The FPGA isn't directly useful to me - because I don't have enough time to use it effectively (one-man team...) But it could become useful if I could download canned applications from you - LCD controller being the application of primary interest! > - Concerning the kit, do you think a base board with integrated programmers, > serial transceivers and prototyping area would be more useful to you than an > adapter board and separated programmers? Lose the prototyping area. Bring the signals to headers. I'm not hacking stuff onto an eval board.
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