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Flash card interface is a small cup of tea... Kelvin "John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:c7ujfo$shq$1@bunyip.cc.uq.edu.au... > Hi Iwo, > > Iwo Mergler wrote: > > > I'm looking for a CF FPGA prototyping card. Do you know > > of such a beast? > > > > The closest I could find so far is the Wildcard, combined > > with a CF to PCMCIA adapter. > > I don't know of any other cards, but some second hand comments about the > Wildcard: > > Someone I spoke to recently was complaining bitterly that the WildCard's > communication interface between the FPGA and the PCMCIA bus is extremely > narrow and slow, basically he was forced to do single-byte programmed > reads/writes across that interface. Yuck. > > So, it seems to make the idea of using the Wildcard as a computational > accelerator/coprocessor pretty useless - you just re-invent the > bus-bound architecture... > > It may just be a problem with the host drivers, rather than the WildCard > architecture itself, I'm not sure. If anyone from Annapolis is reading > this it would be interesting to get clarification. > > Regards, > > JohnArticle: 69526
Hi, VHDL doesn't allow white box probing in the language and hence is this issue. Having said that, many simulators provide through their APIs a way to do this. You didn't mention which simulator(s) you are using, AFAIK NCSIM, Modelsim & Aldec supports such APIs. The down side is that your TB code tends to become simulator dependent. I recently uploaded a simple package to avoid this, you may want to take a look at that, see http://www.noveldv.com/eda/probe.zip HTH, Srinivasan "arkaitz" <arkagaz@yahoo.com> wrote in message news:c1408b8c.0405100720.26a061da@posting.google.com... > Hi all, > > This question might obvious, but I cannot find any other way to > instatiate signals from a top of a design for simulation purposses. > > What I usually do is to add those signals as ports in each entity > beginning from the bottom of the design and continuing the hierarchy > until I arrive to the top. In order not to consider them in the > synthesis I add "synthesis translate off/on" comments. > > Here you are an example: > > Imagine that I want to instantiate the internal signal of the > subblock1 from the top > > entity top is > port( > -- synthesis translate off > tb_out : out std_logic; > -- synthesis translate on > ... > ); > end top; > > architecture arch of top is > begin > > uut: subblock1 > port map( > -- synthesis translate_off > internal => tb_out, > -- synthesis translate_on > ... > ); > end; > > Then I instantiate the top in the same way from the testbench. > > I know that in verilog there is another way just with something like > this. > > "top.subblock1.internal" > > I would be glad is someone could help. > > Thanks in advance, > > Arkaitz.Article: 69527
Hi, I had posted this message earlier on comp.cad.synthesis ... but the traffic there is so low that I am not sure if enough people have seen it. I have a VHDL model where a number of nodes are talking to each other as well as a register file, using a common pair of address-data buses with requests and acks for arbitration. Each node has a single process with an FSM that governs its working. The model works correctly in ModelSim, but I face problems when synthesising. I am using the Xilinx ISE version 6.1i for this. The synthesis phase completes, but XST throws a lot of warnings like the one below: WARNING:Xst:638 - in unit top_entity Conflict on KEEP property on signal rfile_inst_Mtridata_data_bus<4> and node2_inst_Mtridata_data_bus<4> node2_inst_Mtridata_data_bus<4> signal will be lost. "node2_inst" is an instance of a component called "node2" in an entity called "top_entity". "data_bus" is an inout std_logic_vector port on the node2 entity. I had searched the newsgroups for similar problems and learned about the "equivalent_register_removal" and "keep" attributes. But the signal mentioned here, "Mtridata_data_bus" is inferred internally by the synthesiser, so I have no idea how to set these attributes on this signal! Setting this attribute for just "data_bus" doesn't seem to help. Inspite of these warnings, the synthesis phase finishes, but the "translate" phase aborts after this error from NGDBUILD: ERROR:NgdBuild:456 - logical net 'rfile_inst_Mtridata_data_bus<4>' has both active and tristate drivers I have no idea how to rectify this error. And this seems to occur only for the Virtex and Spartan FPGAs ... I tried synthesising for the CoolRunner CPLD, and everything worked out without any error. How do I address this from my VHDL code? Or is this a tool or platform specific problem? Ashant.Article: 69528
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<_Jwoc.1581$FN.172196@news02.tsnz.net>... > Fitters commonly use BLIF, PLA, or sometimes EDIF files, so try and > find the .EXE that is the fitter for your old device. > > "failed to spawn child process" could simply mean it was unable to find > the fitter, and if you can manually launch the fitter, it will work ok. The following process are ok: - Update all schematic files OK - Link design OK Linked equations OK - Fit design OK Prefit equations OK Signal cross reference OK Jedec File *** FAIL *** This is the reported message: Synario Auto-Make Log File -------------------------- Updating: JEDEC File Starting: 'C:\ISPDSPS\ISPSYN\BIN\SYNDPM.EXE -i pldhcc.tt2 -if pla -p ispLSI1032E-70LJ84 -z -of verilog -of vhdl' Received process exit status -1 Possible system problem to spawn child process Done: failed with exit code: -001. ---------------------------- I tried to execute that command line from MS-DOS, but SYNDPM does not verbose anything. Here: http://www.fpga-faq.com/archives/09650.html#9664 ...I found that someone had the same problem, but there is no answer... > Talk with lattice, they should know what these legacy fitter(s) are > called, as well as file and calling methods for command line operation. I'll try to contact them. Thank you very much FabioArticle: 69529
jon@beniston.com (Jon Beniston) writes: > > With two clocks and two write ports!? > > Ok, maybe not that particular case, but most other configurations of > dual-port RAM can be infered. In Verilog at least, isn't this a > problem with the language rather than the FPGA tools (i.e. you can't > write to the same variable from two different processes)? > :-) I'm slightly bitter - as that's just what I want to do right now... Coregen is not an option ... Grrr.. In VHDL you could maybe do it with shared variables, but I've always avoided them to avoid shooting myself in the foot! > > Open-source doesn't *have* to mean no-cost... > > Sure. I was more refering to that fact that due to the quality & size > of some open source/free software projects, the bar has been raised > significantly. > OK.. I thought you were saying that releasing software as either free or open-source implies you can't get revenue from it. There are an enormous number of people managing it though! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 69530
nospam wrote: > hi, is there any Virtex-II Pro (with only one PPC core embedded, > XC2VP4-5FG456C), the clock, config ROM, JTAG (maybe also USB) and some RAM > board out there? > > cause i've seen some cards from Memec (there's one at about 400dollars with > EDK and 200 without it), but they dont have any RAM, I have the "Virtex-II Pro Development Board" from Insight Memec (Rev3), and it has 32MB SDRAM... No USB though, only UART. cu, SeanArticle: 69531
Ashant wrote: > <snip> > ERROR:NgdBuild:456 - logical net 'rfile_inst_Mtridata_data_bus<4>' > has both active and tristate drivers > > I have no idea how to rectify this error. And this seems to occur only > for the Virtex and Spartan FPGAs ... I tried synthesising for the > CoolRunner CPLD, and everything worked out without any error. > > How do I address this from my VHDL code? Or is this a tool or platform > specific problem? Hi Ashant, it is difficult to diagnose this without seeing the code. I would guess that there is a little mistake in your code. When you describe busses and you synthesize it for a PLD, this is usually mapped into a MUX/DMUX structure (PLDs do not have tristatable drivers). Most FPGAs (so the Virtex) have tristatable drivers and can handle real busses. So you should check first whether the bus you have in your design is properly described. I.e. under some condition you assign a value, and under other conditions you assign a 'Z' (for each part that is driving something onto the bus). Another explanation could be that these inferred "rfile_inst_Mtridata_data_bus", etc. signals are the actual driver controls (enable signals) and are for some reasons set to "always active". This would also explain the ngdbuild error you are receiving later. You say that the synthesis for a CoolRunner CPLD worked fine. Have you simulated and verified the backannotated design? Regards, MarioArticle: 69532
> I have the "Virtex-II Pro Development Board" from Insight Memec (Rev3), > and it has 32MB SDRAM... No USB though, only UART. Forgot the URL: http://tinyurl.com/23zou This is a never rev than the one I have, but with the same features. cu, SeanArticle: 69533
Hi Steff, Thanks a lot for your help. I'm sorry about the posting mistake. I didn't know that there was a specific forum for VHDL. Arkaitz. > See the following links. They show you simulator dependent and > independent solutions. > > <http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#monitor> > > <http://tinyurl.com/2gyo2> > > <http://tinyurl.com/3h83e> > > And please post further VHDL questions to comp.lang.vhdl. > > I hope this solves your problem :-) > > Tschoe, > SteffArticle: 69534
Earlier the Xilinx ISE distribution included a CAE Libraries CD. This CD contained Synopsys Design Compiler libraries (.db files) which were installed under $XILINX/synopsys/libraries/syn/. But now I can't seem to find any Synopsys .db files in ISE 6.2i. Can I download these from the Xilinx Web site or order a CD? It's not a problem for Virtex-II/Pro and Spartan-III where Synopsys provide libraries with Design Compiler FPGA (BTW a great synthesis tool, especially if you are used to DC for ASIC design). Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 69535
John Williams wrote: > Hi Iwo, > > Iwo Mergler wrote: > >> I'm looking for a CF FPGA prototyping card. Do you know >> of such a beast? >> >> The closest I could find so far is the Wildcard, combined >> with a CF to PCMCIA adapter. > > > I don't know of any other cards, but some second hand comments about the > Wildcard: > > Someone I spoke to recently was complaining bitterly that the WildCard's > communication interface between the FPGA and the PCMCIA bus is extremely > narrow and slow, basically he was forced to do single-byte programmed > reads/writes across that interface. Yuck. > > So, it seems to make the idea of using the Wildcard as a computational > accelerator/coprocessor pretty useless - you just re-invent the > bus-bound architecture... > > It may just be a problem with the host drivers, rather than the WildCard > architecture itself, I'm not sure. If anyone from Annapolis is reading > this it would be interesting to get clarification. > > Regards, > > John John, thanks for the input. I'm mainly interested in transferring a stream of data at 500KByte/sec, with tough real-time constraints. With current hand-held/laptop devices the choice seems to be USB1.1 or CF. USB1.1 is pretty much at its limit with this. It works, but I have to use 8MB of buffer memory to cover the times when the OS decides to go away and do something else for a few seconds. I was hoping to use some sort of DMA transfer via CF, to move that buffer memory into the main memory and stop the OS from interfering. Kind regards, IwoArticle: 69536
Student wrote: > Flash card interface is a small cup of tea... > > Kelvin > Yes, and I'm trying to design a better teabag. ;^) IwoArticle: 69537
Fabio G. wrote: > Jim Granville <no.spam@designtools.co.nz> wrote in message news:<_Jwoc.1581$FN.172196@news02.tsnz.net>... > > >>Fitters commonly use BLIF, PLA, or sometimes EDIF files, so try and >>find the .EXE that is the fitter for your old device. >> >>"failed to spawn child process" could simply mean it was unable to find >>the fitter, and if you can manually launch the fitter, it will work ok. > > > The following process are ok: > - Update all schematic files OK > - Link design OK > Linked equations OK > - Fit design OK but presumably there is no .JED file at this stage ? > Prefit equations OK > Signal cross reference OK > Jedec File *** FAIL *** > > This is the reported message: > > Synario Auto-Make Log File > -------------------------- > > Updating: JEDEC File > > Starting: 'C:\ISPDSPS\ISPSYN\BIN\SYNDPM.EXE -i pldhcc.tt2 -if pla -p > ispLSI1032E-70LJ84 -z -of verilog -of vhdl' Some educated guesses based on other fitters I've used : SYNDPM.EXE is the lattice fitter (it may need some library files) -i pldhcc.tt2 -> Input file is PLA format pldhcc.tt2 ( your compiled design ) -if pla -> confirms format, ( may also allow EDIF or BLIF options) -p ispLSI1032E-70LJ84 -> Physical device/package to target FIT to -z -> ? -of verilog -> output format If you are getting a .TT2 file, all your sources are compiling/reducing to boolean eqns OK, you just need to get the fitter to co-operate :) It is the right version fitter ? > > Received process exit status -1 > Possible system problem to spawn child process > Done: failed with exit code: -001. > ---------------------------- > > I tried to execute that command line from MS-DOS, but SYNDPM does not > verbose anything. I do not have syndpm.exe, but with Atmel's fitters fit15xx.exe gives a short help list fit15xx.exe -h2 gives a full help list fit15xx.exe -h2 >Fit15xx.TXT dumps that help to the .TXT file (etc) if theirs does not give help from blank command line, you could trawl the .EXE in a file viewer - eg to check your SYNDPM version is correct for your device, verify you can find target ispLSI1032E-70LJ84 inside the .EXE move your .PLA to the fitter/fitlib dir, and try simpler command lines. Well behaved fitters SHOULD be able to take a PLA file, and create a JED with a minimal command line. -jgArticle: 69538
> Most FPGAs (so the Virtex) have tristatable drivers and can handle > real busses. As I remember there are no real tristate signals any more in Xilinx FPGAs because they were too slow ... real tristate is only in the IOBs in the FPGA there are structures that *simulate* a tristate behaviour (for backward compatibility) but they can't be used for bidirectional busses ... I guess you described something like a bidirectional tristate bus and the synthesis-tools can't handle that properly ... bye, MichaelArticle: 69539
Michael, >> Most FPGAs (so the Virtex) have tristatable drivers and can handle >> real busses. > > As I remember there are no real tristate signals any more in Xilinx > FPGAs because they were too slow ... real tristate is only in the IOBs > > in the FPGA there are structures that *simulate* a tristate behaviour > (for backward compatibility) but they can't be used for > bidirectional busses ... No, according the data sheets describing the architecture this is wrong. VirtexII devices have two tristate buffers per CLB and they provide according tristatable connection lines as well. It is written in the data sheet: The 3-state buffer logic is implemented using AND-OR logic rather than 3-state drivers, so that timing is more predictable and less load dependant especially with larger devices. (Virtex-II Functional Description (Module 2), page 20) Perhaps this has confused you. No matter how Xilinx implemented this physically, the direct support of tristatable (and hence bidirectional) busses is there. Regards, MarioArticle: 69540
"Joe" <joe_y@invalid_address.nospam.com> wrote in message news:c7uafp$5cl$1$830fa17d@news.demon.co.uk... > Tom Hawkins wrote: > > > What can we do to improve open-source EDA? > > > > Regards, > > Tom > > > > For me, and I guess for a lot of people in this industry, contribute to > open source could be a legal minefield: > > - In my job contract, it stated my employer own the copyright of designs > I done. So officially I cannot post any IP design/source code to public. > Depending on the sort of work you do, it can sometimes be directly economically benificial for your employer if particular code is released as open source (for example, if you release something that other people will use and enhance, you get the benifits of their enhancements). Everything you write for your employer is owned by them, and in some contracts that also includes things you write in your own time that are related to your job (I guess this is some sort of protection against you moonlighting), but if you want to release some code as open source, you can always ask your employer for permission. > - Patent issues. Some of my knowledge might relate to patented products. > Release of such information could mean I could get sued. That can be a problem, as can NDAs and other such red tape. > > And of course, usually I am too tired after work anyway ;-) And that is invariably a problem :-( > > Joe > > >Article: 69541
Hi I am struggleing with the bootcode. I have compressed the hardware image to half the size with the buildin tool. Now I want to compress the SW image. How can I do this? Can it be done from within Quartus II or must I do it in some other way? Hope u can help Thanks upfront GreateWhite.DKArticle: 69542
Dave wrote: > Thanks, Sean. But, the base address and length seem to be specified > multiple places. The base address shows up once in the linker script > and the length shows up twice (!) in the linker script. Also, the > base is in the .pbd file as well. Is there one centralized place to > set these parameters? I don't think so. EDK, at least in version 3.2, does not handle linker scripts at all. That is, you can specify one, but changes you make to the design will not be ported to the linker script. So the linker script you'd have to change yourself. The information in the .pbd is mostly irrelevant, since that is regenerated every time you reopen the project. Important is what's in the .MHS-file, that's the basis for generating the .pbd. So, you'd have to change the MHS and the linker script, I guess. cu, SeanArticle: 69543
"GreateWhite.DK" <mse@ect.dk> wrote in message news:40a37e22$0$459$edfadb0f@dread14.news.tele.dk... > Hi > > I am struggleing with the bootcode. I have compressed the hardware image to > half the size with the buildin tool. Now I want to compress the SW image. > How can I do this? Can it be done from within Quartus II or must I do it in > some other way? > > Hope u can help > Thanks upfront > GreateWhite.DK > > I assume you mean that you want to store your Nios firmware in the EPCS config chip using the compressed bitstream facilities? Well, I don't have the answer, but I'd like to do the same thing. :) I'm using an EPCS4 with a compressed HW image and uncompressed firmware. It's not quite enough room for all of my firmware, but if I could compress it, it would fit. I don't see any API in the ASMI interface to access compression. I could do my own compression, but since I have another serial flash chip on my board I just use that. In a few months Altera will be shipping EPCS16 and EPCS64 config chips with lots more room. Still it would be nice to have an ASMI interface to compress/decompress. Perhaps with Nios II? :) KenArticle: 69544
Hi, I'm using a Altera Cyclone 1C6 which contains a Nios. The FPGA is configured by an EPCS4. I want to store the firmware for the NIOS in the config device. This should be possible using ASMI. The problem is that I can't store the HEX file into the programming file for the configuration device. With Quartus, this should be done by converting the SOF file into a POF, and then insert the HEX file into the 'Main Block Data' area. This doesn't work, the contents of the HEX file are not included in the resulting POF. (The POF should in turn be converted into a RPD file, which can be programmed into the EPCS4 using a JAM/STAPL player). There are two modes for the HEX file, absolute and relative addressing. With absolute addressing I get a warning that it's overwriting parts of the SOF, but it actually places the data aligned to the end of the configuration file, e.g. the HEX file doesn't immediately follow the FPGA config data (I use nr_asmi_past_config() function to find out where the app code is). With relative addressing, there's no data at all. Is this a bug in Quartus 4.0 or am I doing something totally wrong?? JeroenArticle: 69545
Quartus can only compress the SOF file, but if your bootloader software is stored in on-chip memory, the software is compressed as well, as it's part of the configuration of the FPGA. "GreateWhite.DK" <mse@ect.dk> schreef in bericht news:40a37e22$0$459$edfadb0f@dread14.news.tele.dk... > Hi > > I am struggleing with the bootcode. I have compressed the hardware image to > half the size with the buildin tool. Now I want to compress the SW image. > How can I do this? Can it be done from within Quartus II or must I do it in > some other way? > > Hope u can help > Thanks upfront > GreateWhite.DK > >Article: 69546
"Jeroen" <sink@null.dev> wrote in message news:40a386c6$0$562$e4fe514c@news.xs4all.nl... > Hi, > > I'm using a Altera Cyclone 1C6 which contains a Nios. The FPGA is configured > by an EPCS4. I want to store the firmware for the NIOS in the config device. > This should be possible using ASMI. The problem is that I can't store the > HEX file into the programming file for the configuration device. With > Quartus, this should be done by converting the SOF file into a POF, and then > insert the HEX file into the 'Main Block Data' area. This doesn't work, the > contents of the HEX file are not included in the resulting POF. (The POF > should in turn be converted into a RPD file, which can be programmed into > the EPCS4 using a JAM/STAPL player). > > There are two modes for the HEX file, absolute and relative addressing. With > absolute addressing I get a warning that it's overwriting parts of the SOF, > but it actually places the data aligned to the end of the configuration > file, e.g. the HEX file doesn't immediately follow the FPGA config data (I > use nr_asmi_past_config() function to find out where the app code is). With > relative addressing, there's no data at all. > > Is this a bug in Quartus 4.0 or am I doing something totally wrong?? > > Jeroen > > Big day for Cyclone config! I'd like to know the answer to your question as well, but here is what I did. I used the ASMI interface to write a loader that stores a SRECords in the EPCS4 and loads and runs this stored firmware on boot. SREC format is trivial and even I was able to get it going in less than a day. KenArticle: 69547
jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0405121132.2e45e653@posting.google.com>... > > With two clocks and two write ports!? > > Ok, maybe not that particular case, but most other configurations of > dual-port RAM can be infered. In Verilog at least, isn't this a > problem with the language rather than the FPGA tools (i.e. you can't > write to the same variable from two different processes)? Verilog does not have this restriction. I've searched the LRM and I've run testcases through two reputable implementations without complaints (ncverilog, icarus). Hence my frustration. We can precisely describe a dual port block-ram in Verilog, yet the tools draw a blank. We can even preset RAMs with values, but most, if not all, completely disregard initial statements. Given the size of their development staff and the prices they are able to charge, how can they still ignore important parts of the language standard? -Tom > > > Open-source doesn't *have* to mean no-cost... > > Sure. I was more refering to that fact that due to the quality & size > of some open source/free software projects, the bar has been raised > significantly. > > Cheers, > JonBArticle: 69548
Hi, I am currently trying to update a EDK 3.2 project file to a EDK 6.1 project file. I am using the following procedure and receiving the following error message. Any ideas would be greatly appreciated. Procedure: 1: run rev32to61 utility on project file. Errors: Can't open perl script C:\EDK\\bin\nt\edk_instname_revup.pl": No such file or directory WARNING:MDT - Some of the instance names in your design had same name as the IP. Revup changed those instance names in MHS and MSS files. Revup also changed your c source files where any macros and variables defined in xparameters.h were referred to. If your are referring to these instance names in UCF or BMM file, please change those references yourself. ERROR:MDT - Error while reving up instance names I have searched the entire computer and can not find the perl script it is looking for. I have even tried reinstalling the software:( Thanks in advance, WinstonArticle: 69549
Hi, I am trying to update a XILINX EDK 3.2 project file to a EDK 6.1 project file. I tried using the revup32to61 utility that is included; however, I receive the error message posted below. The PERL file that this utility is looking for is no where to be found. I have tried searching both EDK installation disk and the entire hard-disk; howver, the file is not on either. Thanks in advance. Error Message: -------------- Can't open perl script "C:\EDK\\bin\nt\edk_instname_revup.pl": No such file or directory WARNING:MDT - Some of the instance names in your design had same name as the IP. Revup changed those instance names in MHS and MSS files. Revup also changed your c source files where any macros and variables defined in xparameters.h were referred to. If your are referring to these instance names in UCF or BMM file, please change those references yourself. ERROR:MDT - Error while reving up instance names
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