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Hi all, I cann't do the math problems, such as: sin, cos... Our condition is as follows: At president, we are doing some tests using Virtex-II Pro50 and Xilinx Platform Studio of EDK 6.3i on Windows XP OS. The processor we are using is Microblaze. when we add the function of "sin" in the programme, and the errors when we "build all users applications" are as follows: double s; s=sin(0.222250); mb-ld: region ilmb_cntlr is full (TestApp/executable.elf section .text) mb-ld: region ilmb_cntlr is full (TestApp/executable.elf section .text) mb-ld: section .rodata [00000000 -> 00000327] overlaps section .text [00000000 -> 00004a1f] mb-ld: section .data [00000328 -> 0000035b] overlaps section .text [00000000 -> 00004a1f] mb-ld: section .sdata [0000035c -> 00000363] overlaps section .text [00000000 -> 00004a1f] make: *** [TestApp/executable.elf] Error 1 Do anybody knows what's the problem is then? Thank you very much for your help and kind-hearted! LinaArticle: 84251
Hello I have a design based on an Apex20K400E which uses the AltClockBoost to generate a 48MHz output clock from a 60MHz source. My problem is that I need a very low jitter and the best I can achieve is around +/-400ps. The datasheet gives two numbers for the generated clock jitter: either 200ps, or 0.35% of the generated period (that would be 73ps). How can I obtain such results? NicolasArticle: 84252
praveen.kantharajapura@gmail.com wrote:
>Hi,
>
>Any particular reason for suggesting cpol=cpha= '0'.
>
Because is more likely to came across a chip with this configuration.
Aurash
>
>In some of the docs i have read that cpha='1' is generally suited for
>single master single slave applications , i am not able to figure out
>why??
>
>Any comments on this!!
>
>Thanks in advance,
>Praveen
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 84253
Lina,
This is not a "problem", your software doesn't fit into your memory (to
big) , try to increase the memory, or use external memory (SDRAM, DDR)
Aurash
Lina wrote:
>Hi all,
>
>I cann't do the math problems, such as: sin, cos... Our condition is as follows:
>
>At president, we are doing some tests using Virtex-II Pro50 and Xilinx Platform Studio of EDK 6.3i on Windows XP OS. The processor we are using is Microblaze.
>
>when we add the function of "sin" in the programme, and the errors when we "build all users applications" are as follows:
>
>double s; s=sin(0.222250);
>
>mb-ld: region ilmb_cntlr is full (TestApp/executable.elf section .text) mb-ld: region ilmb_cntlr is full (TestApp/executable.elf section .text) mb-ld: section .rodata [00000000 -> 00000327] overlaps section .text [00000000 -> 00004a1f] mb-ld: section .data [00000328 -> 0000035b] overlaps section .text [00000000 -> 00004a1f] mb-ld: section .sdata [0000035c -> 00000363] overlaps section .text [00000000 -> 00004a1f] make: *** [TestApp/executable.elf] Error 1
>
>
>
>Do anybody knows what's the problem is then?
>
>Thank you very much for your help and kind-hearted!
>
>Lina
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 84254<praveen.kantharajapura@gmail.com> wrote in message news:1116243180.554447.266830@o13g2000cwo.googlegroups.com... > Hi, > > Any particular reason for suggesting cpol=cpha= '0'. It's common. > > In some of the docs i have read that cpha='1' is generally suited for > single master single slave applications , i am not able to figure out > why?? > Any comments on this!! Not really. To me either seems equally suited. Do these docs suggest that cpha='0' is somehow less suited or are you reading that into them? > > Thanks in advance, > Praveen >Article: 84255
praveen.kantharajapura@gmail.com wrote: > Hi, > > Any particular reason for suggesting cpol=cpha= '0'. > > In some of the docs i have read that cpha='1' is generally suited for > single master single slave applications , i am not able to figure out > why?? > Any comments on this!! > > Thanks in advance, > Praveen Most simple logic ICs are sensitive to the raising clock edge. If you want to read a TTL shift register, data changes on the rising clock edge so you better sample on the falling one. Thus cpha=1. Regards, IwoArticle: 84256
"Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:d5vvg2$30d3@cliff.xsj.xilinx.com... > Fred wrote: >> "AVG" <hse00045@fh-hagenberg.at> wrote in message >> news:d7206b46299a6e210db5611bcf733a3d@localhost.talkaboutelectronicequipment.com... >> >>>Hi, >>> >>>I am using Oregano's mc8051 IP Core on a Altera Cyclone II FPGA (EP2C35) >>>Board with great success. >>>I have synthesized this core many times with Quartus (several procets). >>>The occupied area is about 12%, fmax is about 20 MHz. >>> >> For my own interest I've tried fitting the core to a Xylinx device, an >> XC3S200-PQ208 and it won't fit: >> >> Number of Slice Flip Flops: 566 out of 3,840 14% >> Number of 4 input LUTs: 4,562 out of 3,840 118% >> (OVERMAPPED) >> Logic Distribution: >> Number of occupied Slices: 2,356 out of 1,920 >> 122% >> (OVERMAPPED) >> Number of Slices containing only related logic: 2,284 out of >> 2,356 96% >> Number of Slices containing unrelated logic: 72 out of >> 2,356 3% >> *See NOTES below for an explanation of the effects of unrelated >> logic >> Total Number 4 input LUTs: 4,669 out of 3,840 121% >> (OVERMAPPED) >> Number used as logic: 4,562 >> Number used as a route-thru: 107 >> Number of bonded IOBs: 156 out of 141 110% >> (OVERMAPPED) >> IOB Flip Flops: 47 >> Number of MULT18X18s: 1 out of 12 8% >> Number of GCLKs: 1 out of 8 12% >> >> It may be ISE but I can't seem to make a symbol either? > > It's not ISE, it's your selection of a Spartan-III part. You can't compare > a EP2C35 device (33,216 LUTs/475 IOs) to a 3S200-PQ208 (3,840 LUTs/141 > IOS). > The part that you selected was 10% the size of the other part!!! > > The OP said the EP2C35 was about 12% used which is about 4K LUTs. This > isn't too far off from your report. > > Select a larger Spartan-III part with more IOs (at least 156 per your > report) > and it should go through without a problem. > > Ed Many thanks. I was a bit disappointed that I couldn't create a symbol and then leave off the bits I didn't want such as serial comms etc. Otherwise I accept your points, just that it makes for an expensive processor.Article: 84257
"B. Joshua Rosen" <bjrosen@PleaseDontSpamMEpolybus.com> wrote in message news:pan.2005.05.15.11.54.37.465174@PleaseDontSpamMEpolybus.com... > On Sun, 15 May 2005 04:57:06 +0000, Ronald H. Nicholson Jr. wrote: > >> Are there any FPGA design tools which will run under Mac OS X? >> >> I've found that the Icarus Verilog simulator and synthesis tool >> will run under OS X, but I'm not sure whether that's actually useful >> for programming any current FPGA part. >> >> Thanks. > > Get yourself a Linux machine (x86 obviously, not Linux on PPC) to run your > FPGA development environment. You can use the Mac as an X-Server, but > thats as close as you are going to be able to get. It's inconceivable that > the FPGA or CAE companies would add a third platform. What you mean like windows , linux and solaris ? (Most current tools don't support solaris) Shouldn't take to much work to go from linux to OSX (depending on how they implemented the port) I'd be happy to beta test. It is interesting to see some work starting to be done with eclipse and the GEF(graphical Editing Framework). see http://www.eclipse.org/gef/overview.html?cvsroot=Tools_Project AlexArticle: 84258
Candida Ferreira wrote: > NAND and NOR functions by themselves can be used to describe any other > function, including NOT, ZERO and ONE. But, for instance, the 3-multiplexer, > which is also by definition an ULM, can not by itself describe a NAND gate > as it is unable to create a NOT gate. But there are other functions that > behave exactly like NAND or NOR gates in the sense that, by themselves, they > can also describe any other function. Do such functions have a name? I think > there is something special about them and I would like to distinguish them > from the ordinary ULMs. I don't follow. Multiplexers are as complete as any logic element. I'm not sure what you mean by a 3-multiplexer, but I will assume you mean a 2 input mux with a single control input. You can get a NOT function by putting a 1 on the I0 input and a 0 on the I1 input and your signal on the sel input.Article: 84259
Candida Ferreira wrote:
> NAND and NOR functions by themselves can be used to describe any other
> function, including NOT, ZERO and ONE.
True. NCR once produced a computer using only NAND gates.
> But, for instance, the 3-multiplexer,
> which is also by definition an ULM, can not by itself describe a NAND gate
> as it is unable to create a NOT gate.
A four to one mux can make any boolean function of two variables.
The mux selector takes the two inputs and the mux inputs
become a function code.
> But there are other functions that
> behave exactly like NAND or NOR gates in the sense that, by themselves, they
> can also describe any other function.
A NAND or NOR is the simplest case, but requires multiple instances.
A 4:1 mux is the simplest complete case for two inputs.
There are cases in between and redundant cases,
but those are not very interesting.
> Do such functions have a name? I think
> there is something special about them and I would like to distinguish them
> from the ordinary ULMs.
Not in digital electronics. Do some research on "Lattice Theory"
-- Mike Treseler
Article: 84260
"rickman" wrote:
> I don't follow. Multiplexers are as complete as any logic element.
> I'm not sure what you mean by a 3-multiplexer, but I will assume you
> mean a 2 input mux with a single control input. You can get a NOT
> function by putting a 1 on the I0 input and a 0 on the I1 input and
> your signal on the sel input.
That's true and does not contradict the definition of a ULM, but you need
the 1 and the 0 to create a NOT. Without them you cannot create a NOT with
the 3-multiplexer. But there are other functions, such as the NAND and the
NOR functions that, by themselves, can create any other function, without
needing the NOT, the ZERO and the ONE. These are the ULMs I want to
distinguish from the more ordinary ones.
Candida
---
Candida Ferreira, Ph.D.
Chief Scientist, Gepsoft
http://www.gene-expression-programming.com/author.asp
GEP: Mathematical Modeling by an Artificial Intelligence
http://www.gene-expression-programming.com/gep/Books/index.asp
Modeling Software
http://www.gepsoft.com/gepsoft/
Get APS 3.0 Std free with the book!
Article: 84261Hi, thanks. The reference designs look nice. regards, BenjaminArticle: 84262
Alex Gibson wrote: > "B. Joshua Rosen" <bjrosen@PleaseDontSpamMEpolybus.com> wrote in message > news:pan.2005.05.15.11.54.37.465174@PleaseDontSpamMEpolybus.com... > > > > Get yourself a Linux machine (x86 obviously, not Linux on PPC) to run your > > FPGA development environment. You can use the Mac as an X-Server, but > > thats as close as you are going to be able to get. It's inconceivable that > > the FPGA or CAE companies would add a third platform. > > What you mean like windows , linux and solaris ? > (Most current tools don't support solaris) > > Shouldn't take to much work to go from linux to OSX > (depending on how they implemented the port) ModelSim runs under a wish shell on Windows and Linux and Solaris, so it seems to me that the port would be rather painless. Of course, look how long it took Mentor and Xilinx to support Linux. > I'd be happy to beta test. So would I. -aArticle: 84263
"Luke Darnell" <luke.darnell@g2microsystems.com> wrote in message news:ee8e47d.-1@webx.sUN8CHnE... > Our current design uses clock swallowing to obtain lower frequency clocks. I'd like to implement this clocking behaviour (while still maintaining the phase relationahip between the clocks) inside a VIRTEX4 but don't know if this is possible. For example: > > I input a 44MHz clock. > > I generate a 22MHz clock with 25/75 duty cycle by gating every second 44MHz pulse. > > How can I maintain the phase relationship between the new 22Mhz clock and the origianl 44MHz clock ?? > > All the clock divide options of the DCM's and PMCD's will have 50/50 duty cycle outputs. Is there no method of obtaining a divided phase aligned non 50/50 duty cycle clock? > > regards, Luke darnell Hi Luke, So, whatever you do, don't gate the clock in the fabric. It's _bad_. Search this group to find out why. I'd suggest, for stuff inside the FPGA, you should use your 44 MHz clock with an enable every other clock. If you want to send a 22MHz clock out of the FPGA, use this enable with the double data rate registers (search for DDR) in the IOBs to get what you want. If your input clock has a bad duty cycle a DCM could clean this up before the DDR. Have fun swallowing, Syms.Article: 84264
Generally when you want to test your code whether it is FIFO or anything else you would usually like to start by testing the HDL design as it run much faster and help eliminating all the logic issues. The use of Behavioral FIFO don't mean you should not use later the Vendor FIFO as if you find the vendor to give better FIFO go ahead and use it The use of Behavioral FIFO (which MUST be working with similar way to the FIFO you will later use meaning if the input address is sampled the same should happen in the behavioral and so on) is in order to get your logic design tested quickly, as running test on netlist is generally speaking very slow not to mention harder to debug as some nets might be renamed and counter are now become separate FF's which you need to group and so on. Once your HDL testing is done you should run post place and route with timing information (sdf file) which will verify that the design work also with all the timing as well as that your RTL was synthesis and optimized correctly. To get into overflow and underflow condition in large fifo you can "play" with the pointer like starting them in certain value or forcing them at some point to certain value or simple use a smaller fifo. Obviously the preferred way is not touch anything and simple run the test for enough time to get into overflow and underflow (and random the clock to get as much senario as possiable). If for example your FIFO can handle let say 100ppm and is deep enough so cells/frame never cause an underflow or overflow and you want to verify that if from some reason this does happen your code is robust enough than simple change your clock's to be with "bigger ppm". This by the way should be done not only for FIFO but basically for any design you do, meaning first test it with HDL code and only than with the netlist. Have fun.Article: 84265
I'm not aware of any book that gives good explanation however I can suggest a simple solution. Write a simple code and I do mean simple like 2 bit counter or something like this which you know how the logic should have been done if you had to draw it using gates and FF's. Now synthesis and place and route it and open the floorplaner or fpga editor or even better both and see that you recognize what it what and so on. Than try to move it to be where you want it to be and see what was added to the constrain editor (Once you move thing around you can ask the tool to save the needed constrain in the constrain file) Look on the constrain file and see if it make sense to you. Now come the fun part, try remove some of those constrain and see what happen. As you will notice some constrain are nice but not necessarily needed at least on many case while other do. Now that you feel more comfortable make another simple design like maybe state machine with 2 bits or something else, synthesis place and route and see what you got. Than add constrain to put the FF for example where you want and than synthesis and place and route it and see if they moved to the place you ask them to move. Only after you got comfortable with the small design go the your main design as in big design you have so much wiring going all over as well as less space to move thing not to mention when you move one thing you might be hurting something else and than need to fix another problem and before you know you will see that sometime to fix one problem you need to generate two new and fix them as well. You might want also later to play with logic lock to tell the tool in what area to put your state machine and so on, but always try it first with small design where you can see what happen and not get "overwhelmed" due to other part which make it difficult to figure what it what and where until you get accustom. Have fun.Article: 84266
Simon Peacock wrote: > When you need to worry about floor planning.. you had better have a PhD. > Its one of the black arts when you are concerned about arrival times ... its > far better to let the tools do it for you in most cases, but there are > occasions where the tools fall flat but then you only fix the fault not > place the whole design. Flooplanning is a lot of PCB layout, except instead of ICs you have lots of logic blocks. And if your design entry is an HDL, then oftentimes those logic blocks have arbitrary reference designators and netnames, which makes correlating the logic to its function rather difficult. Anyways, my point is that PhDs don't do PCB layout. Having seen the results of a PhD's layout, there's a real good reason for that! As others have said, layout is a visual process that requires a knack. You've either got it or not. (Cue: "My Sharona") -aArticle: 84267
"B. Joshua Rosen" <bjrosen@PleaseDontSpamMEpolybus.com> writes: > On Sun, 15 May 2005 04:57:06 +0000, Ronald H. Nicholson Jr. wrote: > > > Are there any FPGA design tools which will run under Mac OS X? > Get yourself a Linux machine (x86 obviously, not Linux on PPC) to run your > FPGA development environment. You can use the Mac as an X-Server, but > thats as close as you are going to be able to get. It's inconceivable that > the FPGA or CAE companies would add a third platform. Well, Java could could be the common platform for the rest of the world. MB -- Michel BILLAUD billaud@labri.fr LABRI-Université Bordeaux I tel 05 4000 6922 / 05 5684 5792 351, cours de la Libération http://www.labri.fr/~billaud 33405 Talence (FRANCE)Article: 84268
Hi,
MicroBlaze has now an optional integrated single precision FPU.
Depending on your performance and precision needs this might help you tremendously.
You only need to enable the FPU in MicroBlaze and compile your C code.
Göran
Stanley wrote:
> Dear Gurus,
>
> I've few concerns from the given function.
>
> 1. Do I necessary have to re-implement the data-type from float/double
> to integers? I found it's difficult to re-scale the coefficients into
> integers for this particular polynomial, since the range is fall
> between 35333307.73 and 0.014726741 (to keep the precision at least 7
> decimal places), and the integer for my machine can only support
> 4bytes. How will the typical designer do to overcome this problem?
>
>
> 2. I've found several 3rd party tools that particularly focus on this
> field of application, e.g. Starbridge Inc. Viva, Mitrion-C, Celoxica-C,
> ImpulseC...etc. Do they really can optimize the software design into
> hardware design automatically without the tedious conversion? Or
> alternatively, Matlab combines with Xilinx's system generator,
> Accelchip, Xilinx core_gen (free)...etc. Which of them is the most
> cost-effective for my case? Kindest thanks for your feedback!
>
>
> Any help will be very appreciate!
>
> // x is fall within a range of 0.0 to 10.0
> float j1(float x)
> {
> float ax,z;
> double xx,y,ans,ans1,ans2;
> if ((ax=(float)fabs(x)) < 8.0) {
>
> y=x*x;
> ans1=x*(35333307.73+y*(-3855009.392+y*(118357.8384
> +y*(-1451.470429+y*(7.668204395+y*(-0.014726741))))));
>
> ans2=70666615.43+y*(1123308.192+y*(9073.879268
> +y*(48.55831735+y*(0.184081611+y*4.8828125e-4))));
> ans=ans1/ans2;
>
>
>
> } else {
> z=(float)8.0/ax;
> y=z*z;
> xx=ax-2.356194491;
> ans1=1.0+y*(0.183105e-2+y*(-0.3516396496e-4
> +y*(0.2457520174e-5+y*(-0.240337019e-6))));
>
> ans2=0.04687499995+y*(-0.2002690873e-3
> +y*(0.8449199096e-5+y*(-0.88228987e-6
> +y*0.105787412e-6)));
> ans=sqrt(0.636619772/ax)*(cos(xx)*ans1-z*sin(xx)*ans2);
> if (x < 0.0) {
> ans = -ans;
> }
> }
>
> return (float)ans;
> }
>
>
>
> best regards,
>
> Stanley
>
Article: 84269JJ wrote: > [snip] > > I wonder how much demand there would be for a realy slick and > commercial FPGA layout tool that had at least a basic model of the LUTs > and wiring delays that could be correlated with actual devices. I have > some ideas on this but other projects come 1st. > > > johnjakson at usa dot com The Guys at HierDesign thought so. They came up with a product called "PlanAhead" which now belongs to Xilinx. see: http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=dr_dt_planahead or http://www.hierdesign.com/Article: 84270
FPGA Engineer Necessary Skills =B7 Responsible for implementing DSP functional block in FPGA from conception through HDL to production. Must have working knowledge of Xilinx FPGA (Virtex-II Pro), HDL Verilog entry, synthesis, simulation, timing analysis, and EDA tools in Linux. Additional Skills- =B7 Have ASIC/FPGA design experience with MPEG-2 audio (AC3, MUSICAM) and video processing blocks (VLD, VLE, DCT, IDCT, Q, IQ), and understanding MPEG-2 transport/video/audio layers and network TCP/IP. =B7 Capable to perform test bench design verification of multiple FPGAs in system environment. =B7 Provide support for hardware DVT, firmware integration, and system qualification tests. =B7 Must have at least 8+ years of experiences and BS/MS EE or CE. Please send resumes to: headlandsconsulting@yahoo.com=20 care of Sarah SchloenvogtArticle: 84271
Duane Clark wrote: > Phil Tomson wrote: > >> >> Well, it turns out the the ISE GUI is unusable for me - it takes up to >> several minutes to respond to mouse clicks. > > > I found that behavior if I have, for example, setiathome running in the > background. Even renicing seti to priority 19 did not help. I would > suggest checking for processor intensive tasks running in the background. > Much thanks for that! I was really excited when I saw the ISE WebPack for Linux. But that excitement turned to horror when it took 3 minutes to resize the main window. Killing my Folding@Home Client cleared up the slowness. > So in my alias to configure for the Xilinx environment, I kill seti too: > xi seti stop;source $XILINX/settings.csh;source > $XILINX_EDK/setup.csh;source /opt/eldk/v2p_bsp_envs.csh > >> >> However, I'd actually prefer to be able to script the whole thing. I >> know that a while back someone posted a link to a webpage that showed >> how to run the Xilinx tools from the command line but now I can't find >> it even via goodle. Anyone got the link? >> >> PHil >>Article: 84272
leonardopsantos wrote: > Hello All: > I have a succes story about ISE 7.1i and Mandrake 10.1, with the > usual hassle of library linking and installing openmotif. > What I haven't been able to do is to use iMpact. The GUI loads > fine, but it seems unable to load the Xilinx cable drivers. I tried > to recompile the drivers, but that didn't work either. Has anyone > been able to use iMpact on a 2.6 Linux box? Or at a Linux box at > all? > Thanks! > I've just successfully used the new ISE 7.1i for Linux (on Fedora Core 3 - kernel 2.6.11) to program an XC9500 using the jtag parallel cable I made last week. I had to patch / recompile the drivers. There was some work involved, but it wasn't too terrible. I used the method outlined in this article: http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm There were some unnecessary parts, and some necessary parts that were a little foggy. But I managed. Hint: don't bother with the Xilinx drivers - use the windrvr from http://www.jungo.com/ JasonArticle: 84273
On Mon, 16 May 2005 14:42:37 GMT, "Candida Ferreira" <cferreira@seehomepage.com> wrote: >"rickman" wrote: > >> I don't follow. Multiplexers are as complete as any logic element. >> I'm not sure what you mean by a 3-multiplexer, but I will assume you >> mean a 2 input mux with a single control input. You can get a NOT >> function by putting a 1 on the I0 input and a 0 on the I1 input and >> your signal on the sel input. > >That's true and does not contradict the definition of a ULM, but you need >the 1 and the 0 to create a NOT. Without them you cannot create a NOT with >the 3-multiplexer. But there are other functions, such as the NAND and the >NOR functions that, by themselves, can create any other function, without >needing the NOT, the ZERO and the ONE. These are the ULMs I want to >distinguish from the more ordinary ones. I've seen them named "complete logic gate set" or "primitive logic gate set". I am not sure whether there is a universally accepted name.Article: 84274
"Unlike a liar, who knows the truth and wants to keep people away from it, the bullshitter exhibits a complete lack of concern in differentiating between truth and falsehood. What matters to the bullshitter is: will it further my aims?" As Frankfurt writes in his book, "It's impossible for someone to lie unless he thinks he knows the truth. Producing bullshit requires no such conviction." This lack of concern for the truth - which even the liar must exhibit in order to lie - is what makes b.s. a greater enemy of the truth than lies, he believes. "On B.S.", by Professor Harry G Frankfurt, is published by Pinceton University Press posted by Peter Alfke, speaking for himself
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