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While some early VHDL simulaters were way slower than early Verilog simulators even upto 50x, there is no reason for this today. Traditionally Verilog was/is used for high end ASIC flow years before FPGAs were around and chip guys insisted on and paid for the fastest simulators $ could buy. Since VHDL was much less used then for ASICs, the EDA attention went to Verilog. After synthesis and STA took over, it should be more moot point. Look at Modelsim and others that support both languages, if you construct an entity in either it is compiled into the same internal representation so simulates the same. If you are using a free simulator you get what you pay for, free simulators often perform far slower than leading commercial compilers. Which simulutors are you comparing? johnjakson at usa dot comArticle: 84451
Thomas Entner wrote: [...] > A hint for Xilinx marketing: They could also increase the I/O-count by 7.8% > due to extra features ;-) Indeed. In fact, I can't help but think it's more than just 7.8%! The mind boggles just thinking of all the ways their marketing department could find justification for saying that a 456 pin device has "effectively 2000 pins". > Seriously: I think Altera has more sophisticated counter and > register-packing, so this 2.25-factor is very misleading. Things look > different when we are talking about Stratix II - ALMs, where I would not > really back up Altera's +25%-claim, too (at least what I see from a larger > test-design, originally targeted to Cyclone). Agreed. Inflating their (Xilinx or Altera) numbers by 25% implies to me that, I should find the "extra features" being used in one out of four logic cells, on average. Instead, I find that on a 20000 LUT design, 2000 MUXFx's are used. So for this design, it's really 10% - and that was coding by our ASIC guys, who tend to not pipeline as much as they could/should. On our other designs, it is noticably below 10%. Have fun, MarcArticle: 84452
Symon, According to the data sheet, you can run the LVDS I/O up to 500 MHz in the fastest speed grade part. That would get you 1 Gbps. More likely, you would use the SERDES. For example, at 130 MHz and using x8 serialization, you get 1.04 Gbps per pair. Here is a link to the DPA datasheet: http://www.altera.com/literature/hb/stx2/stx2_sii52005.pdf JohnArticle: 84453
Hi,
i am using the Spartan 3 (XC3S200) and the onboard clock on this
FPGA works at 50Mhz, 20ns. Does anyone know how many instructions this
FPGA can do in one cycle (20ns), in other words, what is the CPI(clocks
per instruction) of the SPartan3.
I want to make a delay that lasts for 1 micro second by using an
incrementing counter. If the CPI for example was one, then i would have
to increment the counter 50 times to get a delay of 1 micro
second.(1*us / 20ns)
Is that correct ????? thanks !!!
Article: 84454Hi Thomas, > Seriously: I think Altera has more sophisticated counter and > register-packing, so this 2.25-factor is very misleading. Things look > different when we are talking about Stratix II - ALMs, where I would not > really back up Altera's +25%-claim, too (at least what I see from a larger > test-design, originally targeted to Cyclone). The 2.5 Stratix LEs to Stratix II ALM ratio is an average over a large suite of (real) designs. That said, there *is* a spread to the LE to ALM ratio. An (artificial) design that maps perfectly into 4-LUTs will get a ~2:1 ratio. An (artificial) design comprising all random 6-LUTs will get a ~4:1 ratio. Real designs will land somewhere in between as they will use a variety of various LUT types. Also, the amount of arithmetic circuitry and # of FFs in the design can impact the packing ratio. From an intuitive perspective, just look at the ALM and you can see that there is a lot more goo there than just what would be needed for 2 LEs. That extra circuitry isn't free -- we would not have spent that silicon area on it without getting more logic density back. Otherwise we would have just removed the circuitry and instead fit more LEs in the chip! Regards, Paul Leventis Altera Corp.Article: 84455
Spartan-3 isn't a processor so the clock used generally determines the maximum rate that things can change at. You can create another faster clock by multiplying the input clock, within the Spartan-3, using a DCM. You can also clock different resources on different edges of the clock. There are lots of ways to do your counter either incrementing, decrementing or some other encode scheme but generally you will count 50 clocks of the 50 MHz to get 1uS. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk <amir.intisar@gmail.com> wrote in message news:1116508772.460301.184420@o13g2000cwo.googlegroups.com... > Hi, > i am using the Spartan 3 (XC3S200) and the onboard clock on this > FPGA works at 50Mhz, 20ns. Does anyone know how many instructions this > FPGA can do in one cycle (20ns), in other words, what is the CPI(clocks > per instruction) of the SPartan3. > > I want to make a delay that lasts for 1 micro second by using an > incrementing counter. If the CPI for example was one, then i would have > to increment the counter 50 times to get a delay of 1 micro > second.(1*us / 20ns) > > Is that correct ????? thanks !!! >Article: 84456
Hi, I'm trying to find out when exactly the XC9572XL recognizes a falling edge. It has a 3.3V supply, and the signal is a square wave between 0V and 5V (this Xilinx is 5V input compatible). At what voltage would a falling edge trigger? I have looked at its datasheet but can't find anything that fits what I'm seeing - I thought that maybe 0.8V was the falling edge threshold (since it is the highest input low voltage), but from my testing it seems to happen a *lot* earlier than that, maybe when the voltage drops to about 4.3V, but that can't be correct I realize. Apologies for what must seem such a basic question, but if anyone could please clarify I would be extremely grateful, thank you. JamesArticle: 84457
Hi, I saw your post about ncsim. I was used to modelsim and really liked it but I have to use ncsim now. I wonder how you use it. You say the GUI is very good, so I wonder how you launch it and run it. I assume you launch it from the command line. What arguments are you using? It would help me if you can simply give me a general idea of your flow. Thank you very much, David John McGrath wrote: > I think the best commercial simulator is by far Cadence's ncsim. This > can support verilog or vhdl or both. I know it is relatively new to the > FPGA simulation world, but is supported in Xilinx's ISE now. I have > used it extensively for verilog HDL development, and found it extremely > fast, has good, intelligent syntax/error messages, and a fantastic GUI > (modelsim's gui really gets on my nerves!). (it also allows features > such as tracing the source of an X on a net (schematically), which is > not one I have seen in other simulators. > I dont know if it is faster than modelsim, (I've never compared them) > but it definatly feels slicker. As for feature complete - I'm guessing > you mean language coverage? - I dont know about VHDL, but I always code > in verilog-2001, and have never seen it unable to handle these "new" > constructs. > I've tried ModelSim, Virsim, Verilog-XL, ncsim (ncverilog), and without > doubt ncverilog wins. It does take a little getting used to, but it's > more than worth it! > > > > gallen wrote: > > I'm sure this kind of things has come up in the past, but given that > > things change, I'd like to throw this out there. > > > > Which simulators do people like to use for their HDL purposes? > > > > I have tried a couple of simulators and I was curious about peoples > > recommendations. > > > > I have used Modelsim XE starter for my purposes (I am just a hobbyest > > now), icarus verilog and GPL cver. I have used the built-in quartus > > simulator as well. > > > > So a couple questions regarding these. Which simulators do people > > consider feature complete? Why do I never hear about cver in this > > group? Does nobody use it? If not, why? What's really wrong with > > Modelsim. People seem faily opposed to it. They say the error > > messages are bad, but I certainly feel that icarus error messages are > > worse. > > > > Also, I haven't really discussed VHDL. Which are best for this? > I've > > heard GHDL is pretty good. > > > > I've mostly discussed free simulators, but I'm also interested in how > > expensive simulators compare to the free sims. > > > > -ArlenArticle: 84458
An FPGA is not a processor. One way to look at it is that the XC3S300 can run up to one instruction every 10ms or so. But the instruction is about 1MBit in size and can do a lot of things simultaneously or sequentially. For example you could use a few hundred bits of that instruction to delay an input signal for exactly 50 clock cycles. Or you can load a single large instruction (or configuration how FPGA people tend to call it) that processes smaller instructions compatible to some RISC CPU at a rate of a 100 MIPS or so. Or you can do both at the same time. Kolja Sulimma amir.intisar@gmail.com wrote: > Hi, > i am using the Spartan 3 (XC3S200) and the onboard clock on this > FPGA works at 50Mhz, 20ns. Does anyone know how many instructions this > FPGA can do in one cycle (20ns), in other words, what is the CPI(clocks > per instruction) of the SPartan3. > > I want to make a delay that lasts for 1 micro second by using an > incrementing counter. If the CPI for example was one, then i would have > to increment the counter 50 times to get a delay of 1 micro > second.(1*us / 20ns) > > Is that correct ????? thanks !!! >Article: 84459
Generally the point will lie between 0.8V(Vil) and 2.0V(Vih) which are the guaranteed limits. The XC9572XL has hysteresis on the I/O so level will be different on the way down to the on way up. Threshold will vary with temperature, voltage (and voltage noise) and with silicon batch so don't rely on anything other than guarantee limits. John Adair Enterpoint Ltd. - Pushing The PicoBlaze. http://www.enterpoint.co.uk "James A" <me@privacy.net> wrote in message news:qK0je.10223$yY4.9241@newsfe5-win.ntli.net... > Hi, > > I'm trying to find out when exactly the XC9572XL recognizes a falling > edge. > It has a 3.3V supply, and the signal is a square wave between 0V and 5V > (this Xilinx is 5V input compatible). At what voltage would a falling edge > trigger? > > I have looked at its datasheet but can't find anything that fits what I'm > seeing - I thought that maybe 0.8V was the falling edge threshold (since > it > is the highest input low voltage), but from my testing it seems to happen > a > *lot* earlier than that, maybe when the voltage drops to about 4.3V, but > that can't be correct I realize. > > Apologies for what must seem such a basic question, but if anyone could > please clarify I would be extremely grateful, thank you. > > James > > > >Article: 84460
Our latest TechiTip on PicoBlaze posted here http://www.enterpoint.co.uk/techitips/Previous_TechiTips/techitips_pushing_picoblaze_part1.html for anyone that has a passing interest. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.ukArticle: 84461
Those 0.8V is the level, where it is guaranteed to detect a low-level... So every real device will switch somewhere in between "max. low" and "min. high" experience "normally" tells me (device independant): - take the supply voltage - divide it by 2 - subtract a small portion 2 to 5% => this will be a reasonable switching level (hysteresis NOT taken into account) but you defentively can't rely on it !! The only thing you can rely on are those mentioned min/max values and using a 'fast' transition (whatever 'fast' means) Jochen JochenArticle: 84462
"John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in message news:1116511092.18941.0@ersa.uk.clara.net... > Generally the point will lie between 0.8V(Vil) and 2.0V(Vih) which are the > guaranteed limits. The XC9572XL has hysteresis on the I/O so level will be > different on the way down to the on way up. Threshold will vary with > temperature, voltage (and voltage noise) and with silicon batch so don't > rely on anything other than guarantee limits. > > John Adair > Enterpoint Ltd. - Pushing The PicoBlaze. > http://www.enterpoint.co.uk Many thanks John. - JamesArticle: 84463
"Jochen" <JFrensch@HarmanBecker.com> wrote in message news:1116511858.745274.202370@o13g2000cwo.googlegroups.com... > Those 0.8V is the level, where it is guaranteed to detect a > low-level... > > So every real device will switch somewhere in between "max. low" and > "min. high" > > experience "normally" tells me (device independant): > - take the supply voltage > - divide it by 2 > - subtract a small portion 2 to 5% > > => this will be a reasonable switching level > (hysteresis NOT taken into account) > but you defentively can't rely on it !! > > The only thing you can rely on are those mentioned min/max values and > using > a 'fast' transition (whatever 'fast' means) > > Jochen > Thank you Jochen. I appreciate you passing on your experience too, as someone with very little in this area! ;) - JamesArticle: 84464
Antti Lukats wrote: > "Michael McGuirk" <michael.mcguirk@xilinx.com> schrieb im Newsbeitrag > news:428BB131.1AB9E7E1@xilinx.com... > >>Antti- >> XMD does not currently support the USB cable. Support will come in an >>upcoming 7.1 service pack. You should use the PC4 for now. >>-Michael > > > ok, thanks for rerply - on the PC where I need it I do not have parallel > ports :( > so I need to wait... > > Antti > > I'm almost certain they make USB->parallel port adapters. Probably no more than $20 or so from newegg.Article: 84465
"Rob Gaddi" <rgaddi@bcm.YUMMYSPAMtmc.edu> schrieb im Newsbeitrag news:d6i8cn$c5d@gazette.corp.bcm.tmc.edu... > Antti Lukats wrote: > > "Michael McGuirk" <michael.mcguirk@xilinx.com> schrieb im Newsbeitrag > > news:428BB131.1AB9E7E1@xilinx.com... > > > >>Antti- > >> XMD does not currently support the USB cable. Support will come in an > >>upcoming 7.1 service pack. You should use the PC4 for now. > >>-Michael > > > > > > ok, thanks for rerply - on the PC where I need it I do not have parallel > > ports :( > > so I need to wait... > > > > Antti > > > > > I'm almost certain they make USB->parallel port adapters. Probably no > more than $20 or so from newegg. USB to parallel will not work with xilinx parallel cable. AnttiArticle: 84466
I have the required skills and experience in FPGA design and implementation of DSP algorithms. I architected and implemented a new low power architecture for Rake receiver for WCDMA systems and have a publication for that too. I am proficient in VHDL, scripting languages and also in the toolsets. I want to send my resume for this position but the email address is not clear from the post. Please let me know that. My email address is mukesh.chugh@gmail.com Thanks, MukeshArticle: 84467
Sorry, I mispelled. However I don't understand very well your mail: so you propose to use a high radix multiplier (something like a multiplier 3bit x 3bit) to create a large word multiplier (16 x 16)? If yes is there some hint that you can provide me about how to accomplish this task, how to put together the basic blocks? Thanks a lot, GiovanniArticle: 84468
Hi Lina,
> I cann't do the math problems, such as: sin, cos... Our condition is as
follows:
> mb-ld: region ilmb_cntlr is full (TestApp/executable.elf section .text)
mb-ld: region ilmb_cntlr is full (TestApp/executable.elf section .text)
mb-ld: section .rodata [00000000 -> 00000327] overlaps section .text
[00000000 -> 00004a1f] mb-ld: section .data [00000328 -> 0000035b] overlaps
section .text [00000000 -> 00004a1f] mb-ld: section .sdata [0000035c ->
00000363] overlaps section .text [00000000 -> 00004a1f] make: ***
[TestApp/executable.elf] Error 1
So, as Aurelian pointed out, your application has become too big for the
available memory. The sin() function requires lots of other floating-point
math functions to support it.
Doing floating-point entirely in software will take up a lot of instruction
space. If you are using the floating-point coprocessor which is available
for MicroBlaze, then your code will be smaller, because the routines for
e.g. add and multiply can be done in hardware.
In any case, try using the function sinf() instead - this uses
single-precision rather than double, and is therefore a bit smaller.
However, it is not part of the ANSI C standard.
Hope this helps,
-Ben-
Article: 84469
randomdude@gmail.com wrote:
>
>
>
que<= (others=>'1');
que(0 to 7)<= "11111111";
std_logic_vector is an array (<> natural range) of std_logic. You can
use that instead of explicitly defining a type!
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 84470
hi
it is working when the setting is the following.....:)
------------------------------=AD------------------------------=AD--------
.=2E..
-- RAMB4_S4 declared ONCE as below
component RAMB4_S4
generic (
INIT_00 : BIT_VECTOR :=3D
X"0000000000000000000000000000=AD000000000000000000000000000000=AD000000";
.
.
.
.
-- 2 components of RAMB4_S4 are instantiated TWICE as below
RAM0: RAMB4_S4
generic map(
INIT_00 =3D>
X"0000000000000000000000000000=AD000000000000000000000000000000=AD003048",
.
.
.
RAM1: RAMB4_S4
generic map(
INIT_00 =3D>
X"0100000000000000000000000000=AD000000000000000000000000000000=AD009751",
Article: 84471
m_oylulan@hotmail.com wrote:
>Hello,
>
>I'm trying to write a CORDIC macro for a polar transmitter FPGA design.
>I've used the parallel approach, but when I do a timing estimation the
>longest delay path is through the CORDIC routine, and limits the
>maximum clock rate of the whole design to about 40MHz. Other parts of
>the design on the same board need to run at much faster rate so I'm
>considering using a bit-serial version.
>
>As I understand it, the bit-parallel implementation has low latency and
>therefore high throughput, but because of the the word-wide shifts it
>clocks at a slower rate. Conversely, the bit-serial
>routine has a high latency and low throughput rate, but allows the
>board to run at a faster clock rate. Is this right?
>
>My question is:
>
>In the bit-serial implementation, you still need to perform the shift
>operation on the entire word to select the right bit to send to the
>bit-serial adder/subtractor, so how does this solve the problem of a
>slow clock rate due to the shift operation?
>
>Thanks,
>
>Mees
>
>
>
Is this an iterative or an unrolled? I am assuming it is iterative,
in which case you have a rather nasty shifter to deal with which is
killing your performance assuming one clock per iteration. You can
pipeline the iterations to allow more than one iteration result at a
time in the loop, but it requires a bit of careful bookkeeping in the
design. For a bit serial implementation, the shift is accomplished by
varying the delay, which if implemented in memories involves messing
with the address to reduce the overhead for the shifter.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 84472
Mike Treseler wrote:
I concur with everything Mike has said here. I can count on one hand
the number of times I've done a timing simulation on an FPGA design, and
I have done literally hundreds of FPGA designs. It is too slow, and too
easy to miss a timing parameter. Do a thorough static timing analysis
and a functional simulation instead, and inspect any clock domain
crossings very carefully.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 84473Has anyone succeded to install Webpack for linux on non-RH based distro with modern 2.6 kernel etc ? I have recently tried, but failed miserably. After breaking through numerous dependency problems, I have managed to get it to start,but it crashed after opening a few menus... I have had no luck with Windows version under Wine either. IIRC it works under VmWare, but it seems like an overkill to run virtual machine just for Webpack... Best regards, BrankoArticle: 84474
On 18 May 2005 22:28:09 -0700, "CODE_IS_BAD" <Puneetsingh81@gmail.com> wrote: >hi all, > i wud like to know how many logic cells are there in 1 slice. 1 >slice contains 2 LUTs. OK to tell in particular i am using an XC2V3000 >with 14336 slices. So how many logic cells does it amount to? thanx Depends on your exact definition of a logic cell. If a logic cell is "one 4-LUT and one FF", then a slice (a xilinx term) contains 2 of them. The slice contains other stuff that is not part of the above definition of a logic cell, and the logic cell (LUT+FF) can do stuff beyond the minimum of what you would expect a "4-LUT + FF" can do (such as SP RAM, DP RAM, SRL16, carry). According to http://www.fpga-faq.org/compare/build_form.cgi the XC2V3000 has: 28672 4-LUTS 28672 FFs (in the slices. there are 720 I/Os that also have FFs) A slice contains the following: Slice (2 x (FF+Carry+XOR+AND+LUT4(as Logic/ROM/RAM/Shifter) ) Philip =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORG
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