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Messages from 84425

Article: 84425
Subject: Re: Which Simulators
From: "John McGrath" <tails4e@gmail.com>
Date: 18 May 2005 19:00:39 -0700
Links: << >>  << T >>  << A >>
I think the best commercial simulator is by far Cadence's ncsim. This
can support verilog or vhdl or both. I know it is relatively new to the
FPGA simulation world, but is supported in Xilinx's ISE now. I have
used it extensively for verilog HDL development, and found it extremely
fast, has good, intelligent syntax/error messages, and a fantastic GUI
(modelsim's gui really gets on my nerves!). (it also allows features
such as tracing the source of an X on a net (schematically), which is
not one I have seen in other simulators.
I dont know if it is faster than modelsim, (I've never compared them)
but it definatly feels slicker. As for feature complete - I'm guessing
you mean language coverage? - I dont know about VHDL, but I always code
in verilog-2001, and have never seen it unable to handle these "new"
constructs.
I've tried ModelSim, Virsim, Verilog-XL, ncsim (ncverilog), and without
doubt ncverilog wins. It does take a little getting used to, but it's
more than worth it!



gallen wrote:
> I'm sure this kind of things has come up in the past, but given that
> things change, I'd like to throw this out there.
>
> Which simulators do people like to use for their HDL purposes?
>
> I have tried a couple of simulators and I was curious about peoples
> recommendations.
>
> I have used Modelsim XE starter for my purposes (I am just a hobbyest
> now), icarus verilog and GPL cver.  I have used the built-in quartus
> simulator as well.
>
> So a couple questions regarding these.  Which simulators do people
> consider feature complete?  Why do I never hear about cver in this
> group?  Does nobody use it?  If not, why?  What's really wrong with
> Modelsim.  People seem faily opposed to it.  They say the error
> messages are bad, but I certainly feel that icarus error messages are
> worse.
>
> Also, I haven't really discussed VHDL.  Which are best for this?
I've
> heard GHDL is pretty good.
>
> I've mostly discussed free simulators, but I'm also interested in how
> expensive simulators compare to the free sims.
> 
> -Arlen


Article: 84426
Subject: Re: About back annotated simulations...
From: "Vaughn Betz" <no_spam@altera.com>
Date: Wed, 18 May 2005 23:59:40 -0400
Links: << >>  << T >>  << A >>
One other thing worth doing, if you're using Quartus -- run the design 
assistant.  You can access it from Processing->Start->Start Design 
Assistant.

It will check for things like an undisciplined reset strategy, missing 
timing constraints, lack of synchronizers/FIFOs where you should think about 
having them etc.  It's a useful checker on a design, a bit like lint for 
hardware. It will flag many of the things Mike lists as poor design 
practice, and the more of those you can get rid of, the more you can trust 
that meeting your static timing requirements means your design will work 
without problems.

Regards,

Vaughn
[v b e t z (at) altera.com]






Article: 84427
Subject: Re: Quartus II 4.1 Problem
From: "Vaughn Betz" <no_spam@altera.com>
Date: Thu, 19 May 2005 00:07:46 -0400
Links: << >>  << T >>  << A >>
I ran this by a device programming expert at Altera, and from this error 
message, he thinks the device you are using does not agree with the JAM file 
you're using.

 Here is the cause and action for the message from the Quartus II online 
help:

CAUSE: You directed the Programmer to configure the specified device.

However, the Programmer cannot successfully configure the device because

the JTAG ID code for the specified target device does not match any of

the valid ID codes for the device. This problem occurs when the target

device's location on the circuit board does not match the device's

location in the device chain in a Chain Description File (.cdf), as

displayed in the Programmer window.

ACTION: Make sure the target device's location on the circuit board

matches the device's location in the device chain as displayed in the

Programmer window.


Hope this helps.

Vaughn
[v b e t z (at) altera.com]

"Jos? Luiz Martins" <jmartins@modemmedia.com> wrote in message 
news:98f4d5f.0503290657.54a22025@posting.google.com...
> Thank you Bert !
>
> I did the configuration as detailed on Altera's documentation for this 
> board
> and nope...
>
> I even replaced the current device to another good one.
>
> I can detect what device is present, but nothing else.
>
>
> Thank you ,
>
>
> JL Martins
>
> Bert Cuzeau <_no_spa_m_info_no_underscore_@alse-fr___.com> wrote in 
> message news:<4248ffef$0$1623$636a15ce@news.free.fr>...
>> Make sure you selected the exact correct device.
>> OTOMH, some old UP boards have two devices (cpld + fpga) and a switch
>> to select which one is hooked to the JTag connector...
>> There is a command to scan the JTag chain.
>>
>>
>> Jos? Luiz Martins wrote:
>>
>> > Hi folks,
>> >
>> >
>> > I'm facing one problem that is driving me crazy...
>> >
>> > The error is the following:
>> >
>> > Error: JTAG ID code specified in JEDEC STAPL Format File does not
>> > match any valid JTAG ID codes for device.
>> >
>> > I'm using one ALtera University Program with ByteBlaster MV Cable on a
>> > Windows XP machine.
>> >
>> > This is my first project in FPGA... I read almost everithing about
>> > ByteBlaster and Quartus II configuration, and nope...
>> >
>> > My cable is installed, and everytinh else...
>> >
>> > Thank you very much in advance.
>> >
>> >
>> > JL Martins 



Article: 84428
Subject: Re: VHDL array question
From: "Marc Randolph" <mrand@my-deja.com>
Date: 18 May 2005 21:27:35 -0700
Links: << >>  << T >>  << A >>

randomdude@gmail.com wrote:
> Yeah, I'm trying very hard to visualise how the statements I make
will
> map to hardware. Finding it kind of hard though, so I'm hoping some
> nice books will help me out.
> Ta for the searching-google-groups tip, btw!

Howdy Alan,

Until you have the hardware drawn (in your head, on paper, or in a
schematic tool), I dare say there is little chance of getting the
desired result(s) out of the tools.  I'm not saying this to make it
sound difficult or to keep you from trying - just that even people who
know what hardware they want find it easy to screw up HDL's.

> So are schematics compiled to VHDL which is then synthesised? I
always
> assumed the HDL was 'compiled' into a schematic which was then mapped
> into the chip.

The Mentor schematic tool created VHDL.  I don't know if Xilinx's
schematic tool does or not - but it wouldn't have to.  It could
directly synthesize the schematic into a netlist, if that's how they
designed it.

> I'm determined to master this fpga marlarkey.. even if it takes me a
> log time.. :) Thanks.

If you have some digital design experience, it shouldn't take too long
to get a fair understanding of it.

Good luck,

   Marc


Article: 84429
Subject: Re: About back annotated simulations...
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Thu, 19 May 2005 04:32:58 GMT
Links: << >>  << T >>  << A >>
On Tue, 17 May 2005 17:52:57 -0700, Phil Hays
<Spampostmaster@comcast.net> wrote:

>Fred C wrote:
>
>>...what are their really use for ?
>>For several years, I developped and succesfully used FPGA(Xilinx,
>>Altera, Actel) designed with strongs Static Timing analyses, with a good
>>constraint coverage and only some lite back annotated simulations.
>>After some recent discussions, I'm looking for external experiences that
>>can prove me that back-annotated simulations in min/typ/max timings are
>>not only better for design verification - I'm convinced of this-, but
>>are necessary, even if done with the static timing analyses.
>>Is there something I missed ?
>
>Suppose you were designing an FPGA that would control some part of an
>oil refinery.  Or the landing of a probe to Mars.  Or the engines on
>an airliner.  Or the dosage of radiation given to a cancer patient.
>
>Wouldn't you want to verify the design as correct in as many ways as
>you could?

Sure.  But as a practical matter, there's never enough time or money
to verify a design in as many ways as I could think of, even if the
reliability of the product is super, super important.  And were I to
come up with a prioritized list of things I could do to ensure the
correctness and reliability of a design, functional simulation with
back-annotated timing would be near the bottom.

It's not that it's bad; it's just that I can almost always find a
better payoff for my time.

Bob Perlman
Cambrian Design Works







Article: 84430
Subject: Re: Which Simulators
From: "jtw" <wrightjt @hotmail.invalid>
Date: Thu, 19 May 2005 04:43:26 GMT
Links: << >>  << T >>  << A >>
Which version of Modelsim?  There is a feature in (or available for) SE that 
lets you chase down those X's.

Sorry, I haven't used ncsim.  (Years ago, I did use something from them. 
It's been so long, I don't remember much about it.)

Jason

"John McGrath" <tails4e@gmail.com> wrote in message 
news:1116468039.094501.120150@g14g2000cwa.googlegroups.com...
>I think the best commercial simulator is by far Cadence's ncsim. This
> can support verilog or vhdl or both. I know it is relatively new to the
> FPGA simulation world, but is supported in Xilinx's ISE now. I have
> used it extensively for verilog HDL development, and found it extremely
> fast, has good, intelligent syntax/error messages, and a fantastic GUI
> (modelsim's gui really gets on my nerves!). (it also allows features
> such as tracing the source of an X on a net (schematically), which is
> not one I have seen in other simulators.
> I dont know if it is faster than modelsim, (I've never compared them)
> but it definatly feels slicker. As for feature complete - I'm guessing
> you mean language coverage? - I dont know about VHDL, but I always code
> in verilog-2001, and have never seen it unable to handle these "new"
> constructs.
> I've tried ModelSim, Virsim, Verilog-XL, ncsim (ncverilog), and without
> doubt ncverilog wins. It does take a little getting used to, but it's
> more than worth it!
>
>
>
> gallen wrote:
>> I'm sure this kind of things has come up in the past, but given that
>> things change, I'd like to throw this out there.
>>
>> Which simulators do people like to use for their HDL purposes?
>>
>> I have tried a couple of simulators and I was curious about peoples
>> recommendations.
>>
>> I have used Modelsim XE starter for my purposes (I am just a hobbyest
>> now), icarus verilog and GPL cver.  I have used the built-in quartus
>> simulator as well.
>>
>> So a couple questions regarding these.  Which simulators do people
>> consider feature complete?  Why do I never hear about cver in this
>> group?  Does nobody use it?  If not, why?  What's really wrong with
>> Modelsim.  People seem faily opposed to it.  They say the error
>> messages are bad, but I certainly feel that icarus error messages are
>> worse.
>>
>> Also, I haven't really discussed VHDL.  Which are best for this?
> I've
>> heard GHDL is pretty good.
>>
>> I've mostly discussed free simulators, but I'm also interested in how
>> expensive simulators compare to the free sims.
>>
>> -Arlen
> 



Article: 84431
Subject: Why do VHDL gate level models simulate slower than verilog
From: "abilashreddy@yahoo.com" <abilashreddy@yahoo.com>
Date: 18 May 2005 21:53:25 -0700
Links: << >>  << T >>  << A >>
Hi Group,
         Iam not sure if this is the right group to post my query
on,butI would appreciate any kind of information.I am relatively new to
VHDL and am tring to understand whyVHDL gate level descriptions
simulate slower than verilog models.I was told that it was because how
the VHDL model gets evaluated (delay
models) that makes it slower.I didnt quite follow this and if somebody
in the group could point me towards a more detailed explanation ,it
would be great.I would also like to know why do we see better VHDL
performace at behavioural descriptions(as compared to verilog
behavioural descriptions.).I am sorry if this has been discussed
previously.

Thanks,
Abilash.


Article: 84432
Subject: Re: open support question to Xilinx. should be fairly simple to answer.
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 19 May 2005 07:03:13 +0200
Links: << >>  << T >>  << A >>
"Michael McGuirk" <michael.mcguirk@xilinx.com> schrieb im Newsbeitrag
news:428BB131.1AB9E7E1@xilinx.com...
> Antti-
>      XMD does not currently support the USB cable. Support will come in an
> upcoming 7.1 service pack. You should use the PC4 for now.
> -Michael

ok, thanks for rerply - on the PC where I need it I do not have parallel
ports :(
so I need to wait...

Antti



Article: 84433
Subject: Re: Virtex-2 JTAG problem
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 19 May 2005 07:20:29 +0200
Links: << >>  << T >>  << A >>

<Chris> schrieb im Newsbeitrag news:ee8e533.5@webx.sUN8CHnE...
> It appears to be a BGA install problem. I have the one board loaded up
with a test program that toggles all the I/Os so I can probe around on the
board and test the BGA installation. One of the I/Os that is supposed to be
toggling is just an open circuit. When I squeeze the board and the BGA
between my fingers it becomes a closed circuit and I get my square wave out.
When I let go it goes open again.
>
> It just so happens that the /PROG pin is another one of these open
circuits. If I squeeze the board and BGA and hit my reset button, the FPGA
reboots itself. If I'm not squeezing the button does nothing.
>
> I am going to assume that the other board that I can't even get to program
has the same problem, just with more opens under the chip. On that one I can
see the JTAG TDI signal going into the FPGA is toggling but the TDO out of
the FPGA is always high.
>
> I guess it could be a board manufacture problem, with the vias not working
right and having intermittent connections in them. I doubt it though.
>
> Sigh. I hate BGAs.

I dont hate BGA, or only when they are mis soldered ;)

the no connect on PROG pin would make the configuration to fail.
It is a bit weird and I think also undocumented that if there is no pull up
on PROG then the FPGA can not be configured over JTAG, at least on Virtex
devices, I had one hand soldered protoboard (direct wires to BGA balls)
where the JTAG was working ok, but config over JTAG not. The problems was I
assumed the jtag conf work when prog is open. it does not.

Antti



Article: 84434
Subject: How many logic cells are there in one slice
From: "CODE_IS_BAD" <Puneetsingh81@gmail.com>
Date: 18 May 2005 22:28:09 -0700
Links: << >>  << T >>  << A >>
hi all,
   i wud like to know how many logic cells are there in 1 slice. 1
slice contains 2 LUTs. OK to tell in particular i am using an XC2V3000
with 14336 slices. So how many logic cells does it amount to? thanx


Article: 84435
Subject: Re: How many logic cells are there in one slice
From: "Marc Randolph" <mrand@my-deja.com>
Date: 18 May 2005 22:41:25 -0700
Links: << >>  << T >>  << A >>

CODE_IS_BAD wrote:
> hi all,
>    i wud like to know how many logic cells are there in 1 slice. 1
> slice contains 2 LUTs. OK to tell in particular i am using an
XC2V3000
> with 14336 slices. So how many logic cells does it amount to? thanx

Step 1: go to http://www.google.com
Step 2: type in the following three words: logic cell slice
Step 3: click on the 4th result

   Marc


Article: 84436
Subject: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
From: "sankalp.singhal" <sankalp.singhal@rediffmail.com>
Date: 18 May 2005 23:05:40 -0700
Links: << >>  << T >>  << A >>
hi group,
   I have just started using NIOS II with Quartus II ver 4.2 ..I tried
a simple project having a NIOS CPU, an onchip-memory(16Kbytes)and an
led PIO.
   Using IDE i made a C application program and included the respective
.ptf file..after succesfully building the the project , when i am
RUNning the application it is giving a warning in the console--
"Using cable "ByteBlasterII [LPT1]", device 2, instance 0x00
Pausing target processor: not responding.
Resetting and trying again: FAILED
Leaving target processor paused"

    Could u pls help me out or any suggestions related to the above
problem >>>>

Hardware & Softwares used >>>
1. Quartus II ver 4.2
2. NIOS II evaluation version
3. NIOS II IDE(Integrated Development Environment)
4. Stratix Board (EP1S25F1020C5)
5. ByteBlasterII

regards,
sankalp.singhal


Article: 84437
Subject: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
From: "CODE_IS_BAD" <Puneetsingh81@gmail.com>
Date: 18 May 2005 23:31:10 -0700
Links: << >>  << T >>  << A >>
hi sankalp....
   Have u downloaded the basic NIOS core into the FPGA first???? Coz
after that only u can download ur compiled code from the NIOS IDE...


Article: 84438
Subject: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
From: "sankalp.singhal" <sankalp.singhal@rediffmail.com>
Date: 18 May 2005 23:38:55 -0700
Links: << >>  << T >>  << A >>
hi,
   I have downloaded the .sof file on my board.(Not sure weather the
board is configured properly or not)...thereafter only i tried to
download the c application over it....

regards,
sankalp.singhal


Article: 84439
Subject: Re: How many logic cells are there in one slice
From: "Thomas Entner" <aon.912710880@aon.at>
Date: Thu, 19 May 2005 08:44:47 +0200
Links: << >>  << T >>  << A >>
> Step 1: go to http://www.google.com
> Step 2: type in the following three words: logic cell slice
> Step 3: click on the 4th result
>

The 4th result of google will change frequently...

I think the OP is confused by the fact the Xilinx count a slice as 2.25 LCs 
due to "extra features".

A hint for Xilinx marketing: They could also increase the I/O-count by 7.8% 
due to extra features ;-)

Seriously: I think Altera has more sophisticated counter and 
register-packing, so this 2.25-factor is very misleading. Things look 
different when we are talking about Stratix II - ALMs, where I would not 
really back up Altera's +25%-claim, too (at least what I see from a larger 
test-design, originally targeted to Cyclone).

Thomas

www.entner-electronics.com



Article: 84440
Subject: Actel Designer on Linux
From: "Neill A" <neilla@ewst.co.uk>
Date: 19 May 2005 00:06:33 -0700
Links: << >>  << T >>  << A >>
Does anyone have any experience of running Actel Designer on Linux?

We currently use WinXP, and have recently been informed that if we used
Linux, then Designer would run 10x faster.  I would just like to see if
anyone out there can confirm this before trying to get a machine set up
with Linux.

Also since I'm talking about Linux, is there any preference as to which
distro is best for FPGA development?

Thanks

Neill.


Article: 84441
Subject: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
From: "sankalp.singhal" <sankalp.singhal@rediffmail.com>
Date: 19 May 2005 00:09:13 -0700
Links: << >>  << T >>  << A >>
hi puneet,
           could u suggest me any links related to NIOS II and NIOS II
IDE ......


Article: 84442
Subject: how to debug a C/C++ application in NIOS II IDE
From: "sankalp.singhal" <sankalp.singhal@rediffmail.com>
Date: 19 May 2005 00:16:26 -0700
Links: << >>  << T >>  << A >>
 hi all,
     how to debug a C/C++ application in NIOS II IDE??
what r the instructins/funtions used for programming a LED using HAL
library ?

regards
sankalp.singhal


Article: 84443
Subject: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
From: "CODE_IS_BAD" <Puneetsingh81@gmail.com>
Date: 19 May 2005 00:25:55 -0700
Links: << >>  << T >>  << A >>
hi sankalp....
   there is lots n lots of material on altera website.... U can
download whole lot of stuff...
 Also there r some reference designs given in those pdfs u can follow
the step by step procedure and check it out (ex LED blinking, timer
count display on LCD and the 7-segment displays etc.)... It works for
my case :-)


Article: 84444
Subject: Re: Problems with Constraints (Xilinx, ISE 6.3)
From: Klaus Falser <kfalser@durst.it>
Date: Thu, 19 May 2005 09:27:21 +0200
Links: << >>  << T >>  << A >>
In article <d6g5jd$7aa@gazette.corp.bcm.tmc.edu>, 
rgaddi@bcm.YUMMYSPAMtmc.edu says...
> So I've got the whole VHDL thing down, but I've still got some problems 
> understanding how to set up timing constraints.
> 
> I've got a 50 MHz oscillator that I use two DCMs to turn into three 
> clocks, 40 MHz @ 0<, 40 MHz @ 180<, and 20 MHz @ 0<.
> 
> The master clock for all the logic is the first of the 40 MHz clocks. 
> But for some reason I can't get the Constraints Editor to accept this as 
> a clock, and so I can't base any timing constraints off of it.  How do I 
> get it to?
> 
> The other two clocks handle some trivial amount of logic, but mainly 
> serve as clocks to external hardware.  Some of them have been getting 
> switched around on the output ports as I try to tweak down the timing, 
> so I often have combinational logic like:
> 
> out_clock_1 <= internal_clock;
> out_clock_2 <= internal_clock;
> 
> where out_clock 1 and 2 are ports on the top-level entity.
> 
> How do I convince XST to keep the name internal_clock for this signal, 
> such that I can know what to try to set constraints on?
> 

If I understand the DCM documentation correctly you have 
to constraint only the input clock with 50 MHz. 
All derived clocks should get their constraints automaticely 
from "ngdbuild".

Somebody knows how to use a INPUT/OUTPUT OFFSET constraint 
with such a derived clock?

Regards 
Klaus

Article: 84445
Subject: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board
From: David Brown <david@westcontrol.removethisbit.com>
Date: Thu, 19 May 2005 10:02:21 +0200
Links: << >>  << T >>  << A >>
sankalp.singhal wrote:
> hi puneet,
>            could u suggest me any links related to NIOS II and NIOS II
> IDE ......
> 


There is plenty of information on Altera's website, such as:
	http://www.altera.com/literature/lit-nio2.jsp
If you've installed QII and the Nios tools, you should also have a whole 
pile of documents on your system (try something like 
c:\Altera\kits\nios2\documents).  Print out the "getting started" and 
"tutorial" documents and work through them.

In future, could you (and "CODE_IS_BAD") please note that this is an 
English language newsgroup (being an international group).  If English 
is not your native tongue (or if, like me, you just can't spell very 
well), then there is no problem with poor spelling or grammar.  But 
there is no excuse for writing in some silly teenage "SMS" code, or 
failing to use capitals as appropriate.

mvh.,

David

Article: 84446
Subject: Re: Actel Designer on Linux
From: "Hans" <hans64@ht-lab.com>
Date: Thu, 19 May 2005 08:17:07 GMT
Links: << >>  << T >>  << A >>
Hi Neill,

I tried it on my Gentoo machine and failed miserably (java issue). If you 
want to try a distro I would suggest one of the free RedHat enterprise 
clones such as Whitebox and Centos. If designer runs 10x faster under Linux 
then I will build myself a RH box immediately since designer for ProASIC is 
sooooo slow :-)

Hans.
www.ht-lab.com

"Neill A" <neilla@ewst.co.uk> wrote in message 
news:1116486392.966216.36360@g43g2000cwa.googlegroups.com...
> Does anyone have any experience of running Actel Designer on Linux?
>
> We currently use WinXP, and have recently been informed that if we used
> Linux, then Designer would run 10x faster.  I would just like to see if
> anyone out there can confirm this before trying to get a machine set up
> with Linux.
>
> Also since I'm talking about Linux, is there any preference as to which
> distro is best for FPGA development?
>
> Thanks
>
> Neill.
> 



Article: 84447
Subject: Xilinx V2Pro DCM config and settling time questions
From: "Ken" <no@spam.com>
Date: Thu, 19 May 2005 10:53:04 +0200
Links: << >>  << T >>  << A >>
Hi all,

I need to generate a 20MHz clock from a 10MHz clock on a V2Pro.

Plan is to use 2 DCMs:

1st DCM:
10MHz into CLKIN
Use CLKFX output with default of M = 4 and D = 1 to get 40MHz.
I need to leave CLKFB unconnected I think because CLK0 and CLK2X will be 
below
24MHz.
Also, since I am using CLKFX, I can leave CLKFB open since it is ok for my
CLKFX clock to be out of phase with the input 10MHz clock.

2nd DCM:
40MHz from 1st DCM into CLKIN
20MHz out of CLKDV
CLKFB gets CLK0.

First question - will that all work?

Next question:

The input 10MHz clock can be varied by +/- 25 parts per million to give a
frequency offset.

So, input clock period is (1/10e6) +/- 2.5ps.

The +/-2.5 ps seems to be way less than the cycle and period jitter spec of
the DCM so I am not worried about that.

The input clock will be held at each offset for 20ms minimum.  Also, there
is 800us available for the DCMs to adjust to the new input frequency.

I see that the lock time of the DCM is 10ms and I assume this is just at
configuration time?

So, am i right in thinking that my DCM cascade will track my freq offset
when it is applied?  Is there a spec somewhere that states how long it will
take to adjust to the new input freq or is it instantaneous since the
variance is only +/- 2.5ps?

Thanks for your time guys,

Ken



Article: 84448
Subject: Re: Xilinx V2Pro DCM config and settling time questions
From: "Jochen" <JFrensch@HarmanBecker.com>
Date: 19 May 2005 03:20:18 -0700
Links: << >>  << T >>  << A >>
Hi Ken,

  we're not using V2Pro ('just' Spartan3) , so I'm not sure about it's
requirements for DCM-input-jitter-requirements...

  But please use
      http://www.xilinx.com/applications/web_ds_v2pro/jitter_calc.htm

  to calculate first DCM's jitter ouput and verify that it fits to
second DCM's input requirements...

Jochen


Article: 84449
Subject: Re: Why do VHDL gate level models simulate slower than verilog
From: "Neo" <zingafriend@yahoo.com>
Date: 19 May 2005 03:23:55 -0700
Links: << >>  << T >>  << A >>
Beacuase the verilog libraries are more faster and efficient for
simulation apart from the fact that algorithms used for simulating
verilog netlists are faster.




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