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Hello, Does somebody know if the last version of JBits (3.0) will work with spartans family? I know JBits 3.0 supports Virtex II, and an older version supported Virtex... but .. Spartan is kind of a Virtex.. so .. have anyone try this before? Thanks, Alonzo.Article: 74276
A lot depends on the type of designs you are doing as well.
Being that my designs are focused on DSP, they tend to be
pipelined data paths with little extra control, so this
methodology is very easy to apply. Other designs, like a
microprocessor could be more difficult. In the example you
cite, a fairly painless approach might be to force the
register write decoding to cause all the registers to be
written at once as a result of the reset.
glen herrmannsfeldt wrote:
> Ray Andraka wrote:
>
> > But Glen, you can get the whole circuit to a
> > known state by just using strategically
> > placed resets. Take a simple example of a pipeline
> > that has an accumulator in it.
> > All that needs to be reset is the registers
> > at the pipeline input (these should be
> > held at a know value for some known number of
> > clocks), and a reset on the accumulator,
> > which is needed to clear out the history
> > stored in the accumulator (it won't self
> > clear regardless of the data coming in
> > because of the feedback loop).
>
> (snip)
>
> > My point is that you do not have to reset
> > every single flip-flop in the design to
> > reach a known state as long as you are willing
> > to take a known number of clock cycles
> > to reach that state.
>
> Yes. That is included in what I wrote as a
> known combination of reset and clocks.
>
> It gets more complicated if you have memory
> elements other than pipelines, such as registers
> in a CPU. While the processor might work just fine
> with them in a random initial state, testing might
> not. All these things have to be considered at
> design time. It might be that they don't add much
> logic, but they do add to the time it takes to
> verify the design.
>
> After I wrote:
>
> >>(I believe it is important for testing purposes
> >> that a known state be reached with a known combination
> > of reset, clocks, and other signals.
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin,
1759
Article: 74277http://xup.msu.edu have several interesting links. Try also www.eece.unm.edu/xup for some tutorials on ISE, EDK and other tools. alnz.Article: 74278
Hi John, Others more familiar with the DCM can probably provide more detail on this, but the ew generation of the DCM in Virtex-4 supports the new Dynamic Reconfiguration Port, which is a memory type-interface, which allows a user to dyamically change the DCM configuration. It should be relatively easy to dynamically change the DCM tap or M/D numbers. So in short, it should be possible to have an MicroBlaze system automatically throttle it's own clock. Also, I beleive if you increment or decrement the tap by 1 tap at a time, the DCM should not loose lock durig this process. Hope this is helpful ! John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<ck1rpt$ubf$1@bunyip.cc.uq.edu.au>... > Hi Austin, > > Austin Lesea wrote: > > > I refer to this as a 'tap dance.' (please forgive my humor, but it is > > part of my personality....) Change the M, or D, or input frequency, and > > the 'tap dance' changes such that the loop stays locked, and the output > > remains phase and frequency locked to the input. > > > > In this way, the phase error (if the oscillator is perfect) is never > > worse than a tap value for one whole concurrence cycle (D cycles of > > input clock, or M cycles of output clock). > > Any ideas (or experience) on what happens if you twiddle DCM > configuration bits on the fly (a la partial reconfig)? I'm guessing it > would be safe to hold the DCM in reset, change the tap configuration, > then restart it, but that's not much use if the DCM is clocking the very > same logic that is driving the partial reconfiguration :) > > I'm picturing a self-reconfiguring microblaze uClinux system dynamically > scaling its own clock... > > JohnArticle: 74279
Thank you for your help. It is fine now. Best regards AndréArticle: 74280
Hi, Does that mean that something like what's below should work without worrying about timedomain crossing ? ___ ___ ____ ____ | R | | R | | R | | R | --| e |---- Comb 1 ---| e |---- Comb 2 ----| e |--\/--- Comb 3 ---| e |--- | g | | g | / | g | | | g | | 1 | | 2 | | | 3 | | | 4 | /|>__| /|>__| | ClkFX-|>__| | /|>__| | | \_________________/ | Clk Clk Clk With ClkFX = n * Clk Note that It doesn't represent something in particular, just something out of my imagination. What comes to mind is for example an operation that would require 3 multiplexer, you could time-multiplex them this way and the rest of the pipeline don't know it ... SylvainArticle: 74281
I've now tried something similar - I removed my own master for my reader,
and replaced it with a standard DMA component. This feeds a fifo (via a
slave port on my reader component, which controls the "waitRequest" line in
order to stall the DMA when the fifo is fairly full until it is nearly empty
again). I actually implemented a small master to control the DMA, starting
transfers automatically and independantly of the Nios. It all works fine,
except...I get one read every two cycles, exactly as when using my own
master.
When I ran at 50 MHz instead of 60 MHz, the bursts were one read per cycle.
I was getting some corruption, but I suspect that was a matter of the phase
for the sdram clock being not quite right for 50 MHz, so I'm worried there.
However, it looks very much like the standard Nios II sdram controller with
the dev kit sdram and default timings won't run properly at 60 MHz. Could
that be the case?
David
"Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message
news:10m7o2hf84dkhce@news.supernews.com...
>
> You've got it. I generate a IRQ based on the fifo level and then in the
ISR
> I setup the dma to dump the fifo to an sdram buffer. The fifo is being
> filled at about one word every 700ns and when the fifo level reaches 480
the
> IRQ dump process is triggered. The interrupt latency is about 8uS and the
> dma itself takes approximately 485 system clocks. (other code is hammering
> the sdram in parallel + sdram refresh etc.)
>
> Here is the fifo instantiation:
>
> NFIFO : scfifo WITH (
> INTENDED_DEVICE_FAMILY = "Cyclone",
> LPM_WIDTH = 36,
> LPM_NUMWORDS = 512,
> LPM_WIDTHU = 9,
> LPM_TYPE = "scfifo",
> LPM_SHOWAHEAD = "ON",
> OVERFLOW_CHECKING = "OFF",
> UNDERFLOW_CHECKING = "OFF",
> USE_EAB = "ON",
> ADD_RAM_OUTPUT_REGISTER = "ON"
> );
>
> Then I hook the chipselect (CS) and read signals from the IUL port thusly:
>
> RD_DN.d = SCAN_IN_CS & SCAN_IN_RE;
> RD_DN.clk = CLK100M;
>
> NFIFO.rdreq = RD_DN;
> NF_OUT[35..0] = NFIFO.q[35..0];
>
> NF_OUT[31..0] is connected directly to the data in port of IUL.
>
> CLK100M is actually the sysclk which is 75 MHz right now. Timing analysis
> says I'm good to 97MHz, but I haven't pushed it yet.
>
> I'm pretty sure this info with the system builder IUL port settings I
posted
> earlier are all you need. Hope this helps.
>
> Ken
>
> "David Brown" <david@no.westcontrol.spam.com> wrote in message
> news:ck05od$t7e$1@news.netpower.no...
> >
> > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message
> > news:10m6j0ko352cb9b@news.supernews.com...
> > >
> > > Hi David,
> > >
> > > Sorry for the delay I've been out of town with no access.
> > >
> > > I'm using the standared included dma peripheral to empty a standard
> single
> > > clock fifo. I did not modify any of the master priorities.vr
> > >
> >
> > So you have a DMA device set up to read from a fifo as a slave. Did you
> > make a class.ptf file for the fifo slave, that you could post here? Am
I
> > right in thinking you used a standard fifo (i.e., readReq triggers a new
> > read) rather than a read-ahead fifo (i.e., readReq works as an
> acknowledge)
> > ? I think the read-ahead version would eliminate your need of a read
> > latency. Also, were you feeding data into the fifo at full speed? In
my
> > application, the other end of the fifo is much slower (roughly 1/6 of
the
> > system speed), so I'd like to let the fifo build up a bit before
starting
> a
> > burst - perhaps triggering a burst start when it is half-full, and
> stopping
> > again when it is empty. I expect to write my own slave, wrapping the
fifo
> > and providing such control signals (I have much of the code for that
from
> my
> > original version using my own master). Would I be correct in thinking
> that
> > the way to handle this is for the DMA to be set up to transfer a given
> > number of words, and have the slave assert waitRequest to pause the DMA
> > reads until the fifo was half-full?
> >
> > David
> >
> >
> >
> > > I can post a test project to the Nios Forum that runs on the Cyclone
> > devkit
> > > board, but I don't have time to document it very well.
> > >
> > > If anyone is in a bind they can contact me through the forum and I
will
> > > email them a .zip of the project. (~4MB)
> > >
> > > The credit for this perfect performance goes mostly to an Engineer at
> > Altera
> > > who worked with me for over a week until we had it perfect.
> > >
> > > One thing was that Read_Latency="1" had to be added to the Interface
to
> > User
> > > Logic settings. (see below for the entire settings list)
> > >
> > > Ken
> > >
> > > SYSTEM_BUILDER_INFO
> > > {
> > > Bus_Type = "avalon";
> > > Address_Alignment = "dynamic";
> > > Address_Width = "2";
> > > Data_Width = "32";
> > > Has_IRQ = "1";
> > > Base_Address = "0x010019A0";
> > > Has_Base_Address = "1";
> > > Read_Latency = "1";
> > > Read_Wait_States = "0.0cycles";
> > > Write_Wait_States = "0.0cycles";
> > > Setup_Time = "0.0cycles";
> > > Hold_Time = "0.0cycles";
> > > Is_Memory_Device = "1";
> > > Uses_Tri_State_Data_Bus = "0";
> > > Is_Enabled = "1";
> > > MASTERED_BY SCAN_IN_DMA/read_master
> > > {
> > > priority = "1";
> > > }
> > > IRQ_MASTER cpu/data_master
> > > {
> > > IRQ_Number = "0";
> > > }
> > > MASTERED_BY cpu/data_master
> > > {
> > > priority = "1";
> > > }
> > > }
> > >
> > >
> > > "David Brown" <david@no.westcontrol.spam.com> wrote in message
> > > news:cjrh8o$ck5$1@news.netpower.no...
> > > >
> > > > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in
message
> > > > news:10lnrtjlg7sff75@news.supernews.com...
> > > > >
> > > > > "Markus Meng" <meng.engineering@bluewin.ch> wrote in message
> > > > > news:aaaee51b.0409290819.a6020e5@posting.google.com...
> > > > > > Hi all [SOPC users],
> > > > > >
> > > > > > is there a way a can configure the read burst length of the
> > > > > > standard SDRAM controller within SOPC 4.1?
> > > > > >
> > > > > > Best Regards
> > > > > > Markus
> > > > >
> > > > > Hi Markus,
> > > > >
> > > > > You might try asking this over on the Nios Forum
> (www.niosforum.com).
> > > I'd
> > > > > like to know the answer as well. I looked through the
controller's
> > > > > class.ptf file and even the verilog source and don't see anything.
> > > > >
> > > > > On writes however, I'm getting bursts of at least 480 long words
at
> > one
> > > > > clock per word. (my system is running at 75MHz)
> > > > >
> > > >
> > > > Did you have to do anything special to achieve that? I have a
custom
> > > > peripheral that is writing as fast as it can to the sdram, but I'm
> > getting
> > > > one 32-bit write every 3 clocks. With the prototype system I have
at
> > the
> > > > moment, that's good enough, but I'd like to improve on it when we
> start
> > > > making the real thing. When reading, I'm getting one read every 2
> > > clocks -
> > > > again, it's not ideal but it works. I'd expect one read/write per
> clock
> > > for
> > > > most of the burst, with some waits while changing banks or
refreshing.
> > > >
> > > > Also, my reader and writer peripherals are independant, so sometimes
> > they
> > > > coincide. The Avalone bus arbitration apparently cannot take
bursting
> > > into
> > > > account, and swaps between the two accesses. Is there any way this
> can
> > be
> > > > improved upon, or do I have to implement my own mini-arbitrator to
> > control
> > > > the two peripherals?
> > > >
> > > >
> > > >
> > >
> > >
> >
> >
>
>
Article: 74282Austin Lesea <austin@xilinx.com> wrote > Not mentioned here is that ASICs suffer a 10:1 disadvantage in single > event upsets. Every single upset in an ASIC is a functional failure > (plus they are a lot more sensitive being the smallest structure > possible). Only 1:10 SEUs in a FPGA cause a functional failure. The > two factors cancel out. We take 10X more to do the same job, but have > 1/10 the upset rate, so we come back to parity on hardness against > cosmic ray neutron showers. Many folks erroniously believe that ASICs > are better with respect to SEUs (or conversely FPGAs are worse than > ASICs): they are not. Could you explain, why only 1 out of 10 SEU in a Xilinx Fpga will be a functional failure? Are there inplicit redundancies inside a Xilinx fpga? And are there possibilities, that an SEU changes the function of the fpga in that whay that e.g. a OR changes to an AND? bye ThomasArticle: 74283
hi i have a question: i have the sparten 3 starter kit from digilent. i use the ise web pack from xilinx and i would like to know what i have to do to programm the fpga so it loads my programm after power on. what i figured out so far is that i have to programm the onboard flash. but how? any jumper or software settings? thanks urbanArticle: 74284
Hi, I have several signals in my design which are outputs that is they are connected to output pin symbols in my schematic top level file. BUT these several output signals are NOT assigned to PINS. Does the compiler (QuartusII) remove these "unused" signals or are they preserved? Thank you for your help. Rgds AndréArticle: 74285
Urban Stadler schrieb: > i have a question: > i have the sparten 3 starter kit from digilent. > i use the ise web pack from xilinx and i would like to know what i have to > do to programm the fpga so it loads my programm after power on. > what i figured out so far is that i have to programm the onboard flash. but > how? > any jumper or software settings? https://digilent.us/Data/Products/S3BOARD/S3BOARD-rm.pdf Chapter 10 and 11. FPGA and Flash are part of the onboard JTAG chain. The Xilinx iMPACT software should recognize them - provided that the Flash PROM is enabled (Jumper JP1). Best regards, Markus.Article: 74286
I was just thinking about: 1M/250k = 4 customers, ok? Why Xilinx, Altera, etc, give us prices for 250k pcs??? DSPs vendors had the same behavior some years ago, but now they use a much more usefull range: price/10k pcs, sometimes price/1k pcs! Does someone else agree? Luiz Carlos.Article: 74287
Luiz Carlos wrote: > I was just thinking about: > > 1M/250k = 4 customers, ok? > > Why Xilinx, Altera, etc, give us prices for 250k pcs??? > > DSPs vendors had the same behavior some years ago, but now they use a > much more usefull range: price/10k pcs, sometimes price/1k pcs! > > Does someone else agree? > > Luiz Carlos. Maybe they sells in theses qty for company like Avnet ... then avnet gives the price for 10k, 1k, and even 100 pieces. SylvainArticle: 74288
################################################################################### International Workshop on Applied Reconfigurable Computing (ARC 2005) Algarve, Portugal, February 22, 2005 http://w3.ualg.pt/~jmcardo/arc2005 ################################################################################### SECOND CALL FOR PAPERS held in connection with IADIS International Conference Applied Computing 2005 (http://www.iadis.org/ac2005/) Reconfigurable computing architectures are becoming especially important for many computing systems. Their use might lead to characteristics - such as high-performance, energy efficiency, and flexibility - not achieved by other forms of computing. Furthermore, these architectures can be an important support to microprocessors in the next generation of computing devices. With so many amenities, this has become an exciting and promising research area. This one-day workshop aims to bring together practitioners and researchers from academia and industry, especially interested on the use of reconfigurable computing platforms as the mechanism choice to perform computing. The workshop is an associated event of the IADIS International Conference Applied Computing 2005 and it will take place in Algarve on February 22, 2005. Algarve is located in the south of Portugal, bordered by the Atlantic ocean, and it is well known by its mild and mellow climate (with a radiant sun), beautiful and impressive beaches and landscapes, golf courses, delicious dishes (including seafood and fresh fish dishes), and a relaxed life style. Topics of Interest Suggested topics of interest include, but are not restricted to: - Methods and Tools (High-Level Compilers, Simulation, Estimation, Design space exploration, Languages to program reconfigurable systems, etc.) - Architectures (Fine-grained, coarse-grained, and mixed-grained, Multiprocessor-based reconfigurable platforms, Microprocessors with tightly-coupled reconfigurable hardware, etc.) - Applications (High-Performance Systems, Use of reconfigurable computing in embedded systems, robotics, digital signal processing, etc.) - Teaching reconfigurable computing - Surveys and Future Trends - Benchmarks (papers presenting benchmarks publicly available to be used by the reconfigurable computing community are especially welcome) Submissions Authors are invited to submit original work in the following formats: - Full papers (8 pages at the maximum): they should include mainly accomplished results; - Short papers (4 pages at the maximum): they should be mostly composed of work in progress reports or fresh development; - Posters (2 pages at the maximum); - One-hour tutorials: Tutorials can be proposed by scholars or company representatives. A proposal of maximum 250 words is expected. Submissions should be sent as an e-mail attachment in pdf format to: jmcardo@ualg.pt - in order to maintain a blind review no information about authors should be included in the papers being submitted - the format of the papers should be according to IADIS format rules - the email should include the title of the paper being submitted, the names and affiliations of the authors, and should identify if it is a full, short, poster, or tutorial submission. Evaluation Each paper will be reviewed by at least three members of the program committee. Important Dates - Submission deadline: 15 October, 2004 - Notification to authors: 19 November, 2004 - Final Camera-Ready Submission and Early Registration: 3 December, 2004 - Late Registration: After 3 December, 2004 - Workshop: 22 February, 2005 Publication - The proceedings of the workshop will be published as a book with ISBN and the papers will be included in the CD-ROM of the IADIS International Conference Applied Computing. Workshop Chair - João M. P. Cardoso, University of Algarve, Portugal Email: jmcardo@ualg.pt Program Committee - António Ferrari, University of Aveiro, Portugal - Eduardo Marques, USP, Brazil - George Constantinides, Imperial College, UK - Gordon Brebner, Xilinx, USA - Horácio Neto, INESC-ID/IST, Portugal - José Nelson Amaral, University of Alberta, Canada - José Sousa, INESC-ID/IST, Portugal - Jürgen Becker, Universität Karlsruhe (TH), Germany - Marco Platzner, Swiss Federal Institute of Technology (ETH), Switzerland - Markus Weinhardt, PACT Informationstechnologie AG, Germany - Mihai Budiu, Carnegie Mellon University, USA - Milan Vasilko, Bournemouth University, UK - Nader Bagherzadeh, University of California, Irvine, USA - Pedro Diniz, University of Southern California/ISI, USA - Peter Athanas, Virginia Tech., USA - Peter Cheung, Imperial College, UK - Ranga Vemuri, University of Cincinnati, USA - Reiner Hartenstein, University of Kaiserslautern, Germany - Roger Woods, The Queen's University of Belfast, UK - Roman Hermida, Universidad Complutense, Madrid, Spain - Russell Tessier, University of Massachusetts, USA - Serge Vernalde, IMEC vzw, Belgium - Stamatis Vassiliadis, Delft University of Technology, The Netherlands - Tim Callahan, SRC Computers, USA - Wayne Luk, Imperial College, UK Workshop Secretariat - secretariat@iadis.orgArticle: 74289
Austin wrote: > > But never silent. > Google and I respectfully disagree with you. Taking just the most recent thread as an example: http://groups.google.com/groups?hl=en&lr=&q=s3+dci+ramp+fpga You and Steve were both quick to discount the possiblity of a parallel DCI startup transient triggering the S3 VCCO ESD circuit; yet when I rephrased my original post to be less ambiguous, there was no response. Outstanding questions from that thread: - Why is there no SSO data for VQ/PQ/TQ packages in the S3 datasheet? - Why did the blank column for said SSO data dissapear? - Has Xilinx considered, tested, or characterized the possibility of triggering the Spartan3 VCCO ESD circuit with an internal VCCO rail collapse induced by the SSO-like effects of the parallel DCI terminator startup current in the leaded packages? I haven't completed an S3 DCI design yet, so I haven't actually witnessed this (hypothetical) problem, but past experience coupled with the description of the VCCO ramp problem led me to ask the question. BrianArticle: 74290
Are you reading sdram or writing? I'm writing sdram in one clock @75MHz.
Since the sc_fifo is good to 200+MHz and has look ahead, in theory it should
be easy to achieve one clock access into (or out of) any Nios/SOPC system.
Your dma setup sounds useful. How do you setup the dma independent of the
Nios? Do you have external logic writing to its control registers? Also,
when you stall the dma with waitRequest, it doesn't stall the Avalon bus
does it?
I think I'll try to set that up in my system so I can dma in chunks that
make sense to my application instead of fifo almost full.
Ken
"David Brown" <david@no.westcontrol.spam.com> wrote in message
news:ck2s3m$5g2$1@news.netpower.no...
> I've now tried something similar - I removed my own master for my reader,
> and replaced it with a standard DMA component. This feeds a fifo (via a
> slave port on my reader component, which controls the "waitRequest" line
in
> order to stall the DMA when the fifo is fairly full until it is nearly
empty
> again). I actually implemented a small master to control the DMA,
starting
> transfers automatically and independantly of the Nios. It all works fine,
> except...I get one read every two cycles, exactly as when using my own
> master.
>
> When I ran at 50 MHz instead of 60 MHz, the bursts were one read per
cycle.
> I was getting some corruption, but I suspect that was a matter of the
phase
> for the sdram clock being not quite right for 50 MHz, so I'm worried
there.
> However, it looks very much like the standard Nios II sdram controller
with
> the dev kit sdram and default timings won't run properly at 60 MHz. Could
> that be the case?
>
> David
>
>
>
> "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message
> news:10m7o2hf84dkhce@news.supernews.com...
> >
> > You've got it. I generate a IRQ based on the fifo level and then in the
> ISR
> > I setup the dma to dump the fifo to an sdram buffer. The fifo is being
> > filled at about one word every 700ns and when the fifo level reaches 480
> the
> > IRQ dump process is triggered. The interrupt latency is about 8uS and
the
> > dma itself takes approximately 485 system clocks. (other code is
hammering
> > the sdram in parallel + sdram refresh etc.)
> >
> > Here is the fifo instantiation:
> >
> > NFIFO : scfifo WITH (
> > INTENDED_DEVICE_FAMILY = "Cyclone",
> > LPM_WIDTH = 36,
> > LPM_NUMWORDS = 512,
> > LPM_WIDTHU = 9,
> > LPM_TYPE = "scfifo",
> > LPM_SHOWAHEAD = "ON",
> > OVERFLOW_CHECKING = "OFF",
> > UNDERFLOW_CHECKING = "OFF",
> > USE_EAB = "ON",
> > ADD_RAM_OUTPUT_REGISTER = "ON"
> > );
> >
> > Then I hook the chipselect (CS) and read signals from the IUL port
thusly:
> >
> > RD_DN.d = SCAN_IN_CS & SCAN_IN_RE;
> > RD_DN.clk = CLK100M;
> >
> > NFIFO.rdreq = RD_DN;
> > NF_OUT[35..0] = NFIFO.q[35..0];
> >
> > NF_OUT[31..0] is connected directly to the data in port of IUL.
> >
> > CLK100M is actually the sysclk which is 75 MHz right now. Timing
analysis
> > says I'm good to 97MHz, but I haven't pushed it yet.
> >
> > I'm pretty sure this info with the system builder IUL port settings I
> posted
> > earlier are all you need. Hope this helps.
> >
> > Ken
> >
> > "David Brown" <david@no.westcontrol.spam.com> wrote in message
> > news:ck05od$t7e$1@news.netpower.no...
> > >
> > > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message
> > > news:10m6j0ko352cb9b@news.supernews.com...
> > > >
> > > > Hi David,
> > > >
> > > > Sorry for the delay I've been out of town with no access.
> > > >
> > > > I'm using the standared included dma peripheral to empty a standard
> > single
> > > > clock fifo. I did not modify any of the master priorities.vr
> > > >
> > >
> > > So you have a DMA device set up to read from a fifo as a slave. Did
you
> > > make a class.ptf file for the fifo slave, that you could post here?
Am
> I
> > > right in thinking you used a standard fifo (i.e., readReq triggers a
new
> > > read) rather than a read-ahead fifo (i.e., readReq works as an
> > acknowledge)
> > > ? I think the read-ahead version would eliminate your need of a read
> > > latency. Also, were you feeding data into the fifo at full speed? In
> my
> > > application, the other end of the fifo is much slower (roughly 1/6 of
> the
> > > system speed), so I'd like to let the fifo build up a bit before
> starting
> > a
> > > burst - perhaps triggering a burst start when it is half-full, and
> > stopping
> > > again when it is empty. I expect to write my own slave, wrapping the
> fifo
> > > and providing such control signals (I have much of the code for that
> from
> > my
> > > original version using my own master). Would I be correct in thinking
> > that
> > > the way to handle this is for the DMA to be set up to transfer a given
> > > number of words, and have the slave assert waitRequest to pause the
DMA
> > > reads until the fifo was half-full?
> > >
> > > David
> > >
> > >
> > >
> > > > I can post a test project to the Nios Forum that runs on the Cyclone
> > > devkit
> > > > board, but I don't have time to document it very well.
> > > >
> > > > If anyone is in a bind they can contact me through the forum and I
> will
> > > > email them a .zip of the project. (~4MB)
> > > >
> > > > The credit for this perfect performance goes mostly to an Engineer
at
> > > Altera
> > > > who worked with me for over a week until we had it perfect.
> > > >
> > > > One thing was that Read_Latency="1" had to be added to the Interface
> to
> > > User
> > > > Logic settings. (see below for the entire settings list)
> > > >
> > > > Ken
> > > >
> > > > SYSTEM_BUILDER_INFO
> > > > {
> > > > Bus_Type = "avalon";
> > > > Address_Alignment = "dynamic";
> > > > Address_Width = "2";
> > > > Data_Width = "32";
> > > > Has_IRQ = "1";
> > > > Base_Address = "0x010019A0";
> > > > Has_Base_Address = "1";
> > > > Read_Latency = "1";
> > > > Read_Wait_States = "0.0cycles";
> > > > Write_Wait_States = "0.0cycles";
> > > > Setup_Time = "0.0cycles";
> > > > Hold_Time = "0.0cycles";
> > > > Is_Memory_Device = "1";
> > > > Uses_Tri_State_Data_Bus = "0";
> > > > Is_Enabled = "1";
> > > > MASTERED_BY SCAN_IN_DMA/read_master
> > > > {
> > > > priority = "1";
> > > > }
> > > > IRQ_MASTER cpu/data_master
> > > > {
> > > > IRQ_Number = "0";
> > > > }
> > > > MASTERED_BY cpu/data_master
> > > > {
> > > > priority = "1";
> > > > }
> > > > }
> > > >
> > > >
> > > > "David Brown" <david@no.westcontrol.spam.com> wrote in message
> > > > news:cjrh8o$ck5$1@news.netpower.no...
> > > > >
> > > > > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in
> message
> > > > > news:10lnrtjlg7sff75@news.supernews.com...
> > > > > >
> > > > > > "Markus Meng" <meng.engineering@bluewin.ch> wrote in message
> > > > > > news:aaaee51b.0409290819.a6020e5@posting.google.com...
> > > > > > > Hi all [SOPC users],
> > > > > > >
> > > > > > > is there a way a can configure the read burst length of the
> > > > > > > standard SDRAM controller within SOPC 4.1?
> > > > > > >
> > > > > > > Best Regards
> > > > > > > Markus
> > > > > >
> > > > > > Hi Markus,
> > > > > >
> > > > > > You might try asking this over on the Nios Forum
> > (www.niosforum.com).
> > > > I'd
> > > > > > like to know the answer as well. I looked through the
> controller's
> > > > > > class.ptf file and even the verilog source and don't see
anything.
> > > > > >
> > > > > > On writes however, I'm getting bursts of at least 480 long words
> at
> > > one
> > > > > > clock per word. (my system is running at 75MHz)
> > > > > >
> > > > >
> > > > > Did you have to do anything special to achieve that? I have a
> custom
> > > > > peripheral that is writing as fast as it can to the sdram, but I'm
> > > getting
> > > > > one 32-bit write every 3 clocks. With the prototype system I have
> at
> > > the
> > > > > moment, that's good enough, but I'd like to improve on it when we
> > start
> > > > > making the real thing. When reading, I'm getting one read every 2
> > > > clocks -
> > > > > again, it's not ideal but it works. I'd expect one read/write per
> > clock
> > > > for
> > > > > most of the burst, with some waits while changing banks or
> refreshing.
> > > > >
> > > > > Also, my reader and writer peripherals are independant, so
sometimes
> > > they
> > > > > coincide. The Avalone bus arbitration apparently cannot take
> bursting
> > > > into
> > > > > account, and swaps between the two accesses. Is there any way
this
> > can
> > > be
> > > > > improved upon, or do I have to implement my own mini-arbitrator to
> > > control
> > > > > the two peripherals?
> > > > >
> > > > >
> > > > >
> > > >
> > > >
> > >
> > >
> >
> >
>
>
Article: 74291I'm trying to run Synplify on a Fedora Core 2 platform but I get the following error message: "relocation error: /../synplify_77/linux/mfw/lib-linux_optimized/libkernel32.so: symbol errno, version GLIBC_2.0 not defined in file libc.so.6 with link time reference" I'm in no way a Linux expert so this means nothing to me. Advice? regards David Kallberg FPGAworldArticle: 74292
"Extrarius" <filtered@psychosanity.com> wrote in message news:ve19d.1372$iC4.305@fe2.texas.rr.com... > I'm looking for advice and resources to help me learn about hardware > design and FPGAs. So far I've done tons of googling, and I've found tons > of information about microcontrollers and things like that, but in another > newsgroup thread[1] it was suggested that an FPGA might be a better > solution for my current goal project: An nes-level gaming 'console'. This > is just something I think would be interesting to do, and I realize it > won't be the first thing I complete, which is why I'm asking for help > getting started with the first steps of thousands that will lead to it's > completion. > > Since I've been doing CS for most of my life(as a hobby, though I'm now > working on a CS degree) and I've only recently taken an interest in EE as > a hobby, I don't know much at all about electronics or the like. From > suggestions in another newsgroup thread[1], I've been reading the > recommended books and learning the basic theory and practice, but I think > I'm ready to start working on more advanced things as well. I'm also being > exposed to VHDL in a Digital Logic(aka boolean algebra) class required for > my degree. Really, the class doesn't cover VHDL, but it is covered in the > book we're using so I've been learning it during class when I read the > book and ignore the incomprehensible professor. > > I'm looking for a good starter kit for FPGAs. So far, Xilinx's Spartan-3 > starter kit seems to be the least expensive kit that includes everything > needed to get started. Like I said, I'm still learning electronics, so > designing my own board is most likely out my reach at the moment, and I'm > a college student so as the cliche goes I don't have tons of money to > spend on hobbies. > > Any suggestions for books, sites to read, FPGA starter kits, etc would be > greatly appreciated. > > [1] = > http://groups.google.com/groups?threadm=4781a87e.0409061701.5eef2236%40posting.google.com > www.fpgaarcade.com not a beginneers project though www.digilentinc.com they make the spartan3 starter kit for xilinx and have other boards and addon modules including usb, ethernet etc www.fpga4fun.com have a few boards for sale and good tutorials. http://www.burched.biz/ sells boards as do www.xess.com AlexArticle: 74293
"Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message
news:10ma9fsff160o2b@news.supernews.com...
>
> Are you reading sdram or writing? I'm writing sdram in one clock @75MHz.
> Since the sc_fifo is good to 200+MHz and has look ahead, in theory it
should
> be easy to achieve one clock access into (or out of) any Nios/SOPC system.
>
I've got both in the system - at the moment, I've been working on the
reader. My writer is also sub-optimal - it seems to be 3 cycles per word at
60 MHz, and 2 cycles per word at 50 MHz, although I haven't tried
fine-tuning it as much (and I haven't tried using a standard DMA component).
> Your dma setup sounds useful. How do you setup the dma independent of the
> Nios? Do you have external logic writing to its control registers? Also,
> when you stall the dma with waitRequest, it doesn't stall the Avalon bus
> does it?
My reader component has 3 Avalon bus interfaces - two slaves and a master.
One slave is used for control and setup, and is connected to the Nios II
data master. The other slave is for the fifo input - it has no address
decoding, and simply accepts words written to it and feeds them into the
fifo. It generates a waitRequest signal as necessary to stall its master
when the fifo does not want more data (after the fifo is mostly filled,
waitRequest is asserted until the fifo is mostly empty again). This slave
is connected to the dma's writer master. The dma's reader master is
connected to the sdram slave (as are the Nios masters), while the dma's
slave is connected to the reader's master. Thus the whole system has three
independant Avalon buses - there is the main one used by the Nios and the
dma reader, there is a private one between the dma writer and the fifo
slave, and a second private one between the reader's master and the dma's
slave port. The reader master port simple reloads the dma's configuration
and starts it running on a regular basis.
Being a private bus, there is no problem with stalling the dma writer master
with a waitRequest - the other buses run regardless.
The whole thing is a little under 100 lines of Confluence code (plus another
150 lines for the component at the other end of the fifo).
David
>
> I think I'll try to set that up in my system so I can dma in chunks that
> make sense to my application instead of fifo almost full.
>
> Ken
>
>
>
> "David Brown" <david@no.westcontrol.spam.com> wrote in message
> news:ck2s3m$5g2$1@news.netpower.no...
> > I've now tried something similar - I removed my own master for my
reader,
> > and replaced it with a standard DMA component. This feeds a fifo (via a
> > slave port on my reader component, which controls the "waitRequest" line
> in
> > order to stall the DMA when the fifo is fairly full until it is nearly
> empty
> > again). I actually implemented a small master to control the DMA,
> starting
> > transfers automatically and independantly of the Nios. It all works
fine,
> > except...I get one read every two cycles, exactly as when using my own
> > master.
> >
> > When I ran at 50 MHz instead of 60 MHz, the bursts were one read per
> cycle.
> > I was getting some corruption, but I suspect that was a matter of the
> phase
> > for the sdram clock being not quite right for 50 MHz, so I'm worried
> there.
> > However, it looks very much like the standard Nios II sdram controller
> with
> > the dev kit sdram and default timings won't run properly at 60 MHz.
Could
> > that be the case?
> >
> > David
> >
> >
> >
> > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message
> > news:10m7o2hf84dkhce@news.supernews.com...
> > >
> > > You've got it. I generate a IRQ based on the fifo level and then in
the
> > ISR
> > > I setup the dma to dump the fifo to an sdram buffer. The fifo is
being
> > > filled at about one word every 700ns and when the fifo level reaches
480
> > the
> > > IRQ dump process is triggered. The interrupt latency is about 8uS and
> the
> > > dma itself takes approximately 485 system clocks. (other code is
> hammering
> > > the sdram in parallel + sdram refresh etc.)
> > >
> > > Here is the fifo instantiation:
> > >
> > > NFIFO : scfifo WITH (
> > > INTENDED_DEVICE_FAMILY = "Cyclone",
> > > LPM_WIDTH = 36,
> > > LPM_NUMWORDS = 512,
> > > LPM_WIDTHU = 9,
> > > LPM_TYPE = "scfifo",
> > > LPM_SHOWAHEAD = "ON",
> > > OVERFLOW_CHECKING = "OFF",
> > > UNDERFLOW_CHECKING = "OFF",
> > > USE_EAB = "ON",
> > > ADD_RAM_OUTPUT_REGISTER = "ON"
> > > );
> > >
> > > Then I hook the chipselect (CS) and read signals from the IUL port
> thusly:
> > >
> > > RD_DN.d = SCAN_IN_CS & SCAN_IN_RE;
> > > RD_DN.clk = CLK100M;
> > >
> > > NFIFO.rdreq = RD_DN;
> > > NF_OUT[35..0] = NFIFO.q[35..0];
> > >
> > > NF_OUT[31..0] is connected directly to the data in port of IUL.
> > >
> > > CLK100M is actually the sysclk which is 75 MHz right now. Timing
> analysis
> > > says I'm good to 97MHz, but I haven't pushed it yet.
> > >
> > > I'm pretty sure this info with the system builder IUL port settings I
> > posted
> > > earlier are all you need. Hope this helps.
> > >
> > > Ken
> > >
> > > "David Brown" <david@no.westcontrol.spam.com> wrote in message
> > > news:ck05od$t7e$1@news.netpower.no...
> > > >
> > > > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in
message
> > > > news:10m6j0ko352cb9b@news.supernews.com...
> > > > >
> > > > > Hi David,
> > > > >
> > > > > Sorry for the delay I've been out of town with no access.
> > > > >
> > > > > I'm using the standared included dma peripheral to empty a
standard
> > > single
> > > > > clock fifo. I did not modify any of the master priorities.vr
> > > > >
> > > >
> > > > So you have a DMA device set up to read from a fifo as a slave. Did
> you
> > > > make a class.ptf file for the fifo slave, that you could post here?
> Am
> > I
> > > > right in thinking you used a standard fifo (i.e., readReq triggers a
> new
> > > > read) rather than a read-ahead fifo (i.e., readReq works as an
> > > acknowledge)
> > > > ? I think the read-ahead version would eliminate your need of a
read
> > > > latency. Also, were you feeding data into the fifo at full speed?
In
> > my
> > > > application, the other end of the fifo is much slower (roughly 1/6
of
> > the
> > > > system speed), so I'd like to let the fifo build up a bit before
> > starting
> > > a
> > > > burst - perhaps triggering a burst start when it is half-full, and
> > > stopping
> > > > again when it is empty. I expect to write my own slave, wrapping
the
> > fifo
> > > > and providing such control signals (I have much of the code for that
> > from
> > > my
> > > > original version using my own master). Would I be correct in
thinking
> > > that
> > > > the way to handle this is for the DMA to be set up to transfer a
given
> > > > number of words, and have the slave assert waitRequest to pause the
> DMA
> > > > reads until the fifo was half-full?
> > > >
> > > > David
> > > >
> > > >
> > > >
> > > > > I can post a test project to the Nios Forum that runs on the
Cyclone
> > > > devkit
> > > > > board, but I don't have time to document it very well.
> > > > >
> > > > > If anyone is in a bind they can contact me through the forum and I
> > will
> > > > > email them a .zip of the project. (~4MB)
> > > > >
> > > > > The credit for this perfect performance goes mostly to an Engineer
> at
> > > > Altera
> > > > > who worked with me for over a week until we had it perfect.
> > > > >
> > > > > One thing was that Read_Latency="1" had to be added to the
Interface
> > to
> > > > User
> > > > > Logic settings. (see below for the entire settings list)
> > > > >
> > > > > Ken
> > > > >
> > > > > SYSTEM_BUILDER_INFO
> > > > > {
> > > > > Bus_Type = "avalon";
> > > > > Address_Alignment = "dynamic";
> > > > > Address_Width = "2";
> > > > > Data_Width = "32";
> > > > > Has_IRQ = "1";
> > > > > Base_Address = "0x010019A0";
> > > > > Has_Base_Address = "1";
> > > > > Read_Latency = "1";
> > > > > Read_Wait_States = "0.0cycles";
> > > > > Write_Wait_States = "0.0cycles";
> > > > > Setup_Time = "0.0cycles";
> > > > > Hold_Time = "0.0cycles";
> > > > > Is_Memory_Device = "1";
> > > > > Uses_Tri_State_Data_Bus = "0";
> > > > > Is_Enabled = "1";
> > > > > MASTERED_BY SCAN_IN_DMA/read_master
> > > > > {
> > > > > priority = "1";
> > > > > }
> > > > > IRQ_MASTER cpu/data_master
> > > > > {
> > > > > IRQ_Number = "0";
> > > > > }
> > > > > MASTERED_BY cpu/data_master
> > > > > {
> > > > > priority = "1";
> > > > > }
> > > > > }
> > > > >
> > > > >
> > > > > "David Brown" <david@no.westcontrol.spam.com> wrote in message
> > > > > news:cjrh8o$ck5$1@news.netpower.no...
> > > > > >
> > > > > > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in
> > message
> > > > > > news:10lnrtjlg7sff75@news.supernews.com...
> > > > > > >
> > > > > > > "Markus Meng" <meng.engineering@bluewin.ch> wrote in message
> > > > > > > news:aaaee51b.0409290819.a6020e5@posting.google.com...
> > > > > > > > Hi all [SOPC users],
> > > > > > > >
> > > > > > > > is there a way a can configure the read burst length of the
> > > > > > > > standard SDRAM controller within SOPC 4.1?
> > > > > > > >
> > > > > > > > Best Regards
> > > > > > > > Markus
> > > > > > >
> > > > > > > Hi Markus,
> > > > > > >
> > > > > > > You might try asking this over on the Nios Forum
> > > (www.niosforum.com).
> > > > > I'd
> > > > > > > like to know the answer as well. I looked through the
> > controller's
> > > > > > > class.ptf file and even the verilog source and don't see
> anything.
> > > > > > >
> > > > > > > On writes however, I'm getting bursts of at least 480 long
words
> > at
> > > > one
> > > > > > > clock per word. (my system is running at 75MHz)
> > > > > > >
> > > > > >
> > > > > > Did you have to do anything special to achieve that? I have a
> > custom
> > > > > > peripheral that is writing as fast as it can to the sdram, but
I'm
> > > > getting
> > > > > > one 32-bit write every 3 clocks. With the prototype system I
have
> > at
> > > > the
> > > > > > moment, that's good enough, but I'd like to improve on it when
we
> > > start
> > > > > > making the real thing. When reading, I'm getting one read every
2
> > > > > clocks -
> > > > > > again, it's not ideal but it works. I'd expect one read/write
per
> > > clock
> > > > > for
> > > > > > most of the burst, with some waits while changing banks or
> > refreshing.
> > > > > >
> > > > > > Also, my reader and writer peripherals are independant, so
> sometimes
> > > > they
> > > > > > coincide. The Avalone bus arbitration apparently cannot take
> > bursting
> > > > > into
> > > > > > account, and swaps between the two accesses. Is there any way
> this
> > > can
> > > > be
> > > > > > improved upon, or do I have to implement my own mini-arbitrator
to
> > > > control
> > > > > > the two peripherals?
> > > > > >
> > > > > >
> > > > > >
> > > > >
> > > > >
> > > >
> > > >
> > >
> > >
> >
> >
>
>
Article: 74294
I 'd like to simulate my design with a memory simulation model.
The vhdl for memory model is like this:
-------------------------------------------------------------------------------
constant weight_L : integer := 16;
constant mean_L : integer := 28;
constant variance_L : integer := 24;
type Gauss_parameters is record
weight : std_logic_vector(weight_L-1 downto 0);
mean1 : std_logic_vector(mean_L-1 downto 0);
mean2 : std_logic_vector(mean_L-1 downto 0);
mean3 : std_logic_vector(mean_L-1 downto 0);
variance : std_logic_vector(variance_L-1 downto 0);
end record;
type ram_data_type is array (0 to 352*288*9) of Gauss_parameters;
signal ram_data : ram_data_type;
-------------------------------------------------------------------------------
whenever I use modelsim to start simulation, the memory uesed by modelsim
will exceed 4G memory, and modelsim crashs. I am using Sun server with 16G
RAM. Can anyone tell me whether it is the problem of my design or the bug with
modelsim. Is there another way to write memory simulation model that uses much
less memory during simulation?
/hongtu
Article: 74295Hongtu wrote: > whenever I use modelsim to start simulation, the memory uesed by modelsim > will exceed 4G memory, and modelsim crashs. I am using Sun server with 16G > RAM. Can anyone tell me whether it is the problem of my design or the bug with > modelsim. Is there another way to write memory simulation model that uses much > less memory during simulation? If the array is sparse you could dynamically reserve the memory. Also use variable instead of signal for the array, because signal has much more state and consumes more memory. You could also use bit* types because they have less states than std_logic type. And if you want to use 64b modelsim you need to install that separately and set the scripts accordingly. 64b modelsim is not normally used, because it is ~25% slower than the 32b version. --KimArticle: 74296
Hello, I have applied that clock setting and it seems to work. One more question: My PLL generates two clocks C0, C1 for internal use and a clock E for external use. The problem: I have an external PHY which needs two clocks, one for data allignment and one for basic clock function. Is it possible to route the E clock to two output pins ? I have tried to route to PLL2_OUT_p and to PLL2_OUT_n. I have made two different clock settings for that pins (device EP1C12F226C7 with pins J16: PLL2_OUT+ and K15: PLL2_OUT-) derived from the CLK_30 setting but the compiler complains that the design cannot be fit. The error message is the following: "Error: Can't place enhanced PLL pll1 in PLL location PLL_2 because PLL requires 2 external clock output ports but the PLL location only has 1 external clock outpit ports. How can I solve this problem ? Thank you for your help. Rgds André > Hello André, > > Here is what you need to do: > > 1.- Define a Base Clock for your clock pin. This clock should have a > requirement of 30MHz (Use Assignments->Settings->Timing Requirements > and Options->Clocks) > > 2.- Define a derived clock for the CLOCK_DIVIDER. This clock should > have the following characteristics: > > - based on the base clock defined on the clock pin (Step 1) > - multiply Fmax by 2 > - divide Fmax by 5 > 30 * 2 / 5 = 12 > - Do NOT set any offset value. This will make the Timing Analyzer auto > compute it. > > (Use Assignments->Settings->Timing Requirements and > Options->Clocks->New->Based On) > > Note that if there are any transfers between the pll input (30MHz) and > the pll output (12MHz), the timing analyzer is likely to find a setup > relationship (a requirement for this transfer). > > That should be it. All PLL outputs do not need a clock setting as the > Timing Analyzer auto generates them. The inverted clock out of c0 will > also be processed correctly by the Timing Analyzer. > > Hope this helps. > > - Subroto Datta > Altera Corp.Article: 74297
Hongtu wrote: > I 'd like to simulate my design with a memory simulation model. > The vhdl for memory model is like this: > > ------------------------------------------------------------------------------- > constant weight_L : integer := 16; > constant mean_L : integer := 28; > constant variance_L : integer := 24; > > type Gauss_parameters is record > weight : std_logic_vector(weight_L-1 downto 0); > mean1 : std_logic_vector(mean_L-1 downto 0); > mean2 : std_logic_vector(mean_L-1 downto 0); > mean3 : std_logic_vector(mean_L-1 downto 0); > variance : std_logic_vector(variance_L-1 downto 0); > end record; > type ram_data_type is array (0 to 352*288*9) of Gauss_parameters; > signal ram_data : ram_data_type; Yikes, a signal! Use a variable (in a process) instead. A signal takes much more memory because it has to drag along a complete event queue and all its attributes. A variable is much more light weight (up to a factor of ten, if I'm not mistaken). Still, the amount of memory will be quite large. Your array will take 113135616 (107M) std_logic bits. Using naturals for the record members will improve this. Paul.Article: 74298
Dear all, I'm currently using a Fast Pll clock output as main clock of my design inside an Altera Stratix device. I have some doubts about the usage of the Pll Lock signal (the output of the Fast Pll, which indicates the Pll locked the input clock). In particular, I'm currently assuming that, after power on, the Pll locks before the completion of the fpga configuration, so that the PLL clock output can feed the internal logic without any protection against VCO transients. If this is not correct, I should in some way gate the Pll clock output with the lock output. Any advice about this point ? Thanks in advanceArticle: 74299
John, Unfortunately the DFS part of the DCM will lose lock if you dynamically change M or D. Due to the hard sync feature, the oscillator risks stopping if the phase if off by too much (see CLKFX_STOPPED status bit). V4 has some changes to keep the oscilltor running even in adverse conditions, as does Spartan 3, but we haven't finished characterizing just how tolerant of the jumps the DFS is. And maybe we won't, as it isn't worth it (such a phase glitch on CLKIN would cause lots of other problems with timing violations in logic anyway). Changing M or D, and then reseting is supported, however. Turns out you can change the CLKIN frequency and the DFS will track, as long as the input changes slowly enoguh that the logic has time to follow it. Taps update every 3 (VII, II Pro, S3) or 6 (V4) clocks, so I suggest that one has at least 100 updates (300 or 600 clocks) before the input frequency is changed by more than a tap in phase (absolutely safe critieria for tracking). The DLL part risks running off either end of the delay line as it is trying to zero the skew as you change input frequency, so the DLL can not track a changing input outside of the specification in the data sheet. Austin John Williams wrote: > Hi Austin, > > Austin Lesea wrote: > >> I refer to this as a 'tap dance.' (please forgive my humor, but it is >> part of my personality....) Change the M, or D, or input frequency, >> and the 'tap dance' changes such that the loop stays locked, and the >> output remains phase and frequency locked to the input. >> >> In this way, the phase error (if the oscillator is perfect) is never >> worse than a tap value for one whole concurrence cycle (D cycles of >> input clock, or M cycles of output clock). > > > Any ideas (or experience) on what happens if you twiddle DCM > configuration bits on the fly (a la partial reconfig)? I'm guessing it > would be safe to hold the DCM in reset, change the tap configuration, > then restart it, but that's not much use if the DCM is clocking the very > same logic that is driving the partial reconfiguration :) > > I'm picturing a self-reconfiguring microblaze uClinux system dynamically > scaling its own clock... > > John
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