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On Wed, 13 Oct 2004, Simon Peacock wrote: > A word of caution here: > > Altium or Protel as it was called is a PCB software company... Nextar is > their FPGA development tools and both of these boards are designed to use > Altium's software. As such support outside this simple parameter will be > non existent. > Well... can't you just buy the devel. board and use the free Webpack or Quartus later ? (when the 30 day trial is finished). -- Sincerely, Jung KoArticle: 74551
Hi there, I have a xilinx test board which has 4 vertex2 and some wireless stuff. It connects P4 system through PCI. Here is the problem. When the channel (air) has sudden change, all the pins connected to the xilinx chips(vertex2 6000) goes up for short time. It remains high about 600 to 800ns. I also checked the ground pin which goes high too. If you have any idea, please let me know. I will appreciate it. Thanks ahead, Heeyong.Article: 74552
Hi I am working with Virtex II EMAC and daughter care phy. I am able to send packet on the wire from the mac and receive these packet back also. But If i ping (add an arp entry with MAC and IP) board I do not get these packets to come in. I am not using any kind of stack. I do get the packet onto the phy (atleast I think) but I don't generate any interrupt for the MAC. any ideas. thanks. TONYArticle: 74553
Sadly Xilinx has abandoned JBits. Question for Xilinx: with JBits now DOA, how are customers supposed to use the ICAPs? Are they now strictly intended for "swapping" a set of prebuilt configurations? Without something like JBits you can't really do runtime template assembly AFAICT... - a "alonzo" <rha_x@yahoo.com> writes: > Hello, > Does somebody know if the last version of JBits (3.0) will work with > spartans family? I know JBits 3.0 supports Virtex II, and an older version > supported Virtex... but .. Spartan is kind of a Virtex.. so .. have anyone > try this before? > > Thanks, > Alonzo. > -- I wrote my own mail server and it still has a few bugs. If you send me a message and it bounces, please forward the bounce message to megacz@gmail.com. Thanks!Article: 74554
Hi Everyone, Can anybody let me know where to buy the EPM1270 TQFP CPLD in a cheap price? I've checked altera.com, the online wholesale price is $4.25/pc for 500K units. But the distributor here would charge me over $24 for 10 pc. (ebay.com is not a good site for the stable supply) Any advice appreciated! -ZimmerArticle: 74555
On Mon, 11 Oct 2004 08:06:28 -0700, Vivek <> wrote:
In a Virtex-II part.
There are several constraints on which global buffers
and clock nets and clock pins can be used in a single
design. The shared resources make certain selections
mutually exclusive.
Here are some examples:
Although there are 16 global clock buffers (and therefore
16 global clock nets), you can only use 8 global clocks
in any quadrant of the FPGA. If your design uses 8 or less
clocks, then this is not too big a deal. When you use 9
through 16 clocks, you have to floor plan your design so
that all the logic in any quadrant does not use more than
8 clocks. (There may also be constraints on which of the
clocks these 8 can come from)
Adjacent global buffers share their inputs. If they are
using separate clocks, this is not too much of a problem,
but if you are using the BUFGMUX function, then this uses
both signals, which makes the adjacent BUFGMUX either
useless, or it must use the same inputs.
Primary and secondary buffers on opposite sides of the
FPGA share some output resources. This means that if
they are mutually exclusive to a quadrant. Confused yet?
(If BUFG1P is used to drive logic in the NW quadrant, then
BUFG1S on the opposite side of the chip can not drive into
the NW quadrant)
Then add in constraints of access to DCMs, and which DCM
outputs go to which buffers, Differential clock inputs,
and probably more stuff, and you have a pretty fun puzzle.
At a minimum, you need to read this document:
http://direct.xilinx.com/bvdocs/userguides/ug002.pdf
pages 58 through 77.
>What is the difference between GLKP and the GLKS?
In prior FPGA generations, The primaries had faster
connections to the clock input pins, but less clock
source options. The secondaries had more signal source
options, but were a little slower. In V-II, since they
share inputs, it would seem that the only difference is
the name.
>I am trying to figure out if i have enough global
>clock resources for the clocks. Right now I have
>about 7 clocks coming into the GLKP pins.
So you aren't yet at the 8 clock max per quadrant limit.
>When i instantiate a bufg, does it matter if its a bufg
>for GLKS or GLKP?
Yes. As the example above (here it is again)
(If BUFG1P is used to drive logic in the NW quadrant, then
BUFG1S on the opposite side of the chip can not drive into
the NW quadrant)
This is regardless of how many clock nets you have.
>Is there something to take into consideration between P or
>S or can i act like all of these are global buffers giving
>me 16 buffers in total?
There are 16 buffers, and there are 16 global nets on their
outputs, and there are 8 clock nets in each quadrant. To have
16 global clocks in a design takes some extremely careful
planning, and floor planning of logic at least into quadrants.
>Any help would be appreciatd thanks.
You really need to read the above reference, and then you can
refine your learning with the FPGA editor, where you can (with
considerable effort) see these interactions.
I would describe this all as gratuitiously complicated, but
what do I know?
Philip
===================
Philip Freidin
philip.freidin@fpga-faq.com
Host for WWW.FPGA-FAQ.COM
Article: 74556Adam Megacz wrote: > > Sadly Xilinx has abandoned JBits. Is this true? JBits support for V2 was announced just a few months ago. > Question for Xilinx: with JBits now DOA, how are customers supposed to > use the ICAPs? Are they now strictly intended for "swapping" a set of > prebuilt configurations? Without something like JBits you can't > really do runtime template assembly AFAICT... Your question has a false premise - customers *aren't* supposed to use ICAP. :-S ... OK so I'm joking, but only just... ICAP is there because it helps Xilinx test chips. They make it visible in the tools etc because it has some interesting research opportunities. It's a bit of a chicken and egg problem - if someone can demonstrate a killer-app for ICAP and partial-reconfig, then support will follow. But without support, developing the killer-app is very difficult... Regards, JohnArticle: 74557
Jung Ko wrote: > > On Wed, 13 Oct 2004, Simon Peacock wrote: > > > A word of caution here: > > > > Altium or Protel as it was called is a PCB software company... Nextar is > > their FPGA development tools and both of these boards are designed to use > > Altium's software. As such support outside this simple parameter will be > > non existent. > > > > Well... can't you just buy the devel. board and use the free Webpack or > Quartus later ? (when the 30 day trial is finished). I belive there is a pretty good Spartan 3 dev board available for $99 that Xilinx supports (XC3S200 vs. XC3S400). I don't know of any that cheap from Altera. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74558
that's as good as you can get.. unless you buy 1/2 a million "Zimmer" <zihu882@yahoo.com> wrote in message news:65a3fa49.0410131936.2bdeb565@posting.google.com... > Hi Everyone, > > Can anybody let me know where to buy the EPM1270 TQFP CPLD in a cheap > price? I've checked altera.com, the online wholesale price is $4.25/pc > for 500K units. But the distributor here would charge me over $24 for 10 > pc. (ebay.com is not a good site for the stable supply) > > Any advice appreciated! > > -ZimmerArticle: 74559
John Williams wrote: > > Adam Megacz wrote: > > > > Sadly Xilinx has abandoned JBits. > > Is this true? JBits support for V2 was announced just a few months ago. > > > Question for Xilinx: with JBits now DOA, how are customers supposed to > > use the ICAPs? Are they now strictly intended for "swapping" a set of > > prebuilt configurations? Without something like JBits you can't > > really do runtime template assembly AFAICT... > > Your question has a false premise - customers *aren't* supposed to use > ICAP. :-S ... OK so I'm joking, but only just... > > ICAP is there because it helps Xilinx test chips. They make it visible > in the tools etc because it has some interesting research opportunities. > > It's a bit of a chicken and egg problem - if someone can demonstrate a > killer-app for ICAP and partial-reconfig, then support will follow. But > without support, developing the killer-app is very difficult... Xilinx had a lot of new tool features they were supporting such as modular configuration. I was told that they were commited to supporting the Spartan 3 devices. But that support never materialized and I dont' see where the new V4 chips are supported yet. Maybe they just don't see much need and are dropping some of these advanced tools on the newer chips. Or maybe it is the lack of tri-state buffers. I know the Spartan 3 chips have none, do the Virtex 4 chips have any internal tri-states? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74560
> >mete wrote: > > > >> Is there method that is more efficient than regular division for > >> calculating modulus ? Well, it depends on what your divisor for the modulus operation is. If you are looking at some small values of divisor, then you can do something of this sort : 1. Start with modulus m = 0. 2. Take one bit at a time starting from the most significant bit. 3. Have one state for every modulus value (0..n-1, if you are doing modulo n). 4. Have a state diagram with the following transitions. If input is `1', then go to m = (2*m+1) mod n. If current input is `0' go to m = (2*m) mod n state. 5. You will have n states with 2n transitions. Run your dividend through this machine. 6. This is generic and well suited for small values of n. Of course, if you need a combinational implementation, or if you have special values of n, or if the operation needs to be signed, then the whole ballgame is different. Hope this helps. --shankarArticle: 74561
> Hi Andre, > > You could use the c0 & c1 output of the PLL's, where you give the c1 > an 180 deg shift, and both route them to output pins. The internal > routing within the device and the placement of the pins could give > some phase shift, but you could 'fiddle' around with that a little to > get it working. > > Karl. Hi Karl, thank you for your answer. The problem is that c0 is a clock with a different frequency used for internal operations. That is c1 remains the only clock. So I could route this one to an output pin. But I also need an inverted clock of c1 to route to an output pin. So the only possibility would be to invert c1. But could that be a problem ? I mean the inverted clock then would not directly come out of the PLL ... Rgds AndréArticle: 74562
Simon Peacock <nowhere@to.be.found> wrote: > that's as good as you can get.. unless you buy 1/2 a million > Or find 1/2 a million people to chip in. -- Wing Wong. Webpage: http://wing.ucc.asn.auArticle: 74563
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:416E1A9B.35BCC6F2@yahoo.com... > Jung Ko wrote: >> >> On Wed, 13 Oct 2004, Simon Peacock wrote: >> >> > A word of caution here: >> > >> > Altium or Protel as it was called is a PCB software company... Nextar >> > is >> > their FPGA development tools and both of these boards are designed to >> > use >> > Altium's software. As such support outside this simple parameter will >> > be >> > non existent. >> > >> >> Well... can't you just buy the devel. board and use the free Webpack or >> Quartus later ? (when the 30 day trial is finished). > > I belive there is a pretty good Spartan 3 dev board available for $99 > that Xilinx supports (XC3S200 vs. XC3S400). I don't know of any that > cheap from Altera. > Altera's evaluation board is $99 but it includes XC3S400 while the board from the Xilinx is XC3S200 (though, personally I think the cyclone version is better because the FPGA has more resources than XC3S400). You can the Altera's board with the free version of the development software from Xilinx or Altera so I think this is an interesting offer. Btw, Rickman, you asked me about a direct link for the technical docs of the Altera's boards. I found it and that is it: http://www.dxpcentral.com/LiveDesign/default.asp The shematics for the Cyclone and Spartan version are: http://www.dxpcentral.com/LiveDesign/LiveDesign_EB_Schematics-Altera_Cyclone.pdf http://www.dxpcentral.com/LiveDesign/LiveDesign_EB_Schematics-xilinx_spartan.pdf and the technical reference manual is: http://www.dxpcentral.com/LiveDesign/LiveDesign_Eval_Board_Tech_Ref_Manual.pdfArticle: 74564
> Altera's evaluation board is $99 but it includes XC3S400 while the board ooops I mean the offer from Altium not Altera!Article: 74565
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:416D6C60.9480E66E@yahoo.com... > I found the offer, but I can't find any info on what the board is... I > don't use Flash and I am not willing to download an exe file. Don't > they even have a data sheet??? > > As someone else pointed out, they are selling this board as a way to > evaluate their software. So I am not clear about what I can do with it > without buying their software. I also would like to know more about the > IO capabilities. I sort of doubt that a Flash presentation will give me > much technical info. There are some links to the board documentation here: http://www.altium.com/dxpcentral/LiveDesign/ Schematics are here, apologies if the links wrap around: http://www.altium.com/dxpcentral/LiveDesign/LiveDesign_EB_Schematics-Altera_Cyclone.pdf http://www.altium.com/dxpcentral/LiveDesign/LiveDesign_EB_Schematics-xilinx_spartan.pdf http://www.altium.com/dxpcentral/LiveDesign/LiveDesign_Eval_Board_Tech_Ref_Manual.pdf Ripping text from the tech reference manual, correcting error in xtal frequency. The LiveDesign Evaluation Boards have the following features: . On-board FPGA Device . Dual 256Kx16 BIT FPGA configurable High Speed Static RAM . Audio System, Delta Sigma stereo DAC with user-adjustable corner frequency . Dual (stereo) miniature speakers with volume control . Audio Line Out and Headphone 2.5mm jacks with volume control . 6 Digit 7-Segment LED display . Fixed 50MHz clock . RS232 Serial Port . VGA Port . PS2 Mini DIN Mouse Port . PS2 Mini DIN PC Keyboard Port . 8-way DIP switch . LED array, 8 LEDS . Dual 20 pin I/O expansion headers with power supply selection links . User-defined TEST/RESET button Cheers, Tim -- Tim Simpson return address mostly is invalidArticle: 74566
Hello All FPGA Gurus, I am new to using Chipscope Pro and Logic Analyzers in general and just started using them recently. Something which I would like to do is to collect 30 data samples each time the trigger occurs. That is, if I have the trigger occuring 10 times i want to collect 30 data samples after each occurence of the trigger and ignore the rest of the data between triggers. Is this possible in Chipscope Pro or am I missing something basic about the way these analyzers work ? Thanks in advance for any suggestion/advice. Cheers, AdarshArticle: 74567
Hello All, Another question for the Gurus. Besides the fact that each device is unique and has a "mind (or body or whatever !) of its own, what do you think could be other possible causes for the same bitstream behaving differently in different devices ? I have a board which has 9 Xilinx V2P7s and all of them are identical in function. I configure all of them with the same configuration file. But when i test them, some of them behave differently than the others.(5 are perfect and 3 have problems, for example). I use all 8 Rocket IOs on each of the 9 devices. My refclk is 80 MHz, userclk is 40 MHz and we are running at 800Mbps on our differential inputs. Our system clock is 40 MHz and so I would like to think that we are not really in the "high speed" domain. I don't see any timing violations. Am I just getting lucky with the 5 devices or unlucky with the 3 ? What are the chances of this being an external problem vis-a-vis and internal one ? We have been in a tough loop for a long time. The board also has, besides the Xilinxs, a couple of Stratix devices, a VME interface, Memories, Transcievers and a few other ICs. So the source of problems could be potentially a lot of things. Any similar experiences/suggestions/solutions ? Thanks in advance, AdarshArticle: 74568
rickman wrote: > John Williams wrote: > >>Adam Megacz wrote: >> >>>Question for Xilinx: with JBits now DOA, how are customers supposed to >>>use the ICAPs? Are they now strictly intended for "swapping" a set of >>>prebuilt configurations? Without something like JBits you can't >>>really do runtime template assembly AFAICT... >> >>Your question has a false premise - customers *aren't* supposed to use >>ICAP. :-S ... OK so I'm joking, but only just... >> >>ICAP is there because it helps Xilinx test chips. They make it visible >>in the tools etc because it has some interesting research opportunities. >> >>It's a bit of a chicken and egg problem - if someone can demonstrate a >>killer-app for ICAP and partial-reconfig, then support will follow. But >>without support, developing the killer-app is very difficult... > > Xilinx had a lot of new tool features they were supporting such as > modular configuration. I was told that they were commited to supporting > the Spartan 3 devices. But that support never materialized and I dont' > see where the new V4 chips are supported yet. Maybe they just don't see > much need and are dropping some of these advanced tools on the newer > chips. I think the problem is probably in the underlying wire database (NCD) that the current-gen tools use. Using constraints for modular/partial flow is not ideal. Better would be to have a database that has the equivalent of the SQL "view" construct - create a virtual device that is some spatial subset of the full device, with full P&R capability over that subset. Of course I'm not saying it's easy! > Or maybe it is the lack of tri-state buffers. I know the > Spartan 3 chips have none, do the Virtex 4 chips have any internal > tri-states? I'm speculating again, but I think the whole tri-state/bus macro thing is a bit of a red-herring - it's just the easiest, guaranteed safe way to do it with the existing tools and tech. Think about it, on-chip bidirectional buses are all done with wired-OR these days, yet functionally it acts like a tri-stated bus. Perhaps the same could be done with partial reconfiguration, it's just too hard to force the tools to obey such a construct. The bus-macros are so inefficient - one of my students looked into making a 32-bit bus macro, it would take more than the height of a V2-1000 device! To do real work with dynamic modules etc you need wide buses - bus macros just aren't gonna cut it. Anyway that's enough speculation for tonight :) JohnArticle: 74569
I am trying to simulate a Xilinx design with Rocket IO smartmodel. I use the Modelsim from within the ISE Project Navigator. I can perform a functional simulation ok but when I try to do a Post Place and Route Simulation, Modelsim crashes. I can see all the libraries loading properly : the Swiftpli.dll and the simprims etc.... but after it loads the glbl.v file, it crashes (or at least, that is the last thing i can observe before the Modelsim Window vanishes) I have modified the modelsim.ini file as suggested on the Xilinx Answer Database, have compiled all the libraries as recommended. Any ideas about the possible causes for such a crash ? Thanks, AdarshArticle: 74570
Vivek <> wrote in message news:<ee896ac.-1@webx.sUN8CHnE>... > What is the difference between GLKP and the GLKS? > > I am trying to figure out if i have enough global clock resources for the > clocks. Right now I have about 7 clocks coming into the GLKP pins. When i > instantiate a bufg, does it matter if its a bufg for GLKS or GLKP? Is there > something to take into consideration between P or S or can i act like all > of these are global buffers giving me 16 buffers in total? > > Any help would be appreciatd thanks. Howdy Vivek, You mentioned in another email that you are using a Virtex-II. Assuming you only need the 8 clocks or less in that device, I would suggest using either only GLKP's or only GLKS's (it doesn't matter which - they are functionally identical). By using only one or the other type, you avoid any issues with getting all 8 clocks into any and all quadrants of the device. The following link points to where more detailed info can be had on the GLK limitations: http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=11112 See the "facing GBUF" rule, shown in figure 3-7 of the user guide. Have fun, MarcArticle: 74571
if i am not wrong if the "window" mode for the trigger is chosen, the user defined amount of samples after a trigger event are stored in the buffer until it is full. hope this helps, andrea "Adarsh Kumar Jain" <adarsh.jain@cern.ch> wrote in message news:cklh5f$7ej$1@sunnews.cern.ch... > Hello All FPGA Gurus, > I am new to using Chipscope Pro and Logic Analyzers in general and just > started using them recently. > Something which I would like to do is to collect 30 data samples each time > the trigger occurs. > That is, if I have the trigger occuring 10 times i want to collect 30 data > samples after each occurence of the trigger and ignore the rest of the data > between triggers. > Is this possible in Chipscope Pro or am I missing something basic about the > way these analyzers work ? > Thanks in advance for any suggestion/advice. > Cheers, > Adarsh > >Article: 74572
Adarsh Kumar Jain wrote:
> I have a board which has 9 Xilinx V2P7s and all of them are identical in
> function. I configure all of them with the same configuration file. But when
> i test them, some of them behave differently than the others.(5 are perfect
> and 3 have problems, for example).
Sounds like a logic race.
Something is not synchronized properly
to the system clock.
> I use all 8 Rocket IOs on each of the 9 devices. My refclk is 80 MHz,
> userclk is 40 MHz and we are running at 800Mbps on our differential inputs.
> Our system clock is 40 MHz and so I would like to think that we are not
> really in the "high speed" domain. I don't see any timing violations.
Synchronization problems rarely show up in simulation
or timing analysis.
> Am I just getting lucky with the 5 devices or unlucky with the 3 ?
I expect that the 5 devices will eventually exhibit similar problems
over time and temperature. You are lucky that you discovered
the problem on the bench.
-- Mike Treseler
Article: 74573Hi Andre, > The problem is that c0 is a clock with a different frequency used for internal > operations. That is c1 remains the only clock. So I could route this one > to an output pin. But I also need an inverted clock of c1 to route to an output > pin. So the only possibility would be to invert c1. But could that be > a problem ? I mean the inverted clock then would not directly come out > of the PLL ... If you do not make use of the differential output standard to generate the clock and !clock signals, nor use the PLL to do so, then you will have some delay of one clock relative to the other unless you are really careful. You could, for example, take your c1 clock and feed it to two parallel logic elements, which then take identical routes to two I/Os. One logic element does nothing (implements a wire function :-)), the other implements an invert function. If you place this LAB adjacent to the horizontal I/O that you want to bring the two signals out of, then you should get pretty similar, short routes from the LEs to the I/Os. Do you need a known phase relationship between the internal clock and the external clocks? Paul Leventis Altera Corp.Article: 74574
Hi, Does anyone know the frequency of the internal oscillator of Xilinx VirtexE FPGAs which is used to generate the CCLK for Master-Serial configuration mode? I'm aware that the datasheet specifies 4 MHz as default CCLK frequency but that isn't necessarily identical to the frequency of the oscillator. What's the behavior of this oscillator after configuration? Is it turned off or can it be disabled through some option in the bit file? Regards Stefan Tillich
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