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Peter published this! ;-) http://www.xilinx.com/xcell/xl24/xl24_20.pdf Just cascade two! Cheers, Syms. <Jonathan> wrote in message news:ee896bd.1@webx.sUN8CHnE... > Yes, I have seen this. THe problem is im trying to select between three clocks. I am using a virtex II. I have 8 GLKP, and I am already using 7 of those global clock pins, leaving me only one left for the output of my three input mux. Is there such an item they have that has a three input bufgmux, or what would be a better solution to this?Article: 74451
On 11 Oct 2004 07:45:20 -0700, tony.p.lee@gmail.com (T Lee) wrote: >I don't work for Atmel. I am interested in knowing how they did it. >(I am using Xilinx at this time - a few very expensive one.) > >Since it is from a fpga company, I wonder if it use one of those >FPGA 2 ASIC conversion process to get such low cost price pointer >for such complex chip. Atmel does have FPGA products, but that is hardly their main product line. They have extensive memory products, processors, and application specific chips. http://www.atmel.com/products/product_selector.asp They have also been a significant custom/ASIC vendor and foundry. What you are looking at almost certainly did not go through a simple FPGA-2-ASIC process, given the on-chip CPU is an ARM. It may have been prototyped in FPGAs (as many ASICs are these days), but not with their FPGAs (too small). Either Xilinx or Altera would be more likely candidates. On the other hand, the chip is mostly many existing IP blocks, so if their development flow is reliable enough, and their simulation/verification supports stitching many IP blocks together, it may not have been prototyped at all. The low price point is because they expect to sell it in high volume, and it does not have any of the silicon overheads of an FPGA. Just like any other custom SOC. >I wonder if has anyone done similar complex SOC chip with >xilinx/altera? Sure. In big, expensive FPGAs, with the ARM as an additional chip. >-Tony Philip Philip Freidin FliptronicsArticle: 74452
As I mentioned before, the issue is the asynchronous relationship between the two Select lines and the three clocks. If you want to switch asynchronously, this gets complicated, although not impossible. It would help to know more details like: frequencies, are all three always running (i.e. do you ever switch to or from a stuck clock?)?. Peter Alfke > From: Jonathan <> > Organization: (none) > Newsgroups: comp.arch.fpga > Date: Mon, 11 Oct 2004 14:51:51 -0700 > Subject: Re: multiplexing clocks > > Yes, I have seen this. THe problem is im trying to select between three > clocks. I am using a virtex II. I have 8 GLKP, and I am already using 7 of > those global clock pins, leaving me only one left for the output of my three > input mux. Is there such an item they have that has a three input bufgmux, or > what would be a better solution to this?Article: 74453
On Mon, 11 Oct 2004 08:06:28 -0700, Vivek <> wrote: >What is the difference between GLKP and the GLKS? > >I am trying to figure out if i have enough global clock resources for the clocks. >Right now I have about 7 clocks coming into the GLKP pins. When i instantiate a >bufg, does it matter if its a bufg for GLKS or GLKP? Is there something to take >into consideration between P or S or can i act like all of these are global >buffers giving me 16 buffers in total? > >Any help would be appreciatd thanks. Were you planning to tell us what chip you are using? Philip Freidin FliptronicsArticle: 74454
I was addressing todat's situation in all FPGAs, since none has Vcc control. In the future one can think of many selective power-down solutions, but they have their own little problems and trade-offs. I just answered an applications question. Peter Alfke > From: Jim Granville <no.spam@designtools.co.nz> > Organization: TelstraClear > Newsgroups: comp.arch.fpga > Date: Tue, 12 Oct 2004 10:03:22 +1300 > Subject: Re: Temperature considerations of inactive logic blocks > > Peter Alfke wrote: > >> You cannot reduce leakage current by changing the bitstream. >> Peter Alfke > > You mean Static leakage, in current Xilinx FPGAs ? > > It is not a bad idea, to have as well as Clock Enables and > clock distribution management, a similar thing with > Core Power ? > Other fields do this already to mitigate the > power hits of the finer processes, and it would cost a little > die area. It would not surprise me to see this on future parts. > > Then, the P&R software could have two more targets : > Minimum Clocked Power, and minimum Static Power :) > >> >> >>> From: "bh" <spam_not@nosuch.com> >>> Organization: Optimum Online >>> Newsgroups: comp.arch.fpga >>> Date: Sun, 10 Oct 2004 21:01:31 GMT >>> Subject: Temperature considerations of inactive logic blocks >>> >>> I was curious if there is much difference in leakage current >>> or other heat-effecting conditions between FPGA logic blocks >>> that are programmed and those that are idle. >>> >>> Presumably, logic that is switching is generating heat. >>> However, is there an optimal programming state for >>> inactive gates in order to reduce heat? >>> >>> In particular, if I have 8 ARINC-429 channels in my >>> FPGA, but the current configuration of the system only >>> uses 2 of them, would it be beneficial (from a heat point >>> of view) to have a different bitstream that only has >>> 2 ARINC-429 channels? > > To answer this specific question, you should create two > valid designs, and measure them. Depending on where the > inactive channel CLOCKs are gated, (and even the physical placements) > you could expect to find a power saving. > > -jg > > >Article: 74455
hello there, i m a newbie to this fpga world. can i ask - what is meant bt timing closure? does it anyway relate to meeting the timing requirements? or something else? i know, it's a stupid question, but one should never underestimate the human stupidity ! ;-) TIA $hrey$Article: 74456
first public version of the simulator is available for downloads http://uclinux.openchip.org There are still known bugs and many planned features are not yet implemented but current version is already able to execute pre-built uClinux demo images from John Williams website :) Implemented is minimal mbvanilla platform support including INTC, UART, Timer, GPIO. SystemACE read only support has also been tested (can mount /dev/xsysace as disk) Please note that the Simulator is an W2K/XP Application! It comes with minimal installer and uninstaller, the kernel loader and kernel images are included all ready to be tested! Comments and bugreports are welcome! Any many thanks to the project sponsors of course :) As a sidenote, has anyone noticed that OpenCores OR1K instruction set is VERY VERY similar to Microblaze? Was a surprise to me :) Well I guess many generic 32 bit RISC instruction sets are have similarities. AnttiArticle: 74457
"Varnavi" <sh_a_12@yahoo.com> wrote in message news:a17d05bc.0410110754.713898b0@posting.google.com... > Hi > > I am a graduate student and would like to implement the SATA I Host > Controller Link and Transport layers in an FPGA for my Project. I am > just starting on the RTL coding but would like to plan ahead for the > verification of my RTL design. Can anyone guide me towards how I could > write a testbench to verify my design and how doable is it. Are there > any freely available Simulation testbenches for SATA I in which I can > plug in my RTL code for verification. Let me know if there is a more > apprpriate forum to address this question. Thanks. > > Varnavi 1) there is virtually nothing free for SATA are you doing it only as theoretical testbench or do you plan to verify it in real FPGA design? There are NO SATA PHY IC's that can be purchased without major headache. And at least V2Pro/V4 RocketIO is not directly fully compliant with SATA physical layer, so in case of FPGA verification what do you plan to use? AnttiArticle: 74458
"General Schvantzkoph" <schvantzkoph@yahoo.com> wrote in message news:pan.2004.10.11.17.39.38.85117@yahoo.com... > On Mon, 11 Oct 2004 19:35:37 -0700, Antti Lukats wrote: > > > "Varnavi" <sh_a_12@yahoo.com> wrote in message > > news:a17d05bc.0410110754.713898b0@posting.google.com... > >> Hi > >> > >> I am a graduate student and would like to implement the SATA I Host > >> Controller Link and Transport layers in an FPGA for my Project. I am > >> just starting on the RTL coding but would like to plan ahead for the > >> verification of my RTL design. Can anyone guide me towards how I could > >> write a testbench to verify my design and how doable is it. Are there > >> any freely available Simulation testbenches for SATA I in which I can > >> plug in my RTL code for verification. Let me know if there is a more > >> apprpriate forum to address this question. Thanks. > >> > >> Varnavi > > > > 1) there is virtually nothing free for SATA > > > > are you doing it only as theoretical testbench or do you plan to verify it > > in real FPGA design? > > > > There are NO SATA PHY IC's that can be purchased without major headache. > > > > And at least V2Pro/V4 RocketIO is not directly fully compliant with SATA > > physical layer, so in case of FPGA verification what do you plan to use? > > > > Antti > > Are the SerDes in SATA significantly different from PCI Express and > InfiniBand?, both of which work fine with RocketIO. SATA is a lower clock > rate than PCI Express and InfiniBand but I would have thought the logic > levels would have been the same. RocketIO can not do PCIe or SATA fully compliant to the specs without special external "tweaking" IC's and have possible problems even with such circuitry being used. Problems are the initial CDR lock range and "Electrical Idle" Vdiff voltage. Workarounds are for Serial ATA OOB transmit idle 1) series resistors and FET shunt Xilinx solutions 2) can be done with no circuitry by using POWERDOWN and 2 MGTs per channel (my solution verified in FPGA) Workaround for CDR lock 1) SATA - not known ! 2) PCIe - external high quality low jitter multiply by 1.25 PLL Those workarounds are REQUIRED for compliance! I think RocketIO has also problems with PCIe TxElecIdle and recovery time, but I have not tested that with real silicon and no-one has so far confirmed this problem (except that I think it is a problem) PCIe requires TxElecIdle Vdiff to be less than 20mV and recovery to normal operation less than 20UI, thats not doable with rocketIO ASFAIK (not without similar to the SATA OOB Transmit workaround) I dont know about the Infiniband. It wonders me that you that rocketIO works fine with SATA and PCIe - it does not at least not without the tricks. Sure as per SERDES there are no problems getting SATA packets received with rocketio isnt that big problem, but getting the system compliant to the spec is. Antti PS I would be glad if I would be wrong with the statements here!Article: 74459
SG wrote: > Austin Lesea writes: > >> Just remember that the PPC, MGT, DCM, EMAC, DSP48, etc. are all 'hard >> cores' and do not 'suffer' from the same 10:1 disadvantages in speed >> and power as plain old interconnect and logic. > > Only if you use them. Otherwise, they contribute even more to the > area disadvantage of FPGAs over ASICs. *Usually*, there will always > be some of hard blocks in a FPGA that you will not use for your > application (the FPGA device having been chosen for cost, fitting > your design, etc reasons). They only "contribute ... to the area disadvantage" if your target is a simple cost function - if you are minimising cost. Just as likely you are putting some weight on minimising risk. And a startup may be working on maximising the minimum profit or minimising the maximum calamity. If so, unused resources are the general's reserve troops.Article: 74460
On Tue, 12 Oct 2004 06:20:57 +0530, Shreyas Kulkarni <shyan@gmail.com> wrote: >hello there, > >i m a newbie to this fpga world. can i ask - >what is meant by timing closure? Sure you can ask. >does it anyway relate to meeting the timing requirements? >or something else? You are correct. When you do your design, you should know the clock frequency (or frequencies) that your design needs to operate at, as well as the requirements at the I/O pins, such as setup and hold times with regard to other I/O pins, and usually clock pins. Together, these timing requirements are referred to as "timing constraints" by the FPGA implementation software. So you pass your logical design plus these constraints to the implementation software, and the end result is hopefully a placed and routed design, plus a timing report. If all went well, the timing report tells you that all your constraints have been met. This would be "closure". Providing that your design is logically correct, and you have timing closure, you are ready to try out your design in an FPGA. If you don't have timing closure, there is little point in running your design, since although it still may work (because the device you are using might be better than average, or it is a cold day, or a full moon), you could not predict whether the design would run in the next chip you try. If you dont have timing closure, there are several hings you can do: 1) Run the implementation tools again. Some tools have some randomness in their operation, and you might be lucky. 2) Figure out what paths did not meet timing constraints, and change your design to make these paths take less time. I.e. less logic, more pipeline stages 3) Change to a faster FPGA 4) Change you clock rate, and the constraints Note that timing closure does not guarantee that your design will work. I have seen many designs where the constraints did not cover all paths in the design. The implementation tools are notorious for reporting that your design meets timing, but fails to tell you that only 30% of your paths had timing constraints. The rest of the paths MUST have some timing requirement, but you forgot to include it in the constraints list. >i know, it's a stupid question, but one should never underestimate >the human stupidity ! ;-) There are no stupid questions, only stupid answers. >TIA >$hrey$ Philip =================== Philip Freidin philip.freidin@fpga-faq.com Host for WWW.FPGA-FAQ.COMArticle: 74461
Hi all, Given a clock of 20Mhz can I generate 320Mhz clock output using single DCM in Xilinx FPGA? Regards Raghavendra.Sortur.Article: 74462
Hi 1. Asynchronus solution The best solution for clock switch is use clock manager logic. Try made clock manager operate with high clock generate by DCM or DLL.The second step is place this component to Virtex (for example constrains.ucf Virtex chips) .The fast step use parameters for phase relation beetwen output clock. I used this method in 24 clock operate system. It works very stable. 2. Synchronus Switch clock in mux. Try use place too. But if you have more clock better use asynchromus clock manager and set phase relation and placeing. Best regards Wojciech Zebrowski Uzytkownik <Jonathan> napisal w wiadomosci news:ee896bd.-1@webx.sUN8CHnE... > Hi, > > I have three clocks connected to input/output pins (not global clock buffers), and then inside the fpga i have a 3 input multiplexer to select between the three clock signals. I then route the output of the three input multiplexer to a bufg component. I was wondering if this is a valid way to globally route the clock, or if someone has a better idea. ANy help would be appreciated greatly > > THank you, > > JonathanArticle: 74463
Symon a écrit: > "Nicolas Matringe" <nicolasmatringe001@numeri-cable.fr> wrote in message > news:416AA011.5050205@numeri-cable.fr... > >>- D0 toggles between 1,5 & 3V ! > Well, that's what's wrong. Thought so too... I don't think it's an accidental short because the problem exists on the 2 boards we have. I'll check the design... Anyone got any idea why the output doesn't go down to 0V? -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 74464
Some additional thing: "Differential" is the wrong expression. I need inverted clocks on a 3,3V logic level. But in my opinion there is no 180° phase allignment given when inverting one of the clocks, isn't there? Does QuartusII provide some module to make this phase allignment? Thank you. Rgds AndréArticle: 74465
Hi Andre, > I have decided to post this problem again because it has gone down > in my last post, so here it is; > > How do I route the output of the PLL (Altera Cyclone) to the PLL_OUT+ > and PLL_OUT- pins for differential clock use? > I mean the PLL has only one output ... Do I have to create an inverted > clock - only by an inverter ? Just set the I/O type of the clock signal to be LVDS or another differential spec. It'll become differential automagically. With the appropriate electrical specs, of course. Best regards, BenArticle: 74466
OK, there is a mistake in the schematics, I connected the output of the XCF02S to the Dout of the FPGA instead of the Din (luckily I can strap it) End of the story -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 74467
This may sound trivial but why is data being output (read) on the out
port during the write cycle in the Xilinx inferred RAM examples such
as:
if (CLK'event and CLK = '1') then
if (en = '1') then
if (we = '1') then
ram(conv_integer(unsigned(addr))) <= di;
do <= di;
else
do <= ram(conv_integer(unsigned(addr)));
end if;
end if;
end if;
Thanks,
YZ
Article: 74468
because if there is a writing access (we = '1') then the input data (di) is
registered both in the corresponding memory location and in the output port
(do), according to the following lines:
if (we = '1') then
ram(conv_integer(unsigned(addr))) <= di;
do <= di;
else
do <= ram(conv_integer(unsigned(addr)));
end if;
hope this helps,
andrea
"Yaseen Zaidi" <yaseenzaidi@NETZERO.com> wrote in message
news:a31921fc.0410120224.23a6ab0a@posting.google.com...
> This may sound trivial but why is data being output (read) on the out
> port during the write cycle in the Xilinx inferred RAM examples such
> as:
>
> if (CLK'event and CLK = '1') then
> if (en = '1') then
> if (we = '1') then
> ram(conv_integer(unsigned(addr))) <= di;
> do <= di;
> else
> do <= ram(conv_integer(unsigned(addr)));
> end if;
> end if;
> end if;
>
>
> Thanks,
>
> YZ
Article: 74469tatto0_2000@yahoo.com (Wong) wrote in message news:<509bfe22.0410110029.3a3cccc0@posting.google.com>... > Hi, > I am a Actel 54SXA family user. I would like to get from the > fusefile what I/O standard I have selected in my Designer software > (i.e. PCI, LVTTL). Is that possible ? I am doing so because I have > been messed up my files and I cant trace back. > Thanks in advance. Any answer ? Please .....Article: 74470
Wong <tatto0_2000@yahoo.com> wrote: : tatto0_2000@yahoo.com (Wong) wrote in message news:<509bfe22.0410110029.3a3cccc0@posting.google.com>... : > Hi, : > I am a Actel 54SXA family user. I would like to get from the : > fusefile what I/O standard I have selected in my Designer software : > (i.e. PCI, LVTTL). Is that possible ? I am doing so because I have : > been messed up my files and I cant trace back. : > Thanks in advance. : Any answer ? Please ..... Search the net for FPGA reverse engineering. I think after that you will give up... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 74471
Hi, Modular Design does not support the use of non-rectangular area group ranges, http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=16423 Miguel SilvaArticle: 74472
Thank's for you help Ray, Now I think I get it!! Please tell me if I'm wrong!!! For example: In my case where I have 16+guardbits in my Cordic(input) the 360 degrees are divided in 2^(16+guardbits),that means that just when the MSW(16 bits) from phase accumulator changes, a new output will come from Cordic on each phase accum. step. But when the phase accumulator LSW changes, Cordics output will not change in every phase acc. step! look figure in http://www.nova-eng.com/downloads/ip_nco_crdc.pdf It will be "ideal" to have always in each acc. step a new output. That will give a better input to the DAC. To achieve this task we will need 2^32 phase acc. steps(common!) and a angle resolution of 2^32. But because a DAC with 32 bits are just dreams!! the angle resolution has to be truncated. Is it right??? Carlos Murillo Ray Andraka <ray@andraka.com> wrote in message news:<416A8F3A.B3FFF57@andraka.com>... > There is a difference between phase resolution and frequency > resolution. Typically, you'll have a phase accumulator that adds some > fixed increment to itself every clock cycle. The increment value sets > the frequency, which is the frequency of the accumulator wrap-arounds. > The frequency is Fo = Fc*N/(2^k) where Fc is the clock frequency, N is > the increment value (integer) and k is the number of bits in the phase > accumulator. The more bits in the accumulator, the finer the resolution > to which you can set the frequency. The CORDIC width does not affect > the frequency at all, rather it will affect the noise added by the > CORDIC. You have several factors here: number of iterations, width of > I and Q paths and width of phase path. > > First, look at the number of iterations. If we assume for the moment > that there is infinite precision in the I and Q data paths as well as in > the phase accumulator path, then each iteration performs a perfect > rotation with no error, but the angle of rotation is fixed at the > elemental angle for that iteration. If you limit the number of > iterations, you limit the total number of possible rotation > angles...that is limiting the number of iterations introduces a phase > error in the rotated output. There is no amplitude error due to > limiting the number of iterations. > > Next, lets consider limited precision in the phase accumulators. Again, > we'll assume infinite precision in the I and Q paths. If the phase > accumulator width is limited, we introduce a truncation/rounding error > in the phase for each iteration accomplished. Again, the error is only > in phase angle, not in amplitude. > > In both the above cases, the phase error is not cumulative from sample > to sample, so it manifests itself as phase noise. Note this has no > effect on the average frequency, and that there is no amplitude noise. > > Finally, in the case of limited precision I and Q, the rotations are no > longer perfect, as there is a rounding or truncation error on sum at > each iteration. The result is the rotated vector is forced to fall on a > retangular grid, which introduces both angular and magnitude errors. > Again, there is no effect on the average phase or amplitude, but the > instantaneous values will have some error bounded by the resolution of > the IQ grid defined by the I and Q resolution. The extra LSBs, which > you are calling guard bits are there to make the I and Q truncation > error smaller with respect to the signal, and therefore reduce this > noise source. > > I hope this helps explain it. > > Carlos Murillo wrote: > > > Hello everybody!! > > > > Maybe some CORDIC guru's can help me??? > > > > I've seen a lot of papers, designs and cores and I still don't > > understand > > why always everybody offers (for example) a Frequency Resolution of > > 32bit when at the input of CORDIC's block the angle just have > > 16bits+guard bits(log2(16)) = 20 bits. That's not a 32 bits > > resolution!!!! The phase offset is 16 bits, That's OK but 32 bits > > frequency resolution!!!! I think maybe it's all about the guard bits > > but I'm not sure!!! Can some one please Help me to understand it!!!! > > Thank's for your time!!! > > > > Carlos Murillo > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 74473
Hi Friends, In my board i have SRAM, Spartan-3 FPGA ,CPLD Xc95144xl and PC104 Connector (ISA bus header). I want to pass the data stored in SRAM to PC104 . in between that with the help of spartan-3 only data stored in SRAM. ____ ______ ______ _______ |pc | | | | | | | |104 | <----> | CPLD | <----> |SP-3 | <---> | SRAM | |____| |______| |______| |_______| This is connection between those components. between the sp-3 and sram i passed 16 bit data line and address pin from sp-3 and some control pins. Now i want to know how many pin shud be connected between cpld and sp-3. so that data pass from sram to pc104. Kindy give me some suggestions. Regards Senthil Chett.Article: 74474
Hi, Is there method that is more efficient than regular division for calculating modulus ? Thanks in advance. Mete
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