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"rickman" <spamgoeshere4@yahoo.com> wrote in message news:41717A2A.B5719B0B@yahoo.com... > John Williams wrote: > > I don't want to beat a dead horse, but it is not very common to goof up > making a PDF file. The Acrobat software installs a printer driver that > is used just like a printer, but it produces a PDF file; WYSIWYG. I use > this very often and I never have any issues with it. I have never seen > it add lines, remove lines or turn text around. > > These mistakes were either due to someone printing out an old version of > the drawings or possibly the Altium software not printing correctly. > Full agreement here.Article: 74701
One final note. I was looking up some conversions in numeric_std and
discovered that I *was* using both conversion and casts in my code.
What I thought was a "cast" is actually a "qualified expression". From
a conversion package.
-- std_logic_vector, signed and unsigned types are "closely related"
-- no type conversion functions are needed, use type casting or
qualified
-- expressions
--
-- type1(object of type2) <type casting>
-- type1'(expression of type2) <qualified expression>
So a type cast will look very much like a conversion, but can only be
done between closely related types. The qualified expression is what I
had some trouble using. I think I don't fully understand the rules for
using them, but I beive it is similar where an expression can be
interpreted as more than one type, e.g. "010110" can be a bit vector or
an slv.
newman wrote:
>
> Rickman,
> Just for my own edification, why do you prefer to convert rather
> than cast.
> Do you consider it bad style, not portable, personnel preference? I
> recently transitioned to using numeric_std, and it appeared to me that
> casting looked more readable when going from std_logic_vector to
> unsigned and then back to std_logic_vector. It simulated and
> synthesized without problems, although I have to admit that I did not
> look at the gate level netlist. Do you think I am missing something?
>
> Thanks,
> Newman
>
> "kofeyok" <lomtik@gmail.com> wrote in message news:<8742cebfcf499980dba16f72a2982be3@localhost.talkaboutelectronicequipment.com>...
> > Thanks for the reply rickman.
> >
> > That makes sence now.
> > I see that passing of values between modules is done using slv.. but you
> > can can convert (not cast) inside of each module. The signed port gives
> > non-synthesizable code. At least my simulator refuses to simulate.
> >
> > Thanks
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 74702
Adam Megacz wrote:
> What was the first FPGA?
Maybe the xc2064 in 1986.
-- Mike Tresler
________________________________________________________________
From: 13-MAR-1986 14:39:46.57
To: @sys$mail:engineer
CC:
Subj: SOFT GATE ARRAY
For anyone interested in the XILINX XC-2064 LOGIC CELL ARRAY read
on.
This is a 1000-1500 gate Gate Array that is configured by
downloading a bit stream to it from rom at power up time. The
configuration 'links' are maintained in CMOS static ram cells in
the IC.
I have a spare copy of the data sheet plus some other information
obtained at the XILINX - HAMILTON/AVNET Seminar.
Some general information :
. 12000 bits are required for configuration
using a 1Mhz clock requires 12 milliseconds to load.
. There are 122 flop flops per IC distributed in 58 I/O blocks and
64 combinational blocks.
. Package size is 68 pin PLCC, 48 pin (40 i/o pins) DIP package
available soon.
. Development software runs on IBM PC XT/AT or compatible, with
hard disk.
. Full speed in circuit emulator is available.
(you can set a hardware breakpoint with this device)
PRICING AND AVAILABILITY.
Development software:
Evaluation Kit $ 250.00
XACT Development system software, including Macro library $3,600.00
SILOS Timing/simulation package $3,500.00
XACTOR in circuit emulator with one pod $3,000.00
(can accomodate 4 pods for simulation of 4 devices at once)
XACTOR pods $ 850.00
XACT training/demo package $ 350.00
Piece parts :
Speed package 1-24 25-99 100-999 5K+ (end '86)
-1 68 lead plcc $60 $53 $47 $20
-2 68 lead plcc $80 $72 $63 $28
-1 (20Mhz) available now, -2 (33Mhz) available end 2nd quarter.
48 pin package "soon"
Article: 74703Yeah. I am gathering that. And it is also difficult to understand where VHDL testbenches "begins" and the other takes over. There is also a waveformer in the Xilinx tool that is somewhat intuitive. I have found some text books that cover simulation testbenches and give a few examples. Very week though in terms of the numbers of examples and the strategy behind the use of the various commands. I still haven't found an example of a bidirectional test bench. I also started searching the web with the words downto and testbench and have found some examples, but these are not what I would call good tutorials. "Simon Peacock" <nowhere@to.be.found> wrote in message news:4171044a@news.actrix.gen.nz... > modelsim isn't really that difficult to use... its the VHDL or verilog > testbench that's the bugger. > > Simon >Article: 74704
> It comes with quite a good introductory tutorial. The 58 page one?Article: 74705
Brad Smallridge wrote:
> Yeah. I am gathering that. And it is also difficult to understand where VHDL
> testbenches "begins" and the other takes over.
The design entity becomes an instance in the testbench architecture.
> I have found some text books
> that cover simulation testbenches and give a few examples. Very week though
> in terms of the numbers of examples and the strategy behind the use of the
> various commands.
The basic strategy is to wiggle the inputs and watch
for expected values on the outputs.
> I still haven't found an example of a bidirectional test bench.
here's one:
http://groups.google.com/groups?q=oe_demo+bidirectional+yang
Good luck.
-- Mike Treseler
Article: 74706> Netlists, Documentation and Development tools can be downloaded from > http://www.niktech.com. 1) are you going to release the HDL sources? 2) are you planning to port uClinux for MANIK? AnttiArticle: 74707
Thank you guys for suggestions. They are very helpful. I decided to complete my design with two pieces of XC95144XL (I have some), and take a look of XCR3000XL and EPM570 once the design works. vax, 9000 wrote: > I am pretty new to the Xilinx world and I am seeking the answers to my > questions here. The requirements are listed here, > 1. 3.3V or 5V parts (compatible with TTL/HTCmos) > 2. no smaller than XC95288 > 3. supported by free webpack > 4. easy to deal with (PLCC or TQ or PQFP or PGA, no BGA) > 5. more than 80 I/O pins > 6. can buy in small quantities (3, for example). > 7. low cost > > XC95288/XC95288XL fit 1,2,3,4,5,6 but I think there might exist cheaper > parts. Less than $10 will be considered good enough. Thanks. > > BTW, is it easy to move a CPLD design (VHDL) to FPGA? It has mostly adders > (5 MHz or lower) and state machines (20MHz). Thanks. If so, would you also > let me know what FPGA family to look at, with those requirements applied? > > vax, 9000Article: 74708
Brad Smallridge wrote: > > Yeah. I am gathering that. And it is also difficult to understand where VHDL > testbenches "begins" and the other takes over. There is also a waveformer > in the Xilinx tool that is somewhat intuitive. I have found some text books > that cover simulation testbenches and give a few examples. Very week though > in terms of the numbers of examples and the strategy behind the use of the > various commands. I still haven't found an example of a bidirectional test > bench. I also started searching the web with the words downto and testbench > and have found some examples, but these are not what I would call good > tutorials. Personally, I find a VHDL testbench much easier to write than generating a waveform type stimulus. In VHDL I can write procedures to control a bus interface reading data from a file or provide feedback from one external interface to another. In short, it is a lot like writing any other program since it does not need to be sythesizable. The *hard* part is knowing what you want it to do! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74709
I design a simple pci target, with only config read/write, NOT response to normal read/write operation, but I implemented the BAR0 ( base address register) (16M Bytes size), and I have implemented the command register. when I plug the card into pc and boot the windows up, I can see " find new device ...", but, the command register's content is "0000h" ( bus disabled) and the the value of BAR0 is "00000000h", why the windows doesnt allocate the memory space for my card? I have test the config read/write operation, all work, where is the problem? Must I implementation the normal read/write to make BAR0 get an address? Thanks!Article: 74710
Mike Treseler <mike_treseler@comcast.net> wrote in message news:<CMqdnQkoMae0GezcRVn-uA@comcast.com>... > Adam Megacz wrote: > > What was the first FPGA? > > Maybe the xc2064 in 1986. > > -- Mike Tresler There were devices in the 60ies that were very similar to FPGA. An array of switch configurable functions that could be locally routed by switches and globally routed by wire wrap. Such a thing is definitely field programmable and it is a gate array and it solves the same problem als todays fpgas. But I must admit that the package probably was larger and had less pins ;-) Kolja SulimmaArticle: 74711
Brad Smallridge wrote: > Yeah. I am gathering that. And it is also difficult to understand where VHDL > testbenches "begins" and the other takes over. There is also a waveformer > in the Xilinx tool that is somewhat intuitive. I have found some text books > that cover simulation testbenches and give a few examples. Very week though > in terms of the numbers of examples and the strategy behind the use of the > various commands. I still haven't found an example of a bidirectional test > bench. I also started searching the web with the words downto and testbench > and have found some examples, but these are not what I would call good > tutorials. IIRC the book "VHDL for Logic Synthesis" by Rushton has a good section on writing VHDL testbenches, talks about file IO and so on. My preferred approach, when possible/sensible, is to write fairly generic VHDL testbenches that read the stimulus and expected response data from text files, and then drives the unit-under-test from that data. This lets you use other tools to generate the input and output datasets. I've used this to verify implementations of image processing algorithms - prototype the algorithm in matlab, design the hardware, then drive both the matlab and VHDL models with the same input data files, comparing the results. Rgds, JohnArticle: 74712
bansal.dhanraj@gmail.com (BANSAL DHAN RAJ) wrote in message news:<a598557c.0410151208.7be2aa2d@posting.google.com>... > hi everybody > How can the FPGAs (particularly ALTERA) be used for high speed data > acquisition of the order of 10 MSPS(mega samples per second ).Which > one ADSP 21992 or FPGA is better? What is a CAN(CONTROone ADSP 21992 > or FPGA is better? What is a CAN(CONTROL AREA NETWORK)? pls reply soon > .thanks in advance There is a recent thread on DAQ at 1GHz in an FPGA. 152c7087.0409060135.30bfa875@posting.google.com I guess your DSP can not do that. 10MHz on a single channel is hardly high speed for either approach, you use whatever you like, it probably does not matter much. Well, if you want to do 100000 channels at 10MHz you better use FPGAs. Especially if you did it in 1994 like these guys: http://na49info.cern.ch/Public/detector/ CAN is a network standard use primarily in cars. (see the 2000+ google hits for "control area network") Kolja SulimmaArticle: 74713
Thank you all. This thread was very helpful... MeteArticle: 74714
>> > > This thread turns out into a contest to build the fastest JOP > version. >> > > Choose an FPGA vendor of your choice and optimize HDL and tool >> > > settings. >> > > Maybe Martin should donate one of his boards to the winner ;-) >> > >> > OK, that's a good idea! >> > Here's the contest in two categories: >> > The smallest JOP in LC/LE count. >> > The fastest JOP in turn of fmax. And the WINNER of the ACEX FPGA board is: Kolja! He changed the multiplier and suggested changes in the ALU (stack.vhd). These two changes with a little bit of optimization by myself resulted in a saving of 136 LCs (with default synthesizer options). The suggestion from Paul for the Quartus settings reduced the area by another 130 LCs or 184 LCs (minimize Area). However, Koljas VHDL changes reduce the area in the Cyclone and Spartan-3 version of JOP. To Paul: I hope you can accept this decision. And it makes more sense to send an ACEX board to a Xilinx user than to an Altera employee ;-) To Kolja: Please drop me a note with your address. The results of JOP on Cyclone and Spartan-3 (both fastest speed grade): Cyclone, opt. for speed: 1800 LCs, fmax: 100MHz Cyclone, opt. for area: 1746 LCs, fmax: 98MHz Spartan-3, opt. for speed: 1844 LCs, fmax: 83MHz Spartan-3, opt. for area: 1689 LCs, fmax: 74MHz If you need a very small JOP core you can implement the multiplier and the barrel shifter in software. Without the uart and the timer this results in 1077 LCs (at 98MHz) in the Cyclone. Martin PS.: The optimized versions of JOP are uploaded on the website. ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 74715
Hi, It's a question about simulation in ISE6.3. In ISE6 tutorial, it says user can translate a .tbw file into .vhd file and edit it manually. Can anybody tell me how to translate it back, from .vhd to .tbw file, it isn't mentioned in the ISE tutorial? If there are alternative approaches to do simulation after manual editing .vhd file, I would be appreciated to learn. -Thx, ZimmerArticle: 74716
Insert this command line in the xyz_vhd_tb.ndo file generated after pressing generate post translate model. compxlib -s mti_se -f all:s -l vhdl -o /home/saurabhc/check (last one is the path of directory having VHDL files) if this command is added then there is no need to add this line in post map file. for more info about this line write compxlib -help in the command prompt in ur modelsim tool. bye Saurabh yaseenzaidi@NETZERO.com (Yaseen Zaidi) wrote in message news:<a31921fc.0410130226.f1d4c03@posting.google.com>... > I generate a testbench and then do Simulate Post-Translate VHDL Model > in ISE 6.2.03i. Modelsim frowns as follow: > > # ** Error: (vcom-19) Failed to access library 'simprim' at "simprim". > # No such file or directory. (errno = ENOENT) > # ** Error: rcvr_translate.vhd(18): Library simprim not found. > # ** Error: rcvr_translate.vhd(19): Unknown identifier 'simprim'. > # ** Error: rcvr_translate.vhd(20): Unknown identifier 'simprim'. > # ** Error: rcvr_translate.vhd(22): VHDL Compiler exiting > # ** Error: C:/Modeltech_5.8d/win32/vcom failed. > > I have compiled both simprim and unisim libraries in $Xilinx > directory. The testbench includes the following headers: > > library SIMPRIM; > use SIMPRIM.VCOMPONENTS.ALL; > use SIMPRIM.VPACKAGE.ALL; > > I like to do post translate/map/PAR timing simulation if I could only > get pass this error. > > Thanks, > > YZArticle: 74717
If they dont respond here, email Xilinx one of those addresses under "contact" link, then (additinally) open a 'Webcase" (under tech support" links) for which you need to be registered. Registration takes 24 hours but do NOT specify yourself as a student, make it professional engineer otherwise they refuse to talk (as happened to me and I had to get answers from here... thanks to all you people). Finally call their tech support hotline, again need to be registered on their Web... Maybe Peter Ryser can answer you - look for him under "Question on Xilinx VirtexProII" I posted on this group, hi sresponse was MOST COMPLETE, so you may want to ask him YOUR question. My posting was dated by October 15 here.Article: 74718
do NOT email Peter Ryser, ask on this Newsgroup instead. He is already overloaded, if gets any mor eemails he won't respond ever and reduce ability to respond even to Newsgroup, so... ask on this Newsgroup and not email. MadmanArticle: 74719
Paul, thanks for your suggestion. However, I will stay at plain VHDL and wait for the synthesizer update :-) > First of all, I should point out that this is sub-optimal synthesis, NOT a > "bug" -- the design will function, it just uses more logic elements than > necessary. We *may* fix this in a future release of Quartus, but the I was never thinking that this is a 'bug' in the sense that it produces wrong results. > solution will not be easy to implement so don't hold your breath. The value > is rather limited due to the input limitations explained below, and the > relative rarity of this combination of functions. However, if the LAB global inputs such as 'sload' and 'ena' are not available for the synthesizer you're 'wasting' resources. Do you use these signals for other functions (perhaps the loadable counter)? BTW.: Do we really need asynchronous signals such as PRN/ALD, ADATA and CLRN (ok this one for the asynch. reset) in these days? Isn't that a waste of resources usfull only for a some designed who doing asynchronous design. > In the meantime, there is a work-around. You can directly instantiate > "stratix_lcells" (the WYSIWYG cell for Stratix/Cyclone LEs). Below I give Is there some documentation about these AYSIAYG lcells? I was looking for such an entity in the Megafunctions/LPM help of Quartus (befor you provided the solution) to implement this function. However, I did not find these basic megafunction. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 74720
"NoThisRAT" <nothisrat@yahoo.com> wrote in message news:ckt766$2gi4$1@mail.cn99.com... > I design a simple pci target, with only config read/write, NOT response to > normal read/write operation, but I implemented the BAR0 ( base address > register) (16M Bytes size), and I have implemented the command register. > when I plug the card into pc and boot the windows up, I can see " find new > device ...", but, the command register's content is "0000h" ( bus disabled) > and the the value of BAR0 is "00000000h", why the windows doesnt allocate > the memory space for my card? I have test the config read/write operation, > all work, where is the problem? Must I implementation the normal read/write > to make BAR0 get an address? > Thanks! > > Hi, I'm currently working on a PCI target. The BARx registers are assigned there values by the BIOS, not Windows. You might already know this, but the BARx registers are either for memory mapped space (mem read/write PCI commands) or i/o port space (i/o read/write PCI commands). The first bit of the BARx registers identifies which type of memory you want (e.g. you hardwire the first bit). First the BIOS tries to set the bits in the command register and if it can set bits 0 and 1 it will then try and set the relevant values in the BARx registers. If you're not supporting either of the I/O or memory read/write PCI commands, the BIOS will not bother writing values to the BARx registers. Does the BIOS try and perform an I/O or memory read/write command, just to check the device is working correctly? I don't know the exact answer to that, but I can't see why it would. I would advise implementing the read/write commands. You don't have to do anything with the data. All you need to do is assert FRAME and TRDY. Discard any data you receive and only ever send out 0xFFFFFFFF. Hope that helps,Article: 74721
Hi, It's a question about simulating CPLD in ISE6.3 Web Pack. In ISE6 WebPack tutorial, it says user can translate a .tbw file into .vhd file and edit it manually. Can anybody tell me how to translate it back, from .vhd to .tbw file? This isn't mentioned in the ISE tutorial If there are alternative approaches to do simulation after manual editing .vhd file, I would be appreciated to learn. -Thx, ZimmerArticle: 74722
Do you know any reference design for 10M sample/sec 12-16bit resolution ADC board with 4-16Ksample buffer? AND/OR A commercial board ADC board with above mentioned specs and with PC104+ PCI or PC104 ISA or USB interface ? > ... > 10MHz on a single channel is hardly high speed for either approach, > you use whatever you like, it probably does not matter much. > Well, if you want to do 100000 channels at 10MHz you better use FPGAs. > Especially if you did it in 1994 like these guys: > http://na49info.cern.ch/Public/detector/ > ... > > Kolja SulimmaArticle: 74723
Rickman, thanks for taking the time for the reply. sig_out_slv <= std_logic_vector(unsigned(sig_out_slv) + 1); -- unsigned '+' natural yields an unsigned value -- Ashenden's 2'nd edition Figure 8-11 -- Addition and subtraction of two vectors: the larger of the two operand -- lengths I enjoy reading your posts! Thanks again, Newman ------------------------------------------------------------------ rickman <spamgoeshere4@yahoo.com> wrote in message news:<41718078.DE6AB80F@yahoo.com>... > One final note. I was looking up some conversions in numeric_std and > discovered that I *was* using both conversion and casts in my code. > What I thought was a "cast" is actually a "qualified expression". From > a conversion package. > > -- std_logic_vector, signed and unsigned types are "closely related" > -- no type conversion functions are needed, use type casting or > qualified > -- expressions > -- > -- type1(object of type2) <type casting> > -- type1'(expression of type2) <qualified expression> > > So a type cast will look very much like a conversion, but can only be > done between closely related types. The qualified expression is what I > had some trouble using. I think I don't fully understand the rules for > using them, but I beive it is similar where an expression can be > interpreted as more than one type, e.g. "010110" can be a bit vector or > an slv. > > > newman wrote: > > > > Rickman, > > Just for my own edification, why do you prefer to convert rather > > than cast. > > Do you consider it bad style, not portable, personnel preference? I > > recently transitioned to using numeric_std, and it appeared to me that > > casting looked more readable when going from std_logic_vector to > > unsigned and then back to std_logic_vector. It simulated and > > synthesized without problems, although I have to admit that I did not > > look at the gate level netlist. Do you think I am missing something? > > > > Thanks, > > Newman > > > > "kofeyok" <lomtik@gmail.com> wrote in message news:<8742cebfcf499980dba16f72a2982be3@localhost.talkaboutelectronicequipment.com>... > > > Thanks for the reply rickman. > > > > > > That makes sence now. > > > I see that passing of values between modules is done using slv.. but you > > > can can convert (not cast) inside of each module. The signed port gives > > > non-synthesizable code. At least my simulator refuses to simulate. > > > > > > Thanks > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74724
newman wrote: > > Rickman, thanks for taking the time for the reply. > > sig_out_slv <= std_logic_vector(unsigned(sig_out_slv) + 1); > -- unsigned '+' natural yields an unsigned value > -- Ashenden's 2'nd edition Figure 8-11 > -- Addition and subtraction of two vectors: the larger of the two operand > -- lengths That is useful info. I always clutter up my code with type conversions/casts from slv to integer and back to slv. This is much simpler. > I enjoy reading your posts! Thanks, I appreciate the comment. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z