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Dear all, I am using Virtex-II Pro device and testing the data transfer rate between PPC and PLB-BRAM(or PLB-GPIO). All peripheral access functions are directly taken from Xilinx driver. Finally I found out that the maximum PPC to PLB-BRAM data transfer rate is only about 50Mbps!! This is far from the noted figure(hundreds of MBps). I would like to know how to speed up the data transfer rate in this case. Where can I find such information. I only found the 'burst' transfer feature available in PLB-BRAM datasheet,while don't know how to employ it in real C application. Thanks for your kind advice or discussion! Rgds, JeffsenArticle: 74951
<Chris> wrote in message news:ee899cf.6@webx.sUN8CHnE... > My first experience with BGA, I stuck the vias in the pads. The company that was installing the chips for me said it would be fine. They got one to work out of about 20 tries, after which I gave up and did some research and redid the board the right way. > We've put vias on the pads with two big bga designs - one using a Motorola MPC561 with around 360 balls, and one using a Stratix with 1040 balls. Both designs worked perfectly first time (well, the Stratix board doesn't work fully yet - but not because of dodgy connections!), and we've made several dozens of the MPC card with no failures. Putting a hole in these pads is outside the spec's for our pcb supplier (they are 18 mil pads with a 9.8 mil hole in the middle), but they took it as a challenge. They filled the holes with varnish - without that, there would be the risk that the solder would flow through the hole during soldering and leave a bad joint. To be honest, I can't see how we could have routed the card without doing this. Putting vias between the pads takes up more space and needs tighter clearances, especially on the top layer. > 5/5 spacing is as low as I've gone, never had to try 4/4 with 2 tracks through yet. Sounds like fun. Most of our Stratix board is 6/6, but I used 4/4 for the area around the FPGA on the top and bottom layers only (where it is easier to check!) to get denser routing where I needed it the most.Article: 74952
Hello Does Vxworks OS contain a Java Virtual Machine? If it does, Which of the one following does it support? a. Java Edition (j2se, j2me) b. Version (1.3?) Otherwise is there any JVM that can be ported to Vxworks.? Thanks in Advance Cheers ShakithArticle: 74953
Just out of interest, what error message do you get from Aldec on this code? Hans. www.ht-lab.com "Ray Andraka" <ray@andraka.com> wrote in message news:4178469F.7E337BDE@andraka.com... > You might try the Aldec tools. They give you much better > error messages, as well as a considerably more friendly user > interface. > > Gabor Szakacs wrote: > > > O.K. I did something stupid, but as a newbie to > > both Verilog and Modelsim I expected a nice error > > message instead of no indication and no response > > while I watched all of my virtual memory get gobbled > > up. Then Modelsim closed (was killed by Windows). > > > > A > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, > 1759 > >Article: 74954
> Hi, > I'm looking to integrate a FPGA based program into a PC based > application. ... ... Hello, is serial communication a must? If not you could use the PC parallel port (parport macro and associated software) and transfer data at 500KBytes/sec, no special semiconductors needed. Free sources available. see: http://www.xilinx.com/publications/xcellonline/xcell_45/xc_pdf/xc_seng45.pdf http://www.seng.de/dlk_interface_.html http://www.seng.de/dlk_.html with best regards, Peter Seng ############################# SENG digitale Systeme GmbH Im Bruckwasen 35 D 73037 Goeppingen Germany tel +7161-75245 fax +7161-72965 eMail p.seng@seng.de net http://www.seng.de #############################Article: 74955
Hello All
I have a problem with my simulation.
Can some one tell me whats wrong. It may be in my test bench as Im no
expert.
I have reduced the verilog so that its at its simplest.
What I find is that a signal which should be toggling in sequence with
the clock in my test bench is just not doing so.
Its the signal Int_Read_Trigger_Address_Clk in the module code. Its
just going high when the clear line goes low.
Its so simple I cant believe its not working.
Please have a look below.
------------------------- This is the test bench
--------------------------
`timescale 10ns/10ns
module Comisn_24_tst;
// Set up local variables for passing parameters to the device under
test.
// INPUTS
reg TOP_Main_clk;
reg TOP_clear;
reg TOP_Read_Trigger_Address_Clk;
comisn1_Top DUT ( TOP_Main_clk, TOP_clear, TOP_Main_clk);
initial // Test stimulus
begin
// Set initial values for all module inputs.
TOP_Main_clk = 0;
TOP_clear = 1;
TOP_Read_Trigger_Address_Clk = 0;
// Set clear line low .
#50 TOP_clear = 0;
#50000 $stop;
end
initial // Clock generator
begin
TOP_Main_clk = 0;
forever #10 TOP_Main_clk = !TOP_Main_clk;
end
always begin
#10 TOP_Read_Trigger_Address_Clk = !TOP_Read_Trigger_Address_Clk;
end
initial
$monitor($stime,,, TOP_clear,,,
TOP_Main_clk,,,TOP_Read_Trigger_Address_Clk);
endmodule
------------------------- This is the module
-----------------------------
module comisn1_Top (Main_clk, clear, Read_Trigger_Address_Clk );
input Main_clk;
input clear;
input Read_Trigger_Address_Clk;
reg Int_Read_Trigger_Address_Clk;
/////////////////////////////////////////////////////
// First Off Synchronise all external signals to
// the main clock for the system.
/////////////////////////////////////////////////////
always @ (posedge Main_clk or posedge clear)
begin
if(clear)
begin
Int_Read_Trigger_Address_Clk <= 1'b0;
end
else
begin
Int_Read_Trigger_Address_Clk <= Read_Trigger_Address_Clk;
end
end
endmodule
----------------------------------------------------------------------
Many thanks for any help in advance.
Regards
Denis
Article: 74956
> Hi,
> I'm looking to integrate a FPGA based program into a PC based
> application.
> I understand i need to write a serial interfacing code on the FPGA
> side and an API on the PC side,considering i intend to use a RS 232
> serial interface bet'n the PC and the FPGA board.
> I need help regarding the PC side API programming.I'll be using a 'C'
> program and would like to call the FPGA based functions.
> Can anyone suggest how i go about this?any references?
>
perhaps this few lines of C can get you started (if you're using Windows):
DCB dcb;
HANDLE hCom;
DWORD dwError;
BOOL fSuccess;
//
// open serial line
//
hCom = CreateFile(argv[argc-1],
GENERIC_READ | GENERIC_WRITE,
0, /* comm devices must be opened w/exclusive-access */
NULL, /* no security attrs */
OPEN_EXISTING, /* comm devices must use OPEN_EXISTING */
0, /* not overlapped I/O */
NULL /* hTemplate must be NULL for comm devices */
);
if (hCom == INVALID_HANDLE_VALUE) {
dwError = GetLastError();
printf("error\n");
exit(-1);
}
fSuccess = GetCommState(hCom, &dcb);
if (!fSuccess) {
printf("error\n");
exit(-1);
}
//
// set properties
//
dcb.BaudRate = 115200;
dcb.ByteSize = 8;
dcb.Parity = NOPARITY;
dcb.StopBits = ONESTOPBIT;
/* use RTS/CTS handshake */
dcb.fOutxCtsFlow = TRUE;
dcb.fRtsControl = RTS_CONTROL_ENABLE;
dcb.fOutxDsrFlow = FALSE;
dcb.fDtrControl = DTR_CONTROL_DISABLE;
dcb.fDsrSensitivity = FALSE;
fSuccess = SetCommState(hCom, &dcb);
if (!fSuccess) {
printf("error in SetCommState\n");
exit(-1);
}
// write a single byte
WriteFile(hCom, &data, 1, &cnt, NULL);
// read a single byte
ReadFile(hCom, &c, 1, &cnt, NULL);
Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/
Article: 74957denis, i think there is an error in the instantiation of the module called comisn1_Top at the following line: > comisn1_Top DUT ( TOP_Main_clk, TOP_clear, TOP_Main_clk); infact the port called Read_Trigger_Address_Clk is assigned to TOP_Main_clk that is the same clock used for the register called Int_Read_Trigger_Address_Clk. in this case the clock will sample itself and it will always be 1. andrea "Denis Gleeson" <dgleeson-2@utvinternet.com> wrote in message news:184c35f9.0410220130.5de8185@posting.google.com... > Hello All > > I have a problem with my simulation. > Can some one tell me whats wrong. It may be in my test bench as Im no > expert. > I have reduced the verilog so that its at its simplest. > > What I find is that a signal which should be toggling in sequence with > the clock in my test bench is just not doing so. > > Its the signal Int_Read_Trigger_Address_Clk in the module code. Its > just going high when the clear line goes low. > > Its so simple I cant believe its not working. > > Please have a look below. > > ------------------------- This is the test bench > -------------------------- > > `timescale 10ns/10ns > > module Comisn_24_tst; > // Set up local variables for passing parameters to the device under > test. > // INPUTS > reg TOP_Main_clk; > reg TOP_clear; > reg TOP_Read_Trigger_Address_Clk; > > comisn1_Top DUT ( TOP_Main_clk, TOP_clear, TOP_Main_clk); > > initial // Test stimulus > begin > // Set initial values for all module inputs. > TOP_Main_clk = 0; > TOP_clear = 1; > TOP_Read_Trigger_Address_Clk = 0; > // Set clear line low . > #50 TOP_clear = 0; > #50000 $stop; > end > > initial // Clock generator > begin > TOP_Main_clk = 0; > forever #10 TOP_Main_clk = !TOP_Main_clk; > end > > always begin > #10 TOP_Read_Trigger_Address_Clk = !TOP_Read_Trigger_Address_Clk; > end > > initial > $monitor($stime,,, TOP_clear,,, > TOP_Main_clk,,,TOP_Read_Trigger_Address_Clk); > endmodule > > ------------------------- This is the module > ----------------------------- > > module comisn1_Top (Main_clk, clear, Read_Trigger_Address_Clk ); > > input Main_clk; > input clear; > input Read_Trigger_Address_Clk; > > reg Int_Read_Trigger_Address_Clk; > > ///////////////////////////////////////////////////// > // First Off Synchronise all external signals to > // the main clock for the system. > ///////////////////////////////////////////////////// > always @ (posedge Main_clk or posedge clear) > begin > if(clear) > begin > Int_Read_Trigger_Address_Clk <= 1'b0; > end > else > begin > Int_Read_Trigger_Address_Clk <= Read_Trigger_Address_Clk; > end > > end > > endmodule > ---------------------------------------------------------------------- > > Many thanks for any help in advance. > > Regards > DenisArticle: 74958
<is about Anttis NIOS clone> >> So, either it's available, or it's not. What's it to be? >> >> John > http://ipcores.openchip.org > Hi Antti, isn't 'Please ask for pricing' on a website with 'openchip' in the domain name a little bit controversial ;-) I know, providing the source code of a processor for free download to be 'open-source' AND trying to sell the design is an unusual and problematic (or better no) business model. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 74959
This would make a nice toy for the desktop: http://www.shopaltera.com/category.asp?catalog%5Fname=ALC&category%5Fname=Demo+Tools Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 74960
gabor@alacron.com (Gabor Szakacs) wrote in message news:<8a436ba2.0410211013.7a931730@posting.google.com>... > Wait a minute... Spartan doesn't have INTERNAL tristate buffers > but all FPGA's have tristates on I/O pins. Were you trying to > run internal logic as tristate? That is no longer available > for Spartan 3. I/O pins should be tri-statable in any family, > but using IOB primitives from another family can get you in trouble. > Right! This supports the result, we've got from my actual design. We have managed the tristates only on toplevel now and do not use any internal tristates (e.g. because of bidirectional lines) yet. Now the connection of the pci-card to our development system works very fine! Thanks a lot either! Thomas.Article: 74961
Hello, In another topic, I discovered that there was no internal 3-state buffer. So, how should I do it if I have let's say 1 master and n slaves on a bus. The master puts an address, and then can either read or write from the slave. 1 bi-dir bus don't seem like a good choice ... So with a din & dout from the master : No problem for dout, only the masters drivers it. But for din, multiples slaves would like to drive it ... I could use a multiplexer for din but it mayu grow quickly ... What's the common way of doing this ? The context is a PCI target core that translates single IO request to request to that internal bus, then different cores expose theirs regs thru it. SylvainArticle: 74962
Hi Vic, Yes, I constrained the clock in the UCF. Alternatively, I also tried the -a option for the TRCE. Both methods give me no Fmax. Thanks Vic Vadi <vic.vadi@xilinx.com> wrote in message news:<4176C862.7E81ED5C@xilinx.com>... > Hi William, > > Did you include a timing constraint of some ns on > your clock in the ucf file? > > - Vic > > William wrote: > > > There is no Fmax reported when I instantiated a DSP48 with internal > > input and output registers turned on. Anyone have any ideas, why this > > happened? > > > > Thanks. > > --Article: 74963
Hi Leon, > This would make a nice toy for the desktop: > http://www.shopaltera.com/category.asp?catalog%5Fname=ALC&category%5Fname=Demo+Tools Yes, it does. It makes a great clock or stock ticker when not being used to try out a design. Very snazzy. Paul Leventis Altera Corp.Article: 74964
Hi Rick, > I am confused. I thought the OP was looking for 5 volt tolerant chips, > no? I am pretty sure the MAX-II is not 5 volt tolerant. Or is it??? > If it is, I would like to know more about the intro schedule. When is > the LPM2210 planned? I thought the original poster was looking for 3.3V or 5.0V. Max II is 3.3V tolerant, not 5.0V tolerant. The 2210 will be out Q1'05. - PaulArticle: 74965
> In another topic, I discovered that there was no internal 3-state buffer.
> So, how should I do it if I have let's say 1 master and n slaves on a bus.
> The master puts an address, and then can either read or write from the slave.
>
> 1 bi-dir bus don't seem like a good choice ...
> So with a din & dout from the master : No problem for dout, only the masters
> drivers it. But for din, multiples slaves would like to drive it ...
>
> I could use a multiplexer for din but it mayu grow quickly ...
Yes, MUXs are the way to go. However, you can still use tri-state values
in your VHDL code ('Z') and the synthesizer will implement the resolution
as MUXs.
I remeber a discussion where one guy believed that there must be tri-state
buses inside the FPGA (there where never TS buses in Altera FPGAs)
because he used the 'Z' values in his code (synthesizers are smart).
That coding style can save you a lot of code and keeps things modular.
I'm using it for an internal IO-subsystem bus.
Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/
Article: 74966Hi Martin, > However, if the LAB global inputs such as 'sload' and 'ena' are not available > for the synthesizer you're 'wasting' resources. Do you use these signals for other > functions (perhaps the loadable counter)? This problem is specific to combining the addsub feature with the sload signal (I think). When you write a vanilla loadable counter or other such code that requires an sload, enable, etc. Quartus should be using the LE properly. Note: There are some circumstances where we do not use an sload or other control signal even though we could. For example, I don't think we recommned that synthesis tools use sload or enable as general logic signals since these signals are shared LAB wide and if you and up with oodles of independent sload or enable signals in a design, there will be poor packing. That's an example where even though the synthesis will use fewer LEs, the # of LABs required will be higher and thus the synthesis is "larger". > BTW.: Do we really need asynchronous signals such as PRN/ALD, ADATA > and CLRN (ok this one for the asynch. reset) in these days? Isn't that a waste > of resources usfull only for a some designed who doing asynchronous design. The quick answer is no, no one should be using many asynchronous control signals. But users do, and if the user writes their (bad?) HDL so that they have async signals, and we don't have the hardware, our only choice is to emulate the async functionality using logic elements. And then you get into some difficulty with the start-up condition of these soft flip-flops, potential glitch issues if not careful, etc. If you look carefully at Cyclone II, we have removed the aload capability since this is cheaper to implement in soft logic for those few times people use it -- we might as well tax the users with aloads rather than burden every user with the slight silicon bloat there would be with hard support. > > In the meantime, there is a work-around. You can directly instantiate > > "stratix_lcells" (the WYSIWYG cell for Stratix/Cyclone LEs). Below I give > > Is there some documentation about these AYSIAYG lcells? I was looking for such > an entity in the Megafunctions/LPM help of Quartus (befor you provided the solution) > to implement this function. However, I did not find these basic megafunction. There is no "user" documentation on the WYSIWYG (I like the all version ;-)). We are working on some documentation that may be released in the future. In the meantime, you can also download the QUIP toolkit (search for QUIP on www.altera.com). This is a package we make available for academics who are designing CAD tools. It provides a document describing the Stratix (and thus Cyclone and Max II) LE WYSIWYGs. Regards, Paul Leventis Altera Corp.Article: 74967
Our experiences with Spartan-3 are good. Your issue with tristates may be a design structural problem. We don't use schematics but an issue with VHDL file structures which probably also applies to schematic. When a tristate is not in the top level you get an internal tristate inferred and a linked output pin usually adopts a hard level. Now given the lack of tristates the tools usual convert tristates to a logic mux in a family like Spartan-3. So if you want a pin tristate function try implementing it at your design top level. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Thomas Bartzick" <thomas.bartzick@atlanticzeiser.com> wrote in message news:47ce721b.0410190358.4d52344a@posting.google.com... > Hello together, > > has anyone experience with tristates in SPARTAN3-fpgas? > If we implement a schematic-oriented structure we won't get any > error-messages but only warnings and the design will be compiled fine. > But it seems that all our tristate outputs are driven permanently > (which is very bad!). > > Hints are very appreciated! > > Thanks, > > Thomas.Article: 74968
I think you will find that you need to do a web install at present to get all the devices. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Hendra" <u1000393@email.sjsu.edu> wrote in message news:3ef7b4ba.0410202025.55b1b801@posting.google.com... > Hi folks, > I notice that the pull down menu for Webpack 6.3i SP2 indicates it > supports Spartan 3 XC3S2000, 4000 and 4000L. Xilinx website said that > this version of Webpack only supports up to XC3S1500. Is there > something wrong with the software GUI, or is the support for higher > device for real? > Thanks in advance! > > HendraArticle: 74969
Hi, For a quite large project dealing with Virtex 4, DDR2, gigabit ethernet and digital signal processing, I'm looking for a top of the bill design house in a far east country like india. All tips are welcome. Best Regards, AnomArticle: 74970
Hi all, firstly I would like to thank all of you guys for answering.. here are some more facts, before posting my questions I've made the following.. (with no sucsess). Multi clocks - my design is indeed using few clock sources but each of them is driving a speperate block (i.e. only one clock is driving the data in/out of a single FSM). Async reset: before I've encountered the problem I used an async reset such as process (resetn,clk) begin if resetn ='0' then ... elsif rising_edge(clk) then ... but when the unstabilty problem has rised I immidiatly changed all my design to work on a sync reset such as process (resetn ,clk) begin if rising_edge(clk) then if resetn ='0' then .... else ... but it did not helped me .. undesired Latch inferences: I also searched my entire design for warnings about latch inferences or some other warning that might indicate regarding an un-intentioned logic implementation (I found one warning regarding a latch, fixed it but the problem didnt "died"). Gated clocks - I dont think that I'm using them but I would be very happy if someone will give me a VHDL code example that will cause a gated clock. so I can be sure what you guys ment by "gated clock". Simulation - I'm not fimiliar with the term "sky-wire" (mentioned by chris) maybe someone can explain what's the meaning of it. FSM encoding: I also changed my FSMs encoding to GRAY instead of "one hot" beacuse from ny past experinse in some cases it helps (but it didnt help). synthesis - Chris mentioned that even the same code could be synthesized differntly on each synthesis. In my case it's no so! I use Source safe for version control and save a version of every "good" synthesis and I saw that whenever I synthesize a code that has worked before it's always continuing to work. In the past when I encounterd such problems I used the ChipScope LA to find & debug them but now the problem is moving from block to block and the chipscope itself when used is also changing the logic (using the device LUTs and RAM resources) so I can't realy use it. I didnt tried yet to run the entire design on a lower frequency rate, that was a good sugesstion and I will try it. I will also try to "play" a little with power supply and with the temperature.. I was wondering if something in my syntheis/MAP/P&R configuration is wrong maybe you can throw me few tips on this subject too (I'm using Xilinx project navigator 6.1 with XST). again, lots of thanks. Regards, Moti.Article: 74971
"Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> wrote in message news:4178f358$0$15734$ba620e4c@news.skynet.be... > Hello, > > > In another topic, I discovered that there was no internal 3-state buffer. > So, how should I do it if I have let's say 1 master and n slaves on a bus. > The master puts an address, and then can either read or write from the slave. > > 1 bi-dir bus don't seem like a good choice ... > So with a din & dout from the master : No problem for dout, only the masters > drivers it. But for din, multiples slaves would like to drive it ... > > I could use a multiplexer for din but it mayu grow quickly ... > > > What's the common way of doing this ? > > The context is a PCI target core that translates single IO request to request > to that internal bus, then different cores expose theirs regs thru it. I've put my multiple reads through a series of OR gates. Rather than using a multiplexer which allups up to 2 elements per logic cell in one structure, I use gated results - two per LUT - where these LUTs can be located closer to the sources, potentially making routing a little easier. While I register this first stage, many designs may not have that luxury. A wide OR of all those gated results comes down to a very nice logic tree to get low delays through standard logic without having to consider the issues around a mux. Do multiplexers do a good job when there are a number of unpopulated nodes on the MUX tree? A wide OR doesn't care. There is a little extra time to generate the gate signals from the address where the time would be more or less free in a MUX but I have the address before I have my read data qualified (I'm not on the PCI bus, myself) so the initial decodes aren't a big timing hit. These gates are the same signals that would be used for an internal tristate anyway, so if you have an existing tristate-driven design, it should be simple and timely to change it to a wide OR of gated signals.Article: 74972
"John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:cl9cas$gf8$1@bunyip.cc.uq.edu.au... > Hi Antti, > > Antti Lukats wrote: > > "Jon Beniston" <jon@beniston.com> wrote in message > > >>"Antti Lukats" <antti@case2000.com> wrote in message > > >>>1) are you going to release the HDL sources? > > >>Similarly to you Antti, are you going to be releasing the HDL source for > > NIOX? > > > lets put it that way, NIOX sources are obtainable ;) > > What does that mean? > > You earlier wrote: "NIOS-II verilog also exists, but it will not be GPL > ;) " > > So, either it's available, or it's not. What's it to be? > > John http://ipcores.openchip.org AnttiArticle: 74973
I haven't seen the docs on the website anywhere. It comes with a CD with docs like the
board schematic. I have one that I intend to play with for some DSP demo apps...in my
spare time. In the mean time, it is serving as a desk clock. I hope to have a DSP
demo using it by FCCM next spring.
"Paul Leventis (at home)" wrote:
> Hi Leon,
>
> > This would make a nice toy for the desktop:
> >
> http://www.shopaltera.com/category.asp?catalog%5Fname=ALC&category%5Fname=Demo+Tools
>
> Yes, it does. It makes a great clock or stock ticker when not being used to
> try out a design. Very snazzy.
>
> Paul Leventis
> Altera Corp.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 74974Hi all, I've been using Altera parts and tools for quite a while and currently have Quartus-II 4.1 on my PC along with the Modelsim-Altera 5.8c. Now I need to do a Virtex-II design so I obviously need to put some Xilinx software on the PC. I've used Xilinx devices and tools before (not the newest ISE, but a pretty old version of Foundation I think and the earlier Webpacks). Anyway, I've installed the newest version of the Webpack software (looks like I remember it for the most part) to use at least initially, but I hesitated on installing the Xilinx Modelsim. If I install the Xilinx modelsim along with the Altera-Modelsim am I going to have all kinds of conflicts? I've never had both on the same PC. Right now the Modelsim-Altera is working well integrated into Quartus to fire up a timing simulation immediately after fitting so I'd hate to mess something up. I'd imagine I could do behavioral simulation of the core VHDL files for the Virtex project in the Modelsim-Altera fine, I just figure I'll have to have the Xilinx version to do any kind of post-place and route timing simulation for the Virtex part. Is this correct? Does anyone know the best way to go about this? Thanks. Sean
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