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Another consideration is that soft processors allow customization. It is relatively easy to add a special purpose hardware DSP function to a soft micro. Using off the shelf components requires a new component for a new function. yong.qin@ecadusa.com (kathy) wrote in message news:<c18c5dac.0409161222.314d5c59@posting.google.com>... > What is different between general micro-controller and FPGA soft > processor? > > Speed? > Cost? > Easy to use? > Easy to learn? > > I am curiouse if the soft controller will replace the regular > microcontroller? > > Xilinx said they implement 32-bit RISC controller with a lot of > benefits. Would that replace ARM?Article: 73276
senthil wrote: > Hi friends.. > > In my board design of FPGA, I Want to interface the Spartan-3 > xc3s400-tq144 with PC/104 ISA bus. I'm new to the interface design. > Pls give some suggestion. > > Regards > > Senthil Chett. S3 is not 5V IO tolerant. You will need to have level shifter to pass from 3.3VIO to 5VIO. One solution is to use pullup resistor for output and serial resistor for input... Can be OK for proto board The only solution, for commercial product, is to use specific level shift device between you s3 and the ISA bus port. Anyway, why not S2 ? Laurent www.amontec.comArticle: 73277
Allan, Well, you don't expect us to tell all of our secrets, do you? Seriously, there is no security in obscurity (I am quoting someone here, but I do not know who, so I apologize). I will find out what mechanism we use to clear the bits for you. We do comply with FIPS on zeroisation (at least from my tests in the lab). One common trick we used ages ago was to make the memory bits highly asymmetric (2K, 3K, 4K series). This way upon power loss, they have no choice but to return to a known state when power is restored. That would make all of those assumptions about freezing cells, and repowering pretty useless (or detecting gate charge, etc.). The re-powering of the cell has no choice but to return to the known state because it was designed that way on purpose (and we had 14 years of experience doing that, so we got pretty good at it, too). This asymmetric cell power on is what we used to prevent power on current surges. Unfortunately with ultra-deep sub-micron and 20 million or more config bits, we could no longer count on 100% of the cells to power on to a 0 under all possible power supply ramp rates, process corners, voltages, and temperatures on all parts. So we abandoned that method for config. We are preparing a USB card to demonstrate security concepts. One possible challenge we may issue is to ask people to hack it and tell us: what is the unencrypted bitstream? what is the key? how can you make the application do what you want it to (the app is a true random number generator -- make it do something non-random)? I would love to have determined hackers attack our device, and let us know just how secure it really is. That way, any weakness can be corrected in the next generation. Email me directly if you are interested. It will probably be sometime in early 2005 that we will go out with this on a large scale (if there is sufficient interest). But in the meantime, we will trial it with a few serious and determined engineers. It is one thing to talk about it, it is another altogether to actually try to crack it. We will provide a full set of schematics and a description of what it does, and how it is intended to be used. No obscurity, just security. Austin Allan Herriman wrote: > On Thu, 16 Sep 2004 14:37:07 -0700, Austin Lesea <austin@xilinx.com> > wrote: > > >>OOPS! >> >>http://www.xilinx.com/products/virtex4/capabilities/designsec.htm >> >>We have AES 256 bit key in THIS generation! (---twice the key length of >>our nearest competitor with similar features) >> >>Oh, and to be compliant with the federal standard for encryption, you >>are not allowed to use non-volatile key storage (must allow >>'zeroization'). Non volatile key storage is trivial to reverse >>engineer. I asked our F/A lab how long it would take to read the value >>of EM polyfuses (invented by IBM), and they repplied "less than a hour." > > > Note that FIPS compliant 'zeroization' requires actively setting all > the bits in the key to zero. > Turning the power off and hoping that the bits change isn't the same > as zeroization. > > This implies the following: > > 1. Either Xilinx isn't performing zeroization (and I haven't found > anything in the data sheet that indicates that they do perform FIPS > compliant zeroization). Hmmm. > > 2. Or, Xilinx have added a low voltage detector and a have developed a > ram with a 'clear' input, or have developed a ram cell that always > goes to a known state as the supply drops. > > 3. Or, zeroization is possible, but can only happen when the user > overwrites the key with zeros, which is only possible when the power > is on (and wouldn't be too hard to circumvent in a real product). > > > Please note: I'm commenting on Austin's use of the (well defined) term > 'zeroization'. I don't mean to imply that I think that there is > anything wrong with the security of the Xilinx parts. > > Regards, > AllanArticle: 73278
Adam, See my other posting today. And, you are correct, we have no NVRAM in our FPGA devices right now. If we did, we would first use it for more useful things (like serial numbers, lot code, etc). NVRAM as I described is not secure, so using it for security means the secret you wish to keep is not worth very much. But, hey, there are lots of folks that have inexpensive secrets. I just do not know any that are seriously considering basing their entire product line's secrets on NVRAM solutions..... And, we have "been there, done that" on having some kind of structure that is inherent in the device, but which provides a unique ID or key. Never succeeded in making any of the methods work. We make just too many chips. And will it change over time? Well, Vts, Idsats, and just about everything else now changes over time (the transistors themselves change as they age in these ultra-deep sub-microm technologies). Austin Adam Megacz wrote: > Physical means. There are quite a few companies in Taiwan that > specialize in this. There might also be noninvasive imaging > techniques similar to those used for MRI or perhaps even Van Eck > phenomena. Dallas Semiconductor is pretty familiar with these attacks > since they specialize in designing NVRAM devices that clear themselves > in such scenarios. > > Actually, I would sincerely hope that the key isn't held in any sort > of "memory"; even ROM. If I were designing such a system I would make > sure that the "key" was an emergent property of some structure with > lower spatial complexity than the key itself (for example, a > sequential circuit computing the collatz sequence). > > I suppose an even better protection technique would be to base the key > on some analog, physical property of the chip itself combined with a > per-chip "offset" value. For example, a function of the ratio of > oscillation frequencies of two pairs of inverters, plus some offset > value "X" which is computed during the testing process and then > flashed onto the chip (ie each chip has a different oscillatior value > due to process variations as well as a different X -- but they all sum > up to the same universal decryption key). > > I hadn't thought of this before; this would actually be pretty hard to > extract. But at the same time I doubt that Xilinx is hiding any NVRAM > in their chips; if their process allowed for that they would probably > offer some of it to their customers -- even a few bytes would still be > handy. > > I suppose that this is my core point: as long as every Xilinx chip of > a given type is exactly the same with respect to the part of it that > performs decryption, I'm highly suspicious of any design security > claims. > > And if you're going to go so far as adding nonvolatile storage to a > chip, well, you might as well go the Actel route and save your > customers the hassle of putting an extra chip on board just to serve > up the configuration data. This also means that a breach of one > particular device's security doesn't compromise the IP of every single > customer at the same time because of a shared secret: Xilinx is > putting all of their customers in the same high-profile basket. > > - a > > > > Austin Lesea <austin@xilinx.com> writes: > >>Adam, >> >>And how do you propose to read out the bits from the key memory? >> >>Austin >> >>Adam Megacz wrote: >> >> >>>Hey Nick, 441 Soda Hall just isn't the same without you.... =( >>> >>> >>>>Thus you have the encrypted bitfile loading on the Virtex lines. >>> >>>Well, IMHO it doesn't qualify as encryption when the chip itself -- >>>which you're giving to your customers -- contains the decryption key. >>> >>> >>>>Personally, I think the V4 version is easily good enough for >>>>protecting a $10,000 secret, and I could probably be OK comfort wise >>>>protecting a $100,000 secret. >>> >>>$10k (loaded cost) will buy you about half a month of a mediocre >>>hardware engineer's time. I doubt many of Xilinx's customers' designs >>>are that simple. Even <$100k designs probably constitutes an >>>unimportant fraction of their market. >>>But I agree with your estimate. I could envision the task of >>>extracting the decryption key from a Xilinx part as being a feasible >>>project with around $300k of funding and the right team to pull it >>>off. >>>So, basically, I wouldn't trust the security of any serious >>>commercial >>>design to Xilinx's obfuscation. Now lawyers, on the other hand... =) >>> - a > >Article: 73279
Say, your clock cycles aren't something very slow like 4MHz, is it? Your speed needs would help drive an "ideal" solution since you could perform all the compares with one comparator over 32 cycles. "Kumar Vijay Mishra" <vizziee@yahoo.com> wrote in message news:889cd7c9.0409152205.35aeb3c@posting.google.com... > Hi. > > I am working on inmplementation of order statistics CFAR, where > sorting of a continuous stream of data is required. > > Exactly problem is as under: > I am getting a continuous stream of 16-bit data. In every clock cyle I > have to sort 32-size array. When I have sorted the array in ascending > order, I want to choose 24th number only. In the next clock cycle, I > get a new no added to my array while the first number gets out of the > array. The new array that I get is to be sorted again and he 24th > position number is to be taken out. > So, in every clock cycle, I get a new data (in an array of 32 16-bit > numbers) (with the oldest data getting deleted from this array) and in > the same clock cycle, I need to have the 24th-position data available > to me for further processing. > > Can anybody help me in this? Plus if someone can direct me to any > useful link on VHDL designs of sorting, since I am new to FPGA and > VHDL. > > Thanx in advance.Article: 73280
Laurent Gauch wrote: > > senthil wrote: > > Hi friends.. > > > > In my board design of FPGA, I Want to interface the Spartan-3 > > xc3s400-tq144 with PC/104 ISA bus. I'm new to the interface design. > > Pls give some suggestion. > > > > Regards > > > > Senthil Chett. > > S3 is not 5V IO tolerant. You will need to have level shifter to pass > from 3.3VIO to 5VIO. > > One solution is to use pullup resistor for output and serial resistor > for input... Can be OK for proto board > > The only solution, for commercial product, is to use specific level > shift device between you s3 and the ISA bus port. > > Anyway, why not S2 ? I use a level shifter, an Altera ACEX EP1K50. It is fully 5 volt tolerant and does not have the high startup current requirements of the Virtex based parts (Virtex, Spartan II, Spartan IIE...). -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73281
Andre Bonin wrote:
> I have an algorithm i would like to implement in an fpga. I have no
> idea of knowing how many times the 'while' loop should run.
Consider adding a clock input and use
a synchronous process loop that executes
once per clock.
Now, within this process, you can do as
many sequential statements as you like
up to the limit of the clock cycle time.
A static timing analysis can check this
for you after synthesis.
Step one is to get your code running
synchronously and correctly in a
simulation testbench.
Step two is a trial synthesis and
static timing check.
If static timing fails the FMAX constraint,
modify your code to do less per clock,
or reduce the clock frequency.
Good luck.
-- Mike Treseler
Article: 73282Hi all. I'm looking for FPGA for real-time video processing. The requirements are not yet fixed, but I think something like Xilinx Virtex-II Pro from XC2VP7 to XC2VP30 would be a good choice. PCI interface would be nice so that I could plug the card in and transfer uncompressed video frames into the card and get compressed frames back. Something like, say 100 Mbit/s Ethernet, might also work but then it would use pretty much all of the bandwidth. Also, I want to do development on Linux (Debian) host, so the tools should run on that. Running Linux on the FPGA PowerPCs sounds like a nice idea too. My question is: what hardware and software do I need? Looks like I need: - The development board. Prospective candidates are Alpha Data's ADM-XPL and Amirix boards. Something from Avnet might also do, except that it appears they don't support Linux. Not sure about Alpha Data either. And then there's Xilinx's ML310 which appears to be a complete computer with PCI slots and Ethernet. But it might have some bandwidth problems, unless I connect camera directly into the PCI slots in the board. - Hardware development tools. Are there other alternatives than ISE Foundation/BaseX? And are there differences between the two except that the latter supports devices only up to XC2VP7? - Software development tools. Should I get them from the board vendor or is it possible to use them from third party? I have found EDK from Xilinx and the TimeSys SDK. What is the difference between the two? Other alternatives? - Operating system for the PowerPC inside the FPGA. Does this come with the development kits or would I need to get one separately? - Something else? I hope the questions were not too silly, but I haven't done any work with FPGAs before.Article: 73283
The problem with a soft processor is that you are never finished. I am sitting with various versions of NIOS and their related SDKs. Cost is also high. A Cyclone with config chip + RAM and Flash will be several times the cost of a gemeral micro. I have several projects where that kind of cost is no problem. Another drawback is small to medium quantity manufacturing requires extra config steps. Advantages with a soft core are plenty. The speed problem is counteracted by the capability of hard wired silicon co-processing. Once you learn your tool set (NIOS in my case) then the rest is easy. Be careful not to replace your trusty PIC or 8051 with a FPGA. If your 8051 can do the job then use your 8051, end of story. As soon as you have equal trade-off point then look at FPGAs. I have several access control applications where I need direct interfacing to passive readers, plenty of serial lines, large storage and medium speed (20-60 MHz). NIOS on a Cyclone serves me well. I still use Atmel 8051s on many other parts of my system because of the low cost. FPGAs can also save you a lot on board space, if your application requires a certain amount of resources. As soon as your board requires plenty of I/O (several 8255s), lot of memory (16 to 32 bit), more UARTs and other peripherals then a FPGA with a soft core will look more attractive. If you can get away with one or two AVRs, 8051 or PICs then use those chips. If your board starts looking like an old mini-computer's main CPU board (i.e. very large) then look at the FPGA. I have several design constraints like euro card size that I have to comply with. Smaller is not always cheaper. A 32 bit FPGA core will require 32 data lines, 20 + address lines and several control lines. This excludes your other I/O. Also you will require a config PROM (unless you are using a Actel Flash based FPGA). Your PCB ends up complicated and multilayered. And don't think of staying double sided and going longer tracks. Your super duper FPGA has very fast rise times that will play "ring-ring" with long tracks. Power supplies: Hmm. Big problem. Your common micros usually run of a single power supply. So you can power the device from a single 5V or 3V3 power supply. FPGAs are not good at this. Most of the newer devices requires at least 2 power supplies, namely 3V3 for I/O and some other obscure voltage for the core (e.g. 1.5V). Try to find a cheap 1.5V regulator. Also do the math with the drop voltage times the current drawn. Another problem is the inrush current on SRAM devices (like Altera and Xilinx devices). They can suck up like 1A of current during startup, and then draw very little afterwards. This requires using a higher current regulator. Your will end up with at least one switcher and one linear regulator. Extra cost. FPGAs are not cheap on power. If your system can afford it then go for it. A FPGA is not a 10mA max device. Go and check the specs. So do the trade offs: Cost/ Complexity/ Tools/ PCB layers/Size/ Power/Availability/Copy protection.... the list is long. Each device fills a market. There is no real threat of FPGAs taking over ARM CPUs. After you have done your trade-offs you will find the optimal solution. I chose NIOS because it fills about 50% of my systems's requirements. Are soft core CPUs cool? Yes. Do I use them for everything? No! Victor Schutte victor@zertec.co.za http://www.zertec.co.za "kathy" <yong.qin@ecadusa.com> wrote in message news:c18c5dac.0409161222.314d5c59@posting.google.com... > What is different between general micro-controller and FPGA soft > processor? > > Speed? > Cost? > Easy to use? > Easy to learn? > > I am curiouse if the soft controller will replace the regular > microcontroller? > > Xilinx said they implement 32-bit RISC controller with a lot of > benefits. Would that replace ARM?Article: 73284
Hi, You can use an odd-even transposition sort. This is a parallel version of the bubble sort that works well in hardware. I have a version of it written in Verilog on my site, http://www.engr.sjsu.edu/crabill in Lecture Module 6. You can adapt it to your application and then remove the pipeline registers if you want to trade frequency of operation for lower latency. Eric glen herrmannsfeldt wrote: > > If it really works that way there is just about only one way > to do it, because you must do everything in one clock cycle. > > You need to compare the number coming in against all the others > in the list, except the one going out, and arrange the new data > ready to clock in on the next cycle.Article: 73285
Although I have not posted yet to this group, I have an FPGA question. I am doing an evaluation of the Stratix II and the Virtex 4. Does anyone have any comparisons or experience of the features, performance, etc. of the two devices? I am trying to understand the tradeoffs of the two different platforms.Article: 73286
Hi, Maybe you can choose any of Insight Virtex-II board such as DS-KIT-V2MB1000-EURO plus a P160 CAN prototype module(DS-KIT-P160-CAN-1-EURO). See http://www.insight.na.memec.com for more detail. Hope it's helpful. "John Watson" <meleth_esp@yahoo.es> дÈëÓʼþ news:Xns9566869E4A542jcastilloopensocdesi@193.147.184.15... > Hello: > > Anybody knows any prototype board with a Xilinx Virtex II FPGA and a CAN > bus controller? > > Regards >Article: 73287
Hi, Can anyone recommend a good book on verilog? I've got some experience with VHDL, but am looking for a book on verilog with an emphasis on synthesisable design. Inclusion of the verilog 2001 additions would also be nice! Thanks in advance, AlexArticle: 73288
In article <slrnckm1nk.1ng.tuukkat@s-inf-pc92.oulu.fi>, Tuukka Toivonen <tuukkat@killspam.ee.oulu.finland.invalid> wrote: >- Hardware development tools. Are there other alternatives > than ISE Foundation/BaseX? And are there differences > between the two except that the latter supports > devices only up to XC2VP7? The free WebPack only supports up to the XC2VP4. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 73289
Tim, There is no comparison. Seriously. Just go to the websites and compare the features. V4 - triple oxide, low leakage, no power on surge in the core, faster, over 100 new technical features (like SSIO, DSP48 MAC's, BRAM/FIFO, 256AES, etc.) 4VLX25ES shipping now, development pcbs order entry open and shipping ... Stratix II - ... (I'll let them play marketing) Austin Tim Michaels wrote: > Although I have not posted yet to this group, I have an FPGA question. > > I am doing an evaluation of the Stratix II and the Virtex 4. Does > anyone have any comparisons or experience of the features, > performance, etc. of the two devices? I am trying to understand the > tradeoffs of the two different platforms.Article: 73290
I just bought an Atmel DK2 (from digkey) and when I attempt to install it, it tries to connect me to the Net. I want to install it on a computer that I use exclusively for design and development work that is not connected to the Net. Is there any way around this? Should I just toss this thing? DaveArticle: 73291
"IgI" <igorsath@hotmail.com> wrote in message news:31J1d.2798$F6.632356@news.siol.net... > Hi! > > A Xilinx representative came today to the company where I work and he had a > short but very informative Virtex4 presentation. What I find very useful is > that Xilinx finally put a FIFO control logic on BRAMs and significantly > increase their performance. Feature to cascade FIFOs will also be very > useful for me. I was also hoping to see a 256 deep and 64bit wide BRAMs, but > I guess we'll have to wait for that feature for a while? [snip] I was just contemplating adding a wide/shallow memory to my design and realized I *could* implement a 256 deep, 64bit wide memory in the BlockRAM. The only trouble is it's single-port.Article: 73292
Hello, I wrote, in regards to PCI Express implementations not using the distributed reference clock: > You can also use a local 125 MHz oscillator that is +/- 100 ppm. This is false. You cannot do this. Such a design would result in clocks off by up to 400 ppm. The Virtex-II Pro transceivers are not guaranteed to lock over that range. In a PCI Express system, you will need to do a 1.25 multply and clean up the reference clock with a PLL. I apologize for providing incorrect information. EricArticle: 73293
"John_H" <johnhandwork@mail.com> wrote in message news:xQJ2d.26$l1.2903@news-west.eli.net... > "IgI" <igorsath@hotmail.com> wrote in message > news:31J1d.2798$F6.632356@news.siol.net... > > Hi! > > > > A Xilinx representative came today to the company where I work and he had > a > > short but very informative Virtex4 presentation. What I find very useful > is > > that Xilinx finally put a FIFO control logic on BRAMs and significantly > > increase their performance. Feature to cascade FIFOs will also be very > > useful for me. I was also hoping to see a 256 deep and 64bit wide BRAMs, > but > > I guess we'll have to wait for that feature for a while? > > [snip] > > I was just contemplating adding a wide/shallow memory to my design and > realized I *could* implement a 256 deep, 64bit wide memory in the BlockRAM. > The only trouble is it's single-port. > Correct! You can do this now in Virtex-II, Virtex-II Pro/X, and Spartan-3. In fact, you can even build a 256x72 (x64 with parity). Figure 22 on page 27 of the following link shows how. http://www.xilinx.com/bvdocs/appnotes/xapp463.pdf --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 73294
Seriously... when are you planning to build? or are you after a one off... If its not been in the market a year its not worth trying to buy them yet! Only those in beta and those ordering thousands have any likelihood of seeing any. So its not what features they have got... but what features that you need that's important. We still use Spartan 2E's at work... why go to Spartan 3 or vertex if you don't need them ??? Simon "Tim Michaels" <tkellis4520@yahoo.com> wrote in message news:f3b2aaca.0409170912.4d645c36@posting.google.com... > Although I have not posted yet to this group, I have an FPGA question. > > I am doing an evaluation of the Stratix II and the Virtex 4. Does > anyone have any comparisons or experience of the features, > performance, etc. of the two devices? I am trying to understand the > tradeoffs of the two different platforms.Article: 73295
Hey all, I'me trying to convert a C algorithm to Verilog using Quartus II Web edition. The following for loop doesn't compile because it says its not of constant loop time. What i really need is to be able to calculate the loop time "on the fly". Can VHDL or Verilog do this? or is this a limitation? Thanks Error: Verilog HDL For Statement error at XXXXXXXX.v(49): must use only constant expressions in terminating conditions ---- Error at while loop - integer X = 0; always begin while( X < 30 ) begin X = X + 1; end endArticle: 73296
Hi! I'm doing the Modular Design Flow for Xilinx Virtex2 Pro (XC2VP7) device. I'm having problems getting all my BRAM's for my module. Since I do modular design I can only use one RANGE constraint, so I always get a rectangular AREA_GROUP RANGE. (Answer Record # 16423) AREA_GROUP "AG_system_0" RANGE = RAMB16_X0Y0:RAMB16_X4Y8; works fine, but I'm missing the BRAM located at X0Y9. AREA_GROUP "AG_system_0" RANGE = RAMB16_X0Y0:RAMB16_X4Y9; gives me an map error: "ERROR:MapHelpers:151 - Error while processing the area group range. Unable to create a LOC object using the constraint RAMB16_X0Y0:RAMB16_X4Y9 attached to area group AG_system0. One or more ranges contain syntax error or illegal site. Please modify the constraint." OK. I must not use forbidden BRAMs at X1Y9:X4Y9, but why is there no problem with forbidden BRAMs at X1Y0:X4Y0 Is there a way to get the missing BRAM for my design? Thanks in advance Andreas andreas@lowtexx.deArticle: 73297
Hi Larry, Perhaps a VHDL Obfuscator can help you out? They are not that expensive, Regards, Hans. www.ht-lab.com "Amontec Team" <laurent.gauch@amontecDELETEALLCAPS.com> wrote in message news:41419f93$1@news.vsnet.ch... > Hi all, > > I am in the case where I need to provide large VHDL code to a customer. > > The design is very large, with some parts written specially for the > customer and with some parts coming from our own re-use VHDL code. > > The application is PCI based with specific data processing, with on > board true random number generator modules. The PCI core side is the > bigger part of the our own re-use code, and we want to protect it. > > Now the question is: > > How to provide the PCI core side to my customer since he cannot (wnat > not to) pay for the generic VHDL source code? In an other hand, my > customer want (ready to pay) to be able to simulate all design, to be > able to modify the specific data processing part (not the PCI part), and > to be able to do new Place&Route of all the design. > > My company cannot pay for a software doing 'crypto' on the VHDL source > code with a concerponding core generator. > > I was thinking to provide to my customer a post-synt model corresponding > to a RTL description or post-P&R model for a specific techno like > SPARTAN-II (using XST). The trouble with post-synt models is we cannot > re-synt. the model for a new P&R version. > > So, what's the best way (low cost) to generate a RTL IP core (soft-hard > core) ? > > Thanks for advicing me ! > > LarryArticle: 73298
I suggest getting both the libraries and running an apples-apples comparison on one of your designs. I found with Stratix and V2 Pro that our designs produced similar results - one came out a little smaller and one a little faster honestly I can't remember which. It turned out for us that since the results were similar enough, price was the deciding factor. Chris "Simon Peacock" <nowhere@to.be.found> wrote in message news:<414b7c0d$1@news.actrix.gen.nz>... > Seriously... when are you planning to build? or are you after a one off... > If its not been in the market a year its not worth trying to buy them yet! > Only those in beta and those ordering thousands have any likelihood of > seeing any. So its not what features they have got... but what features > that you need that's important. We still use Spartan 2E's at work... why go > to Spartan 3 or vertex if you don't need them ??? > > Simon > > > "Tim Michaels" <tkellis4520@yahoo.com> wrote in message > news:f3b2aaca.0409170912.4d645c36@posting.google.com... > > Although I have not posted yet to this group, I have an FPGA question. > > > > I am doing an evaluation of the Stratix II and the Virtex 4. Does > > anyone have any comparisons or experience of the features, > > performance, etc. of the two devices? I am trying to understand the > > tradeoffs of the two different platforms.Article: 73299
Tim Michaels wrote: > Although I have not posted yet to this group, I have an FPGA question. > > I am doing an evaluation of the Stratix II and the Virtex 4. Does > anyone have any comparisons or experience of the features, > performance, etc. of the two devices? I am trying to understand the > tradeoffs of the two different platforms. While I assume the silicon to be similar, I expect the tradeoff to be in the development tools. Both have free web versions. For the reason of a colleague showing me Altera tools, I'm stuck with them and I didn't have the two weeks to have a look at the others. A comparing report about the tools would be appreciated. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
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