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I'm using EPM7128S now.Some of the outputs connect to a Darlington array which controls some relays. So I want to know the exact state of these outputs during the Power-up.But the datasheet of max7000s doesnt mention it. Somebody tell me the voltage of I/Os is uncertain before the POR completed.Then how can I control them before the device running properly? -- Sent by lance.work from gmail piece from com This is a spam protected message. Please answer with reference header. Posted via http://www.usenet-replayer.comArticle: 73176
On 14 Sep 2004 17:47:17 EDT, "Brannon King" <bking@starbridgesystems.com> wrote: >Once upon a time I saw a number that told me what percentage of my project >was unconstrained. I can't seem to get TRCE (Xilinx ISE) to show me that >number again. Can someone point me in the right direction? For the command line version of trce, it is the -u option Philip Philip Freidin FliptronicsArticle: 73177
On 14 Sep 2004 13:10:56 -0700, wpiman@aol.com (MS) wrote:
>We are using the trial version of the OPB Uart 16550 in one of our
>designs. We are running this at 19200,8,N,1, no flow control. We are
>using Hyperterminal- and we are able to access the UART ok for generic
>stuff. Print/scan.
Since your problems seem to be HyperTerminal related, I will
mention that in the past I have used CRT from Van Dyke software,
and been quite pleased. It cost about $35 for a single license,
which is probably far les than the cost of any more time wasted
on Hyperterminal.
http://www.vandyke.com/
===================
Philip Freidin
philip.freidin@fpga-faq.com
Host for WWW.FPGA-FAQ.COM
Article: 73178"Brannon King" <bking@starbridgesystems.com> wrote in message news:ci7ot5$e7q@dispatch.concentric.net... > Once upon a time I saw a number that told me what percentage of my project > was unconstrained. I can't seem to get TRCE (Xilinx ISE) to show me that > number again. Can someone point me in the right direction? > trce used to report % of paths covered at the bottom of the .twr report, but that seems to have disappeared between trce v5.x to v6.x. It was a misleading number anyway becasue it included paths that could not be constrained, so 100% was not possible. Maybe that's why they quit reporting it. But, as Philip said, the trce -u option will report your unconstrained paths.Article: 73179
Symon, Yes. That is a real improvement in V4 to be able to use global clock nets for something other than global clocks. Austin Symon wrote: > Hi Vic, > So you can route clock enables on these V4 global nets? That'd be good. As > for resets, fair enough, provided you're not talking about asynchronous > ones! > cheers, Syms. > "Vic Vadi" <vic.vadi@xilinx.com> wrote in message > news:4147858D.C40A8281@xilinx.com... > >>>Indeed, when I saw that there are 32 global clocks in V4, my heart sank. >>>Unlike Igor, I'm sick and tired of fixing shoddy designs that are the > > result > >>>of inexperienced designers throwing as many clocks as possible at their >>>designs. Go synchronous, young man! >>>Cheers, Syms. >> >>Part of the reasoning behind having 32 global clock buffers is that >>customers may want to route other high fanout nets such as resets >>and clock enables on global clock buffers. (The value of this >>depends on your design style ofcourse) >> >>- Vic >> > > >Article: 73180
Vic, Thanks for clarifying that: it wasn't clear from the presentations, so I was incomplete in my answer. Austin Vic Vadi wrote: >>>Several times in the past I bumped into the 8 global clocks limitation on >>>Virtex II. That's why I was very exited to hear that I can use up to 32 >>>global clocks, but after reading the Virtex 4 User's guide (page 21) my >>>excitement cooled down a bit. There is a statement: "However, only eight >>>different clocks can be driven in a single clock region. A clock region is a >>>branch of the clock tree consisting of eight CLB rows up and eight CLB rows >>>down. A clock region only spans halfway across the device." >>>If I understand this correctly, there is still a limitation of 8 global >>>clocks per device, that means max. of 8 different and completely unrelated >>>clocks can be used in all regions of the chip? Please, tell me I'm wrong? ;) > > > Actually you are wrong. Virtex 4 has several different clock regions. > An LX25 for example has 12 different clock regions. Each of those > 12 clock regions can only get 8 global clocks, but those 8 clocks > in each of those 12 regions can come from any of the 32 > global clock buffers. Plus you also get 2 regional clocks in each > clock region for Source-Synchronous type applications. > > Enjoy, > - VicArticle: 73181
Jim, Afraid not. Still limited in the DCM mux to the clock trees, I think it still is only 4 outputs from a single DCM. But you could use all DCMs from the same clock, and generate a lot of phases. Don't think you could get to 32 of them, but perhaps more than 24. Now you couldn't use them all in one place. Still need CLKFB connections from BUFGs, as well as something to get to all the inputs of all of the DCMs.... And the jitter is still there on all of them, so you would have 24+ some phases fuzzily distributed (but accurately placed over time) thoughout the period. Not sure why anyone would want to do that, but..... Austin Jim Granville wrote: > Vic Vadi wrote: > >>>> Several times in the past I bumped into the 8 global clocks >>>> limitation on >>>> Virtex II. That's why I was very exited to hear that I can use up to 32 >>>> global clocks, but after reading the Virtex 4 User's guide (page 21) my >>>> excitement cooled down a bit. There is a statement: "However, only >>>> eight >>>> different clocks can be driven in a single clock region. A clock >>>> region is a >>>> branch of the clock tree consisting of eight CLB rows up and eight >>>> CLB rows >>>> down. A clock region only spans halfway across the device." >>>> If I understand this correctly, there is still a limitation of 8 global >>>> clocks per device, that means max. of 8 different and completely >>>> unrelated >>>> clocks can be used in all regions of the chip? Please, tell me I'm >>>> wrong? ;) >> >> >> >> Actually you are wrong. Virtex 4 has several different clock regions. >> An LX25 for example has 12 different clock regions. Each of those >> 12 clock regions can only get 8 global clocks, but those 8 clocks >> in each of those 12 regions can come from any of the 32 >> global clock buffers. Plus you also get 2 regional clocks in each >> clock region for Source-Synchronous type applications. > > > So, supposing someone wants to create a 'phased array' of clocks, > to push their time-resolution well below the 1/clock, ( as in other > threads ) what is the practical limit in Virtex-4, for the number of DCM > controled phases that can be generated, AND dispersed thru the chip ? > ( IIRC earlier DCM's had just 4 phases ). > Can each of the 32 global clock buffers be driven to +1/32 phase > advance, for example ? > > -jg >Article: 73182
IgI, Soon on the CD's. As I have said before, I am not in the software division, so I just do not know. We have advanced copies, and I am told I get my updates by next week, which means the builds are ready to roll, and CDs are ready to be burnt after that. I did not take your comments as criticism. I just want to know what you use all those clocks for! If it was me, I would tell someone that having four separate processors, each with their own clock source, is not good system engineering! I would have a master clock generator with four phases, one for each processor (to spread out the RF noise, and make bypassing and SSO's easier). Vic's corrections also help, as you may now use a global clock as a clock enable, making synchronous design easier to implement. Not sure if synthesis can take advantage of this new feature, however. Have fun! Austin IgI wrote: > Hi! > > My points exatly General Schvantzkoph. In a majority of designs 8 is more > than enought, but in cases, when you have to interface with 4 different CPUs > each running in it's own clock domain, you have 4 independent DDR channels > (1-2 variable shifted clocks per channel), 2 ZBTs, USB and Ethernet > interface, 1 or 2 ChipscopePro cores for debugging. Then you also have a > system clock (which is used in 80% of the design) all that on the same > chip,... then you are running out of IOs, out of BRAMs, out of clocks, out > of everything. That's why you need to cross the regions... And on top of > this, SI issues, different IO standards and voltage levels sometimes forces > you use IOs in other banks... And at the end location of other devices on > PCB, which are connected to FPGA also forces you to use IOs you normaly > wouldn't. Some would say use bigger chip. Of course this could be a > solution, but a very expensive one, because price is also a major factor. By > using bigger chip (with more IOs) I would have to use 12 layer PCB instead > of 10, PCB would be bigger, I had to redesign the cooling solution. All this > would result in a more expensive product. > > Austin, It was not my intension to criticize your desicions, I just wanted > to clear this matter. And If I had ISE 6.3 installed on my machine, I > wouldn't ask this, instead I would try to figure this out by myself. Anyway, > when can we expect CDs with ISE 6.3 to arrive? > > Regards, > Igor Bizjak > > "General Schvantzkoph" <schvantzkoph@yahoo.com> wrote in message > news:pan.2004.09.15.00.25.27.975530@yahoo.com... > >>There are lots of situations where you need multiple clocks. If you >>are interfacing to a number of devices that each have their own clock you >>need a separate clock for each of them. Even if the devices are all using >>the same source clock their output clocks (for clock forwarded interfaces) >>are all phase shifted by an indeterminate amount so they have to be >>treated as asynchronous. I typically capture each device's data in an >>async FIFO and then transfer it into a primary clock domain. The great >>majority of the slices are in the primary domain so the device is mostly >>synchronous but there is still a need for a large number of clocks. >> > > >Article: 73183
Vivek, What do you define as 'accurate'? The CLK2X is exactly 2X the frequency (as it is generated by the use of the delay line taps). The CLK2X output has 2X the jitter of the CLK0 output (because it has to make decisions on both edges of the incoming clock, so jitter is doubled). The CLK2X output is in phase with the CLKIN and the CLK0 (every other edge). Austin Vivek wrote: > Hi, > > I was wondering how accurate the clock2x of the VIRTEX 2 FPGA was. I wanted to multiply 60 MHz by two using the clock2x in order to generate a 120 MHz clk for my logic. Has anyone had experience using this and has it worked well?Article: 73184
u722534179@spawnkill.ip-mobilphone.net wrote: > I'm using EPM7128S now.Some of the outputs connect > to a Darlington array which controls some relays. > So I want to know the exact state of these outputs > during the Power-up.But the datasheet of max7000s > doesnt mention it. > Somebody tell me the voltage of I/Os is uncertain > before the POR completed.Then how can I control them > before the device running properly? By having external pull-ups or pull-downs. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 73185
Hi out there; I'm generating 49.152 MHz from 40MHz osc using 2 DCMs first does 24/25 & second does 32/25. This generally works, but sometimes doesn't! I've not used the DCMs' clkfb input as only one clock is used in the whole FPGA, the 49.152. The clkfb of both is tied to gnd. Should I feed the DCM 1 o/p back to its clkfb & similarly for DCM 2, or what exactly? Will this give better functionality? Any commentsd please TIA Niv.Article: 73186
Hi everyone, I am fairly new to VHDL and had several questions about types conversions that I've numbered for easiness of separating them. Any help would be greatly appreciated. I am using signed type throughout my program. Now, there is one third party function that outputs std_logic_vector, that I have to use. The function looks like its std_logic_vector signal is in signed format (the sine wave with positive and negative values). 1. Can I just assume that it's in 2's compliment format similar to signed? In other words, how does STD_LOGIC_VECTOR holds signed numbers? 2. I understand that if I would like to match it to my internal signals, I would have to cast that signal to SIGNED. So, can I do SIGNED(STD_LOGIC_VECTOR signal) to do that? What would be the result of the above statement? Would it take the signal inside and convert it to 2's comliment? That would be useless for me if the signal is already in 2's compliment. If that's not correct, please let me know how can go around this. 3. I suppose STD_LOGIC_VECTOR can hold any format (1's, 2's or just magnitude) as long as you keep in mind in which context you are using it. However, the moment you start using SIGNED function, how does VHDL compiler recognize the numbers from then? Does it still treat them as STD_LOGIC_VECTOR and 'makes a note' for itself that it contains 2's compliement? 4. I've read that ieee.std_logic_arith and ieee.numeric_std are mutually exclusive libraries that you cannot use at the same time. Maybe using one or another one would somehow answer my questions above.. Big thanks in advance! KofeyokArticle: 73187
Austin Franklin wrote: > > "Mark McDougall" <markm@vl.com.au> wrote in message > news:41451b41$0$22790$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > > Austin Franklin wrote: > > > > > I need some help with something. Someone made some technical claims > > > that I am questioning are correct or not ;-), and would like to see > > > what you guys think about these claims: > > > > Homework? > > Not really. Yeah Austin, get your homework done and don't make me tell you again! ;) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73188
sebastian wrote: > > hi, > > im supposed to evaluate the same design in both altera and xilinx > devices, the problem is that altera's software seems a bit "unusual" > and doesnt understand code that all others synthetisers i've tried > recognise. > > first i was having trouble with RAMs, but i solved that following > quartus II handbook coding guidelines (though i had to change several > files...and i dont like when that happens...specially because i'll > have three versions, one for each fpga family and then another for > asic!!) When it comes to memory, it can be hard to infer it in a way that is compatible with multiple hardware platforms. I use the GENERATE feature of VHDL to provide separate memory descriptions depending on the particular chip I am targeting. That way the same files are used for each different target, you just change the flag telling the software which chip to target. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73189
Hi, > It really interest me how is the Xilinx Real PCI exprress > working - there is nothing mentioned about the need of > external PLL but without it can not work?? Your assertion is false. There is nothing in the PCI Express specification that requires you use a distributed reference clock. It's present in some form factors, but not all. When it's present, you might view it as a "convenience". You can use a distributed reference clock with a PLL if you want. But you'll have to convert from 100 MHz to 125 MHz and "clean it up" so that it meets the frequency and +/- 100 ppm requirements of the Virtex-II Pro transceiver blocks. You can also use a local 125 MHz oscillator that is +/- 100 ppm. EricArticle: 73190
Niv, Have you made sure the first DCM holds the second DCM in reset until the first DCM asserts LOCKED? Syms. "Niv" <niv.nospam.goaway@ntlworld.com> wrote in message news:V3%1d.124$QF4.27@newsfe2-win.ntli.net... > Hi out there; > I'm generating 49.152 MHz from 40MHz osc using 2 DCMs > first does 24/25 & second does 32/25. > > This generally works, but sometimes doesn't! > > I've not used the DCMs' clkfb input as only one clock is used in > the whole FPGA, the 49.152. The clkfb of both is tied to gnd. > > Should I feed the DCM 1 o/p back to its clkfb & similarly > for DCM 2, or what exactly? Will this give better functionality? > > Any commentsd please > > TIA Niv. > >Article: 73191
I can not find a way to lauch the ISE text editor or MTI HDL editor in the standalone mode. Does anyone how to do it. I want to view the .v and .vhd file using syntax highlight, but not necessary want to launch the Project Navigator or MTI simulator everytime I double click on one of .v/.vhd file. Thanks CharlesArticle: 73192
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:414883D3.DA14B4DC@yahoo.com... > Austin Franklin wrote: > > > > "Mark McDougall" <markm@vl.com.au> wrote in message > > news:41451b41$0$22790$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > > > Austin Franklin wrote: > > > > > > > I need some help with something. Someone made some technical claims > > > > that I am questioning are correct or not ;-), and would like to see > > > > what you guys think about these claims: > > > > > > Homework? > > > > Not really. > > Yeah Austin, get your homework done and don't make me tell you again! > ;) Good grief, Rick...I haven't done *real* homework in near 30 years! Regards, AustinArticle: 73193
You might be able to generate something close enough in a single DCM. What is more important to your application, a precise frequency or minimum jitter? How accurate do you need the 49.152 MHz clock? In general, using the CLKFX from the first DCM cascaded to the second DCM is not recommended, due to the amount of output jitter from the first DCM. Here are a few examples. (M/D)=16/13 generates 49.23077 MHz, a 0.160% difference. Peak-to-peak jitter 1.14 ns. (M/D)=27/22 generates 49.09091 MHz, a -0.124% difference. Peak-to-peak jitter 1.43 ns. (M/D)=11/9 generates 48.88889 MHz, a -0.535% difference. Peak-to-peak jitter 1.02 ns. If you use the DCM's CLK0 output as feedback, then the CLKFX output and the input clock are phase aligned every M*D clock cycles. See also page 54 and on in XAPP462 (http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf). --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "Niv" <niv.nospam.goaway@ntlworld.com> wrote in message news:V3%1d.124$QF4.27@newsfe2-win.ntli.net... > Hi out there; > I'm generating 49.152 MHz from 40MHz osc using 2 DCMs > first does 24/25 & second does 32/25. > > This generally works, but sometimes doesn't! > > I've not used the DCMs' clkfb input as only one clock is used in > the whole FPGA, the 49.152. The clkfb of both is tied to gnd. > > Should I feed the DCM 1 o/p back to its clkfb & similarly > for DCM 2, or what exactly? Will this give better functionality? > > Any commentsd please > > TIA Niv. > >Article: 73194
"Austin Lesea" <austin@xilinx.com> wrote in message news:ci78v6$ce41@cliff.xsj.xilinx.com... > Antti, > > The MGT's are designed to address the same standards as V2 Pro and V2 Pro X. > > That said, the ppm frequency shift of SATA when using spread spectrum > clocking (0 to -5000 ppm)is not addressed. hm, I am actually looking for +-300ppm lock :) i.e. SATA or PCIe without spread spectrum. PCIe has also spec +-300ppm, but I think the only way to use PCIe is to use external PLL IC, same way Nital is doing on their boards. Its funny that RocketIO seems to be the worst MGT from all 1) Altera Stratix GX has special PLL that is ok to be used, ie Altera can handle PCIe without external PLL 2) Lattice has +-300ppm clock range RocketIO has +-100ppm and can not use DCM for refclock as far as I know, or does there exist a solution to use DCM in the PCIe application? It really interest me how is the Xilinx Real PCI exprress working - there is nothing mentioned about the need of external PLL but without it can not work?? Thanks for any replies AnttiArticle: 73195
Yes, DCM1 lock output is used as the reset for DCM2 (inverted,a s it needs to be). "Symon" <symon_brewer@hotmail.com> wrote in message news:2qrh6lF135k4mU1@uni-berlin.de... > Niv, > Have you made sure the first DCM holds the second DCM in reset until the > first DCM asserts LOCKED? > Syms. > "Niv" <niv.nospam.goaway@ntlworld.com> wrote in message > news:V3%1d.124$QF4.27@newsfe2-win.ntli.net... > > Hi out there; > > I'm generating 49.152 MHz from 40MHz osc using 2 DCMs > > first does 24/25 & second does 32/25. > > > > This generally works, but sometimes doesn't! > > > > I've not used the DCMs' clkfb input as only one clock is used in > > the whole FPGA, the 49.152. The clkfb of both is tied to gnd. > > > > Should I feed the DCM 1 o/p back to its clkfb & similarly > > for DCM 2, or what exactly? Will this give better functionality? > > > > Any commentsd please > > > > TIA Niv. > > > > > >Article: 73196
I need accurate frequency, I'm using a 2 ppm osc as source and need to maintain that. I shall try connecting the clk0 back to clkfb, Thanks. The final choice is to get an accurate osc at the needed freq! "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:cia7ik$kho1@cliff.xsj.xilinx.com... > You might be able to generate something close enough in a single DCM. What > is more important to your application, a precise frequency or minimum > jitter? How accurate do you need the 49.152 MHz clock? In general, using > the CLKFX from the first DCM cascaded to the second DCM is not recommended, > due to the amount of output jitter from the first DCM. > > Here are a few examples. > > (M/D)=16/13 generates 49.23077 MHz, a 0.160% difference. Peak-to-peak > jitter 1.14 ns. > > (M/D)=27/22 generates 49.09091 MHz, a -0.124% difference. Peak-to-peak > jitter 1.43 ns. > > (M/D)=11/9 generates 48.88889 MHz, a -0.535% difference. Peak-to-peak > jitter 1.02 ns. > > If you use the DCM's CLK0 output as feedback, then the CLKFX output and the > input clock are phase aligned every M*D clock cycles. > > See also page 54 and on in XAPP462 > (http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf). > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/II/IIE FPGAs > http://www.xilinx.com/spartan3 > --------------------------------- > Spartan-3: Make it Your ASIC > > "Niv" <niv.nospam.goaway@ntlworld.com> wrote in message > news:V3%1d.124$QF4.27@newsfe2-win.ntli.net... > > Hi out there; > > I'm generating 49.152 MHz from 40MHz osc using 2 DCMs > > first does 24/25 & second does 32/25. > > > > This generally works, but sometimes doesn't! > > > > I've not used the DCMs' clkfb input as only one clock is used in > > the whole FPGA, the 49.152. The clkfb of both is tied to gnd. > > > > Should I feed the DCM 1 o/p back to its clkfb & similarly > > for DCM 2, or what exactly? Will this give better functionality? > > > > Any commentsd please > > > > TIA Niv. > > > > > >Article: 73197
Hello I'm nev on this group and have following problem. I need to program EPM7064SLC44 using JTAG cable (ByteBlasterII) and Quartus 4.1 and it doesn't work Auto detection does not work either. When i connect EPM7128SLC84 all works, so cable and software is OK. I tried different chips (EPM7064SLC44 ones with different speed grades) and all don't work. i connected scope and TDI,TMS and TCK signals seems to be ok, but there is no TDO signal... Does anybody had similar problem? maybe there is something wrong with quartus? I used altera 7000 series chips and never had any problems (but never used 7064 one) Thanks for response Regards GregArticle: 73198
Hi,
The body of this message is about Virtex-II Pro,
and not about Virtex4, as the subject suggests.
I don't want anybody to get confused.
The original post didn't mention compliance.
You simply asserted the need for an external PLL.
That is false.
Virtex-II Pro transceivers require +/- 100 ppm
on the externally supplied 125 MHz reference clock.
The PCI Express 1.0a spec requires components to
generate and tolerate +/- 300 ppm on the unit
interval (UI) which is undoubtedly derived from
a reference clock.
Also note that the Virtex-II Pro transceiver uses
a 125 MHz reference clock, while one implementation
of PCI Express systems provide a 100 MHz reference
clock. The PCI Express 1.0a physical layer specs
don't make any mention of required reference clock
frequency. You might find some future form factor
providing an entirely different reference clock
frequency -- or perhaps none at all (e.g. a cable
based PCI Express system...)
The "quality" of what arrives at the Virtex-II Pro
receiver and the ability of the CDR to recover the
clock and the data is a separate topic not directly
related to this +/- 100 ppm requirement (although I
am sure the quality of the reference clock to the
Virtex-II Pro does have some effect on CDR...)
> using an non locked to PCIe reference clock
> local oscillator for MGT reference will not
> be working solution as the MGT will never get
> initial lock.
Untrue.
If both use the distributed reference clock, you
have a synchronous system. The transceivers will
lock, and the elastic buffers in the devices on
both sides of the link will remain half-full.
This is because everything is running from the
same clock.
If you use independent (local) reference clocks which
result in bitrates close to each other (e.g. +/- 300
ppm) you have a pleisochronous system. The transceivers
lock, and the elastic buffers in the devices compensate
for the difference in bitrate by dropping or adding
symbols in the data stream. In PCI Express, this
clock compensation mechanism is part of the spec and
designed to handle up to a total of 600 ppm difference
(one device at -300 ppm, the other at +300 ppm).
If you're using Virtex-II Pro with a +/- 100 ppm
reference clock, you'll be fine because the total
difference can only reach 400 ppm. Also, for any
given device, it does not matter what reference
clock frequency is required, what matters is that
the bittime (UI) is +/- 300 ppm.
> As much as I know DCM's (in V2Pro at least) are
> no suitable for MGT reflock
That is correct. You need to use the BREFCLK clock
inputs. And, for the reference clock, you can use:
1. Local 125 MHz +/- 100 ppm reference clock.
2. Distributed reference clock, multiplied by
1.25, and cleaned up to +/- 100 ppm.
I hope that makes sense. Sometimes I get dizzy
reading the spec!
Eric
Article: 73199kofeyok wrote: > > Hi everyone, > I am fairly new to VHDL and had several questions about types conversions > that I've numbered for easiness of separating them. Any help would be > greatly appreciated. > > I am using signed type throughout my program. Now, there is one third > party function that outputs std_logic_vector, that I have to use. The > function looks like its std_logic_vector signal is in signed format (the > sine wave with positive and negative values). 1. Can I just assume that > it's in 2's compliment format similar to signed? In other words, how does > STD_LOGIC_VECTOR holds signed numbers? > > 2. I understand that if I would like to match it to my internal signals, I > would have to cast that signal to SIGNED. So, can I do > SIGNED(STD_LOGIC_VECTOR signal) to do that? What would be the result of > the above statement? Would it take the signal inside and convert it to 2's > comliment? That would be useless for me if the signal is already in 2's > compliment. If that's not correct, please let me know how can go around > this. > > 3. I suppose STD_LOGIC_VECTOR can hold any format (1's, 2's or just > magnitude) as long as you keep in mind in which context you are using it. > However, the moment you start using SIGNED function, how does VHDL > compiler recognize the numbers from then? Does it still treat them as > STD_LOGIC_VECTOR and 'makes a note' for itself that it contains 2's > compliement? > > 4. I've read that ieee.std_logic_arith and ieee.numeric_std are mutually > exclusive libraries that you cannot use at the same time. Maybe using one > or another one would somehow answer my questions above.. I understand your confusion. Types and type conversion is possibly the hardest part of learning VHDL. I can't say I am an expert, but I have written many apps in VHDL and I think I have a handle on this. std_logic_vector (slv) makes no assumptions about the data that is being conveyed by the type. The ieee.numeric_std library defines a signed and unsigned type that support vectors of std_logic, but *do* make assumptions of the type of numbers they are being used to represent. Otherwise, I believe these three types are the same. This makes a difference only when you are doing operations that rely on the nature of the number type. If you are just calculating parity, then you don't care if it is signed or unsigned. My recommendation is to convert (not cast) the type when you need to change it. This will be supported by the ieee.numeric_std library for most conversions you will want to do. to_signed() will convert an slv to a signed type. TO_STDLOGICVECTOR() will convert back. I believe I am using a custom package to convert using "to_slv" possibly just because it is less typing, but I believe I can convert directly from integer to slv. Check the description of your library. The ieee.std_logic_arith is not an IEEE library at all. Likewise with IEEE.STD_LOGIC_UNSIGNED and IEEE.STD_LOGIC_SIGNED. Worst of all, the unsigned and signed libraries are mutually exclusive unless you explicitly identify which library you are using on each conversion function. So you can't use both signed and unsigned types in the same program without difficulty. I suggest that you stay away from these. Below are the common libraries I use. Library ieee; Use ieee.std_logic_1164.all; Use ieee.numeric_std.all; -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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