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"lance.work@gmail.com" <u722534179@spawnkill.ip-mobilphone.net> wrote in message news:l.1095341029.1826843261@[221.217.196.69]... > > I'm using EPM7128SLC84 now. > Since some of the outputs is connected to > Darlington arrays controling relays. > So I want to know the exact state of these I/Os before > power on reset(POR) complete. > > Also,if the I/O voltage is uncertain ,how can I control > it? What should I do? > Probably it tristates it pins during power up, so to control the level, use a pull-up or pull down resistor. I guess the problem is that the relays are energized briefly during powerup? JeroenArticle: 73301
Steven K. Knapp wrote: > You may be able to remove the user reset completely. Is your user reset > only to guarantee the initial state of the design (a common ASIC practice)? > If so, you can eliminate this reset signal, which will potentially make your > design significantly smaller. > > Xilinx FPGAs have an internal Global Set/Reset signal that is asserted at > the end of the configuration process, guaranteeing the initial conditions. This can't be good advice. I have a co-worker who does that often, and I get to write drivers for the resulting chips. It bugs me a lot. Using the configuration process to initialize things to a safe startup state is nice and all (especially for "roms" and the like) but RESET is *not* the same thing. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 73302
Tuukka Toivonen wrote: > Hi all. I'm looking for FPGA for real-time video processing. > The requirements are not yet fixed, but I think something > like Xilinx Virtex-II Pro from XC2VP7 to XC2VP30 would be > a good choice. PCI interface would be nice so that I could > plug the card in and transfer uncompressed video frames into > the card and get compressed frames back. Something like, > say 100 Mbit/s Ethernet, might also work but then it would > use pretty much all of the bandwidth. How much do you want to spend? We actually have a board we are working on that has all these goodies, plus camera link, sdram, and a PPC. But I think you'd be looking at a few (a small few?) thousand dollars:-/ > Also, I want to do development on Linux (Debian) host, > so the tools should run on that. Running Linux on the > FPGA PowerPCs sounds like a nice idea too. I know that Xilinx paid-for tools work on a variety of Linux distributions. Heck, I'm running 'em on an AMD64. > My question is: what hardware and software do I need? > Looks like I need: > - The development board. Prospective candidates are > Alpha Data's ADM-XPL and Amirix boards. Something > from Avnet might also do, except that it appears > they don't support Linux. Not sure about Alpha Data > either. And then there's Xilinx's > ML310 which appears to be a complete computer with > PCI slots and Ethernet. But it might have some bandwidth > problems, unless I connect camera directly into the > PCI slots in the board. What sort of camera? > - Hardware development tools. Are there other alternatives > than ISE Foundation/BaseX? And are there differences > between the two except that the latter supports > devices only up to XC2VP7? > - Software development tools. Should I get them from the > board vendor or is it possible to use them from third > party? I have found EDK from Xilinx and the TimeSys SDK. > What is the difference between the two? Other alternatives? Even the PPC of the Virtex-IIPro can be targetted via the GNU toolchain. MonteVista has complete V2P solutions, and Denx.de has an ELDK that can readily target V2Pro. > - Operating system for the PowerPC inside the FPGA. Does > this come with the development kits or would I need > to get one separately? linuxppc should work. Porting Linux to a V2P requires some software savvy because of the "unconstrained flexibility" of the solution. Personally, I'm happier with a standard PPC405 external, but hey... > - Something else? > > I hope the questions were not too silly, but I haven't > done any work with FPGAs before. The scope of what you are talking about is significant for a first time FPGA designer! -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 73303
"John_H" <johnhandwork@mail.com> wrote in message news:<L642d.14$l1.2394@news-west.eli.net>... > To make a complete system, what do you have/want for the system clock? Is > there a need for an on-board oscillator? > > What about power? Are you supplying a predetermined external fixed voltage? > An external voltage to satisfy the FPGA? Several external voltages to match > the FPGA's every whim? > > Are you expecting your I/O to be 5V tolerant/compatible? > > These questions and perhaps a few more might be needed to get the fully > working board. > > Another thought might be to get a TQFP prototyping board (or adapter) and > wire together your own regulators, bypass, and frequency sources. There are > 100 pin TQFP packages that are pretty small - the support stuff might take > up the most room. Yeah, I need an onboard oscillator running at a minimum of 4 MHz. Power is going to be coming from two fixed external sources, one at 3.43V and another at 5V. Where would I be able to find one of these TQFP proto boards? They sound interesting. Thanks. -Darien G.Article: 73304
Hi Andre, I presume because you've posted this to CAF you're writing this code for synthesis. In that case you should really be thinking about what you want synthesised. In your C algorithm, a number X is stored in a memory location somewhere. When it's incremented, the CPU or whatever fetches the value, adds one, and writes it back. Now, in the synthesised version, the number X is actually implemented as a piece of hardware. In your FPGA there's a 5 bit counter, which increments when it gets a clock. Do you see the fundamental difference? You need to code for this hardware. For a start, looking at your verilog code, where's your clock? Good luck mate, Syms. "Andre Bonin" <Yoyoma_2@[at-]Hotmail.com> wrote in message news:5KP2d.38134$%S.33263@pd7tw2no... > Hey all, I'me trying to convert a C algorithm to Verilog using Quartus > II Web edition. > > The following for loop doesn't compile because it says its not of > constant loop time. > > What i really need is to be able to calculate the loop time "on the fly". > > Can VHDL or Verilog do this? or is this a limitation? > > > Thanks > Error: Verilog HDL For Statement error at XXXXXXXX.v(49): must use only > constant expressions in terminating conditions > > ---- Error at while loop - > integer X = 0; > always > begin > while( X < 30 ) > begin > X = X + 1; > end > endArticle: 73305
i just tried with another programmer - ByteBlasterMV and Max+PlusII and problem is exactly the same..it works with all the chips except EPM7064SLC44 i gave up with it and ordered EPM3064A, but it would be goot to know what is going on. any idea? regards Greg -- ---------------------------------------------------------------------------- ------------------------------ Grzegorz Kasprowicz, AB Department, CERN, CH-1211 Geneva 23 office: 37 R-004, phone: +41 22 76 72584, fax: +41 22 76 78200 mailto: Grzegorz.Kasprowicz@cern.ch "Grzegorz Kasprowicz" <Grzegorz.Kasprowicz@cern.ch> wrote in message news:cie834$gj4$1@sunnews.cern.ch... > > > > You have the required pullups and pulldowns ? > > 1k up for TMS, TDI and TDO and 1k down for TCK. > > Plus there is whealth of pins that require a fixed connection. > > Documented in the *.RPT file as ASCII. > > > > > Yes, i have all pullups and pulldowns, all signal except TDO look good, i > mean levels. > All grounds and supplies are also OK. > Anyway instead of solving problem, i will change logic family to MAX3000A, > which better suits my needs (3.3V) > >Article: 73306
Hello all :) I'm doing back annotated simulation in ModelSim 5.6e with at94k_ver library(Atmel AT94K FPSLIC). Clock signals can't pass through the input buffers, the output of the ibuf module is "don't care" in ModelSim waveform viewer...Clock frequency is below the design's maximum frequency. Can anybody tell me what's wrong?Article: 73307
Hello I need to implement gigabit ethernet link in device that is equipped with Cyclone 1C6 FPGA. i found one solution that fits my needs : to use PCI master and Realtek RTL8069SB in 32 bit mode. Additional advantage is that it is in PQFP package. I didn't wanted to use PHY chip and do all in FPGA because i have about 4000LE left, and don't want to implement all TCP/IP stack. This RTL chip does most of the work, segmentation, CRC, etc.. but have PCI interface and i would have to implement PCI master in FPGA. so i'm looking for non-pci single chip solution like LAN9C111 from SMSC, but with gigabit speed. I was looking for SIERRA controllers, but they seem to not have support for TCP/IP stack and requires 2 chips. Regards GregArticle: 73308
>Increment is usually done by setting the carry in to 1. >In the case of a ripple carry adder, it can be done with a >chain of half adders, instead of full adders. I think that >makes it twice as fast, 32 gate delays instead of 64. Is that true on FPGAs? I'd expect that half and full adders would use the same carry chain, generally dedicated logic. So the speed would be the same. Even if you build your own adder logic, is gate delays the right unit? I'd expect LUT delays, and most LUTs are big enough to contain a whole adder so that will be the same speed as a half adder. (maybe off by a few ns to get started) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 73309
Hi folks- I was wondering if it is possible to reconfigure a Spartan 3 during operation without losing the BRAM contents or overwriting it. Is this possible with other FPGAs? Column-wise reconfiguration, would work, I suppose. JakeArticle: 73310
Austin Lesea <austin@xilinx.com> writes: > See my other posting today. Okay, so, it appears that my argument became invalid about a week ago when the Virtex4 shipped. My apologies for this. But at the same time, so did the argument "we can't document the bitstream because it will compromise customer design security".... So, what is the current reason for not publishing the bitstream format? > And, you are correct, we have no NVRAM in our FPGA devices right I was probably a bit too specific there; I meant any sort of customer-writable memory that doesn't get cleared when you take away the main power supply to the device. The battery-backed memory for storing a customer-specific decryption key is close enough -- in fact, this is what Dallas Semico uses (rather than flash or some other zero-current storage). I'm quite happy to see this; unlike previous schemes, this is something I would actually trust. A customer-specific (or design-specific) key is definately the only way to go for any sort of real security. - aArticle: 73311
Austin Lesea <austin@xilinx.com> writes: > no power on surge in the core, This sounds interesting; I didn't notice it on the Xilinx site... do you have a link with more information? - aArticle: 73312
Please help me find the source of this glossary. This is taken from a fraudulent book, which has plagiarised the glossary from some unnamed source plagiarising in apparently violation of the ethics of publishing. I don't think this is available as an online resource. It might be some book. I am giving here some entries beginning with the letter "H". If anybody can find the source please let me know. Hard copy- Printed or filmed-output from a computer device in human readable form. Hard disk- A rigid magnetic disc such as the internal disks used in system units of personal computers and in eternal hard disk drives, Hard Disk Cartridge A cartridge which contains a rigid disk which is designed to be loaded and unloaded into a hard disk system. Hard sector A sector that is established physically on a disk. Hard space A space represented by a special character in a string. Hardware The physical components of a computer system \such as electronic, magnetic and mechanical devices. Hardware panning A video adapter feature that enables it to stimulate a display larger than the one to which the video adapter is connected. Head A device that reads writes or erases data on a storage medium like a magnetic drum, magnetic tape etc. Helper program Few browsers come with helper programs, so users must go through the tedious process of locating the appropriate helper programs, down loading them from the internet and configure the browser to start them automatically when it encounters a multimedia file. Help Function- A feature of system which is designed to assist a user in understanding and operating the system. Heuristic A trail and error method of getting a solution to a problem. A s opposed to algorithm. Hidden file- An operating system file that is not displayed by a directory listing. Hidden line- In computer graphics, a line segment that represents and edge obscured from view in a two dimensional projection of a three dimensional object. High speed scanner work station- An image plus work station equipped with a high speed scanner that can scan large stacks of similar sized paper into the image-plus system.Article: 73313
Hal Murray wrote: (I wrote) >>Increment is usually done by setting the carry in to 1. >>In the case of a ripple carry adder, it can be done with a >>chain of half adders, instead of full adders. I think that >>makes it twice as fast, 32 gate delays instead of 64. > Is that true on FPGAs? The comment was meant to be the non-FPGA case. It may or may not be true implementing a ripple carry adder not using the carry chain in an FPGA. > I'd expect that half and full adders would use the same > carry chain, generally dedicated logic. So the speed would > be the same. The discussion of different adder designs only makes sense if you are not using the dedicated carry logic. > Even if you build your own adder logic, is gate delays > the right unit? I'd expect LUT delays, and most LUTs > are big enough to contain a whole adder so that will > be the same speed as a half adder. (maybe off by > a few ns to get started) Well, both half and full adders have two outputs, so need two LUT's. There is a real question of when it is better not to use the carry chain. The delay through the carry chain is O(n). The delay through a carry lookahead adder is O(log n), though in an FPGA the constant is somewhat larger. For some value of n a carry lookahead adder is faster, though it also uses more LUTs. (If you have unlimited gate width it is O(1), but you never have unlimited gate width without some other cost. I am not so sure it couldn't be done with Altera's cascade chain, but it would take a lot of logic.) -- glenArticle: 73314
Stephen Williams wrote: (snip) > This can't be good advice. I have a co-worker who does that often, > and I get to write drivers for the resulting chips. It bugs me a lot. > Using the configuration process to initialize things to a safe > startup state is nice and all (especially for "roms" and the like) > but RESET is *not* the same thing. I thought Xilinx FPGA's have the ability to connect reset inputs to a global reset line. That can only reset to the same state that the initial startup state is, though. -- glenArticle: 73315
Andre, I do agree with Symon, specially if you have a software background. Be careful when trying to synthesize (HARDWARE) your software. Anyway, below is an example of how to implement a while_loop in VHDL. I added some comments reagarding the conditions under which the whil_loop is implemented; library ieee; use ieee.std_logic_1164.all; entity while_ex is port( clk: in std_logic; z: out boolean); end; architecture beh of while_ex is begin -- while-loops are synthesizable as long as they have a -- valid wait statement in every possible path within the loop -- if a while-loop does not have a single wait statement, and -- it is bound by constantes, then the tool synthesized the -- design correctly process -- no sensitivity list variable x: integer range 0 to 35; begin x:= 0; wait until clk'event and clk='1'; z<= false; wh_loop: WHILE x < 30 LOOP wait until clk'event and clk='1'; x:= x+1; END LOOP; z <= true; end process; end beh; regards, cristianArticle: 73316
Hi Jake, I seem to recall you can read back the whole bitstream from Xilinx FPGAs. I think this includes the current bits in the BRAMs. If you knew which bits were which, you could extract the BRAM bits and plug them into the new bitstream you're downloading. Maybe. Cheers, Syms. "Jake Janovetz" <jakespambox@yahoo.com> wrote in message news:d6ad3144.0409181559.64fbafc6@posting.google.com... > Hi folks- > > I was wondering if it is possible to reconfigure a Spartan 3 during > operation without losing the BRAM contents or overwriting it. Is this > possible with other FPGAs? Column-wise reconfiguration, would work, I > suppose. > > JakeArticle: 73317
If you use a continuous or non-blocking assignment in Verilog and the right hand expression is something that in a real device takes time to become valid after the inputs become valid, how do you ensure the output IS valid when you want to use it? For example: input [1000:0] megaparity; assign foo = ^megaparity; always @(posedge clk) // megaparity valid on this clk saved_parity <= foo; // when is this valid? What if the cascaded xor chain is so slow it's more than one clk period? More than 20? If you assume it's slower than it is (waiting some fixed number of clocks) don't you risk having it change with the input? -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 73318
Does anyone know of a planned/released Development Board for the larger Virtex-4 parts (preferably XC4VLX100)? Google doesn't find anything. TIAArticle: 73319
http://www.fpgajournal.com/articles/20040914_virtex4.htm you could try this article "Rene Tschaggelar" <none@none.net> wrote in message news:414c3979$0$21014$5402220f@news.sunrise.ch... > Tim Michaels wrote: > > > Although I have not posted yet to this group, I have an FPGA question. > > > > I am doing an evaluation of the Stratix II and the Virtex 4. Does > > anyone have any comparisons or experience of the features, > > performance, etc. of the two devices? I am trying to understand the > > tradeoffs of the two different platforms. > > While I assume the silicon to be similar, I expect the > tradeoff to be in the development tools. > > Both have free web versions. > For the reason of a colleague showing me Altera tools, > I'm stuck with them and I didn't have the two weeks to > have a look at the others. > > A comparing report about the tools would be appreciated. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.netArticle: 73320
Ben Jackson wrote:
> always @(posedge clk)
> // megaparity valid on this clk
> saved_parity <= foo; // when is this valid?
"saved_parity" will be updated at
the next "clk", ready or not.
I hope the phrase "this clk" does
not imply that there is more than one.
> What if the cascaded xor chain is so slow it's more than one clk period?
Then static timing will fail.
> More than 20? If you assume it's slower than it is (waiting some fixed
> number of clocks) don't you risk having it change with the input?
You might synchronize foo to the system clock,
and enable the assignment only when foo is valid.
-- Mike Treseler
Article: 73321"Laurent Gauch" <laurent.gauch@DELETEALLCAPSamontec.com> wrote in message news:41493704.2050000@DELETEALLCAPSamontec.com... > Antti Lukats wrote: > > "Laurent Gauch" <laurent.gauch@DELETEALLCAPSamontec.com> wrote in message > > news:414838f8$1@news.vsnet.ch... > > > >>Hi all, > >> > >>Can I insert my own IP core in the Xilinx Core Gen? > >>Can I use Xilinx Core Gen to manage my OWN VHDL IP core? > >>If not, why Xilinx does not allow that feature. > >> > >>Larry, > >>www.amontec.com > > > > > > yes you can. > > > > well there are some problems and I guess not all the core gen funtions are > > accesible to regular non privileged users, but you can create your own > > coregen cores > > > > Antti > > > > > > Hi Antti, > > ... and how to do that ? > I am searching in xilinx doc, but found nothing usable. > > Regards, > Laurent > www.amontec.com we have done that, and the info is available too :) http://ebook.openchip.org/IP_CorePackaging.html AnttiArticle: 73322
Hello all, i'me doing a school project requiring Cyclone2 chips, but all the distributors I called (that allow single-order) have only the EP1C7's (Cyclone1's speed grade 7). And furthermore they sell it for around 300$ us (500 canadian). Am i missing something? Altera says they cost under 3$ each. I concure that yes volume pricing etc, but from 3$ to 500$ seems a rather large increase. I'me looking for the cheapest FPGA possible that will be easy to program on the fly and could multiply a 10x10 matrix. Our design does have some external ram and a PLD so System-On-Chip could be integrated into our pci board. Thanks!Article: 73323
cristian wrote: > Andre, > > I do agree with Symon, specially if you have a software background. Be > careful when trying to synthesize (HARDWARE) your software. The goal of the project is ADPCM encoding and a 10x10 integer matrix multiplication, i think that could be done within the FPGA. it would be *nice* to be able to implement any C algo within hardware but i do accept their are limitations. Though for some odd reason VHDL seems more apt and less 'picky' about these kinds of loops. Or am i being deceived? > Anyway, below is an example of how to implement a while_loop in VHDL. > I added some comments reagarding the conditions under which the > whil_loop is implemented; Thank you for this piece of code, it helps me get started and play around with VHDL. VHDL seems more 'higher level' then verilog. For this type of task, do you reccomend VHDL or Verilog? VHDL is an older standard but my work with verilog gives me the hint that its lower level. > > library ieee; > use ieee.std_logic_1164.all; > > entity while_ex is > port( clk: in std_logic; > z: out boolean); > end; > > architecture beh of while_ex is > > begin > -- while-loops are synthesizable as long as they have a > -- valid wait statement in every possible path within the loop > -- if a while-loop does not have a single wait statement, and > -- it is bound by constantes, then the tool synthesized the > -- design correctly > process -- no sensitivity list > > variable x: integer range 0 to 35; > begin > x:= 0; > wait until clk'event and clk='1'; > z<= false; > wh_loop: WHILE x < 30 LOOP > wait until clk'event and clk='1'; > x:= x+1; > END LOOP; > > z <= true; > > end process; > > end beh; > > regards, > > cristianArticle: 73324
Andre Bonin <Yoyoma_2@[at-]hotmail.com> wrote: : Hello all, i'me doing a school project requiring Cyclone2 chips, but all : the distributors I called (that allow single-order) have only the : EP1C7's (Cyclone1's speed grade 7). And furthermore they sell it for : around 300$ us (500 canadian). : Am i missing something? Altera says they cost under 3$ each. I concure : that yes volume pricing etc, but from 3$ to 500$ seems a rather large : increase. : I'me looking for the cheapest FPGA possible that will be easy to program : on the fly and could multiply a 10x10 matrix. Our design does have some : external ram and a PLD so System-On-Chip could be integrated into our : pci board. Did you consider going with Spartan 3? At nuhorizons they start at 13$45 with the XCF02 for 5$80. Spartan 3 has embedded multipliers. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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Compare FPGA features and resources
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