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Well, I've ended up using a perl script to modify a line
of code in my main include file. I have to remember to
run the script, but it's painless other than that.
I decided to use the Unix "epoch" style timestamp in the
include file. Trivial C code can decode it and it is a
simple 32 bit value to assign to a regr or wire in Verilog.
The C code to print it is like:
// 1st, you need to read the value into 'tmp32', then....
printf("Verilog build date was %s", ctime(&tmp32) );
In the include file I have:
parameter BLD_EPOCH = 32'd1090435314;
The Perl script that updates the line is:
#!/usr/bin/perl -w
#
# SET_EPOCH.PL
# script to update the BLD_EPOCH parameter in the main include file
#
# define the include file and a tmp verion of it....
my $file = "../common_v/po_include.v";
my $tmpfile = $file . "2";
my $found = 0;
my $target_string = "^\\s*parameter\\s+BLD_EPOCH\\s+=\\s+32'd";
my $epoch = time();
# open the original file for reading...
open(ORIG, "<$file") || die "couldn't open $file for reading\n";
open(NEW, ">$tmpfile") || die "couldn't open $tmpfile for writing\n";
# loop copying lines....
while (<ORIG>) {
if (/$target_string/) {
s/32'd.*$/32'd$epoch;/;
print "setting \n\t$_\n";
$found = 1;
}
print NEW $_;
}
close(NEW);
close(ORIG);
if ($found) {
rename($tmpfile, $file) || die "couldn't rename $tmpfile to $file\n";
} else {
unlink($tmpfile);
die "didn't find string /$target_string/\n";
}
I hope this amuses/helps others!
John P
Article: 71551
tns1 wrote:
> Where can I find an explanation of the prefix codes in an nm generated
> symbol table? I see entries such as 'F' which are not described in the
> standard GNU manuals.
man nm
"A" The symbol's value is absolute, and will not be
changed by further linking.
"B" The symbol is in the uninitialized data section
(known as BSS).
"C" The symbol is common. Common symbols are uninitial
ized data. When linking, multiple common symbols
may appear with the same name. If the symbol is
defined anywhere, the common symbols are treated as
undefined references.
- - -
/RogerL
--
Roger Larsson
Skellefteċ
Sweden
Article: 71552
I've attempting to select an FPGA for a new design.
The design will have 9 of the following:
12 bit latches
12 bit down counter
1 bit output latch
So one measure of the size might be 25 registers * 9 = 225 registers.
The counting freq is 15 MHz.
The latches get loaded from an existing micro. So I need a 12 input
pins for a data buss, 4 input pins for which register, a clock pin and
let's say 4 pins for control lines.
Along with the 9 output signals.
So another measure is 12+4+1+4+9 = 30 pins not counting power and
ground.
It would also be desirable to be packaged in a PLCC but TQFP in ok.
And the device should be reprogrammable using JTAG (add 4 more pins).
Voltage is not much of an issue. However 5 V tolerant I/O would be
nice.
I've looked at Lattice and Altera and haven't found the perfect
solution. I can use larger than necessary Altera devices (ACEX1K)
but that seems to be the wrong direction.
Any suggestions/recommendations.
Thanks
George
Article: 71553Here's the situation: an external signal is used as a local clock for a set of eight IOB FFs. There is a UCF file MAXSKEW constraint of 70ps on the signal. PAR reports very low skew (~20ps) on the clock net. However, the MAXSKEW constraint is shown as violated (~200ps skew). I was surprised b/c in an earlier design w/ local clocking for CLB FFs, the net skew and MAXSKEW values only differed by about 40ps. Does anyone have insight as to what contributes to the additional skew when clocking at IOB FFs?Article: 71554
George wrote: > I've attempting to select an FPGA for a new design. > > The design will have 9 of the following: > 12 bit latches > 12 bit down counter > 1 bit output latch > > So one measure of the size might be 25 registers * 9 = 225 registers. > > The counting freq is 15 MHz. > > The latches get loaded from an existing micro. So I need a 12 input > pins for a data buss, 4 input pins for which register, a clock pin and > let's say 4 pins for control lines. > Along with the 9 output signals. > > So another measure is 12+4+1+4+9 = 30 pins not counting power and > ground. > > It would also be desirable to be packaged in a PLCC but TQFP in ok. > > And the device should be reprogrammable using JTAG (add 4 more pins). > > Voltage is not much of an issue. However 5 V tolerant I/O would be > nice. > > I've looked at Lattice and Altera and haven't found the perfect > solution. I can use larger than necessary Altera devices (ACEX1K) > but that seems to be the wrong direction. > > Any suggestions/recommendations. PLCC / 5V /15MHz / 225 registers is more trailing edge, so look at Atmel's AT40K FPGA family (meets all features), or possibly a CPLD - Lattices 4000 family have 5V tolerant I/O ? -jgArticle: 71555
Edmond Cote wrote: > Hi Simon, > > I've been investigating lately *exactly* the same issues you have, > however I finally made a decision and ordered the NuHorizon's board. > > While the width of the SDRAM was a deterrent, simply placing two read > cycles back-to-back should solve the obvious problem. Yes, but I have *plans* [grin] The idea is to use the burst-mode of the DDR2 SDRAM to fill a line of i/d cache at once, taking a hit on fetching the first entry in the line, but hopefully winning overall. For that to work though, I want the access to RAM to be as fast as possible. It would of course work with 2x16-bit access, but I want speed :-) > For curiousity's sake, are you working on a commericial or academic > project?, I am also working on implementing a MIPS based > system-on-a-chip. If you pick up that particular board, maybe we could > help each other out, since the kit includes next to no documentation. I've more or less decided to go for the BroadDown2 board - I think the possibilities for adding stuff onto it are better, and I want SDI in and analog-video --> video decoder chip (Phillips SAA7115 probably). I want to put an MPEG2 decoder / encoder (one at a time) onto the FPGA as well as the CPU core for general purpose stuff. It's going to need an SDRAM controller, and probably a PCI interface too... Like I said, plans :-) So, I'm looking really at the 1.5M part rather than the 400k part, which means lots of expense (Foundation, aaarrggghhh), and I'm going to try and get as much done *before* I cough up the cash to decide if I can actually *do* it or not... As for motive, well at the moment it's purely curiosity on my part, but if it all pans out well, there is a commercial possibility (I work in the professional post-production industry, and there is a gap I could fill...) Simon.Article: 71556
There is the XCR3256XL http://direct.xilinx.com/bvdocs/publications/ds013.pdf This is a 256 macrocell part that operates at 3.3V. It has the required 225 flops (31 to spare), JTAG and is 5V tolerant on the I/Os. It is offered in both TQ and PLCC packages. 15 MHz would bea "piece of cake". It's overkill in the I/O , but more is better than less. Of course, there is a 1.8V version, but it does note tolerate 5V without extra circuitry on the outside. Peter Alfke, Xilinx Applications ================================== > From: george.martin@att.net (George) > Organization: http://groups.google.com > Newsgroups: comp.arch.fpga > Date: 21 Jul 2004 13:02:10 -0700 > Subject: FPGA Selection-- > >Article: 71557
Hi, Does anyone know of any cheap FPGA's? By cheap I mean £5 or less. Also, do you know any suppliers in the UK? Thanks,Article: 71558
Dave, Thanks for the info - it was very useful! "Ryan Fong" <rfong@vt.edu> wrote in message news:cdgqc3$7ob$1@solaris.cc.vt.edu... > Fellow comp.arch.fpga users, > > I'm trying to obtain information die sizes for various Xilinx FPGAs in the > Virtex, Virtex-II Pro, Virtex-II, and Spartan-III families. I am using this > information in my Master's thesis to approximate the physical lengths of > long wires, and how they have been scaling with delay. Any pointers will > help. Thanks. > > -Ryan > >Article: 71559
What do you want them for? Are you building a run of boards? BTW: Xilinx has a $99 spartan 3 development board. "Ed" <Ed@nospam.com> wrote in message news:cdm3g3$809$1@news5.svr.pol.co.uk... > Hi, > > Does anyone know of any cheap FPGA's? By cheap I mean £5 or less. Also, do > you know any suppliers in the UK? > > Thanks, > >Article: 71560
Well I sat through an hour of market talk so I could fill out the survey in hopes of winning a digital camera only to have the presentation close with no survey presented. WHAT A LOAD OF CRAP.Article: 71561
On Thu, 15 Jul 2004 13:14:33 +0200, Amontec Team wrote: > Hi all, > > Sorry but this question is not about logic system. > > I have to control the VCCO of one bank of a SPARTAN-3. > I need to be able to control the drive of 3.3V, 2.5V, 1.8V, 1.5V, 1.2V > to VCCO. How about a digital pot (Xicor or similar) in the feedback for an adjustable linear regulator?Article: 71562
Ok Christos, thanks a lot. Rgds "Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message news:<cdl7n4$rg0$1@sunnews.cern.ch>... > "ALuPin" <ALuPin@web.de> wrote in message > news:b8a9a7b0.0407202330.41ee13a0@posting.google.com... > > Hi, > > > > I have a directory called "TOP_PROJECT" in which I have several > submodules. > > > > These submodules include VHDL files among each other. That can be done > > in QuartusII -->Projekt --> Add/Remove Files in Project > > There you have to specify the path of the VHDL file you want to include. > > > > But what if I want to change the name of "TOP_PROJECT" directory to > > "TOP_PROJECT_X" ? > > Is that a problem? Are the VHDL files still included correctly? > > > > And what if I change the directory name of a submodule ? Does > > Quartus update the "links" by itself or do I have to change the links > > manually? > > > > Thank you for your help. > > > > Kind regards > > Hi, > > After you open the moved project in the new directory, first thing is to > change the 'User libraries' found in the settings menu. > > Most of the times this is the only thing I need to do. > In the case though, you decide to change also the name or place of a > subfolder then in the Add/remove files setting you have to remove and add > again from the new folders the files affected. > > Hope I explained it clear enough for you to understand, if not let me know. > > Christos Zamantzas at cern dot ch.Article: 71563
Jim, Lattice's ispMACH4000 is a great family and available in different packages. However, George mentioned he want's to use a PQFP,and the ispMACH4000 is not available in PQFP. Ttherefore I would like to suggest a M4A3-256/128-10YC. This is the previous generation. If price matters, and George can live with TQPF (which is actual a smaller package) then he can chose the LC4256V-75T100C. This device has 64 IOs. Regards, Luc On Thu, 22 Jul 2004 09:16:05 +1200, Jim Granville <no.spam@designtools.co.nz> wrote: >George wrote: >> I've attempting to select an FPGA for a new design. >> >> The design will have 9 of the following: >> 12 bit latches >> 12 bit down counter >> 1 bit output latch >> >> So one measure of the size might be 25 registers * 9 = 225 registers. >> >> The counting freq is 15 MHz. >> >> The latches get loaded from an existing micro. So I need a 12 input >> pins for a data buss, 4 input pins for which register, a clock pin and >> let's say 4 pins for control lines. >> Along with the 9 output signals. >> >> So another measure is 12+4+1+4+9 = 30 pins not counting power and >> ground. >> >> It would also be desirable to be packaged in a PLCC but TQFP in ok. >> >> And the device should be reprogrammable using JTAG (add 4 more pins). >> >> Voltage is not much of an issue. However 5 V tolerant I/O would be >> nice. >> >> I've looked at Lattice and Altera and haven't found the perfect >> solution. I can use larger than necessary Altera devices (ACEX1K) >> but that seems to be the wrong direction. >> >> Any suggestions/recommendations. > > PLCC / 5V /15MHz / 225 registers is more trailing edge, so look at >Atmel's AT40K FPGA family (meets all features), or possibly a CPLD - >Lattices 4000 family have 5V tolerant I/O ? >-jgArticle: 71564
or you could use the incremental design flow http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/xst/xst0035_6.html "Cody" <cody1980@hotmail.com> wrote in message news:40fdd0d6@news.starhub.net.sg... > remember to check the KEEP_HIERARCHY in the XST Options, and put > AREA_GROUP "your_area_group_name" PLACE = CLOSED; > AREA_GROUP "your_area_group_name" GROUP = CLOSED; > > Kelvin > > > > > > "Jim Wu" <NOSPAM@NOSPAM.COM> wrote in message > news:fujLc.30825$F8.15097@nwrdny02.gnilink.net... > > > > > > Ramtilak wrote: > > > Hi, > > > > > > Can anyone suggest how to assign a area constraint on a sub-module > > > within my design? I dont care where the other sub-modules are as long > > > as this particular sub-module is in the required area. I know we can > > > assign a area constraint for the whole design. But, how to do it for a > > > sub-module? > > > > For Xilinx FPGA and tools, add something like below to the ucf file: > > > > INST "hierarchy/path/to/submodule" AREA_GROUP = "your_area_group_name"; > > AREA_GROUP "your_area_group_name" RANGE = range; > > > > HTH, > > Jim (jimwu88NOOOSPAM@yahoo.com remve NOOOSPAM) > > http://www.geocities.com/jimwu88/chips > >Article: 71565
I am an M.Sc. Instrumentation Science student in Univ. of Pune,India. I am supposed to cover six 1/2 hr. seminars on FPGAs & CPLDs. I would like to know more infromation about what an FPGA or CPLD comprises of completely. If you know of any such resource/white paper, pls reply here or mail me at : arolk@hotmail.com I am covering VHDL, Desigin considerations for FPGAs and its Boards, and a few case studies. If you have any info. regarding this pls reply or mail me.Article: 71566
"Amit Olkar" <arolk@hotmail.com> wrote in message news:7747d0b4.0407220313.3d33410c@posting.google.com... > I am an M.Sc. Instrumentation Science student in Univ. of Pune,India. > I am supposed to cover six 1/2 hr. seminars on FPGAs & CPLDs. I would > like to know more infromation about what an FPGA or CPLD comprises of > completely. If you know of any such resource/white paper, pls reply > here or mail me at : arolk@hotmail.com > I am covering VHDL, Desigin considerations for FPGAs and its Boards, > and a few case studies. If you have any info. regarding this pls reply > or mail me. The best way to learn this stuff is to buy a couple of small CPLD chips like the Xilinx XC9536 or the Altera EPM7064, design and make a small PCB with the chip, a clock, programming interface and breadboarding area, buy or make a programming adapter, download the free development software provided by Xilinx and Altera and start playing with it. It'll only take a day or two to get started and you'll learn far more than just reading about it. I've got one or two designs on my web site that will help you get started. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 71567
BurchED announces the availability of the Sydney-X1
FPGA Computer, for the introductory price of US$499 !
The SYDNEY-X1 FPGA Computer -
An educational FPGA development system for universities,
design engineers, and electronics hobbyists.
http://www.burched.biz/sydneyx1.html
Features:
* Complete FPGA system with keyboard, mouse, VGA cable,
speaker, 64MB CF card, RS232 port, power supply
and FPGA programming cable.
* B5-X300 FPGA motherboard with 300K gate Xilinx
SpartanIIE device.
* Modules mounted in a stylish transparent box.
* Works with the free Xilinx WebPACK(tm) design software.
* Programming in VHDL or Verilog hardware description
language.
* Two 7-Segment-Displays.
* 2Mbit fast SRAM (accessible as 128K x 16 or 256K x 8).
* 64 colour VGA output.
* Mono audio output with speaker, for great quality, loud
sound output
* Flash-config device, configures FPGA automatically on
power-up.
* Power supply, with a wall plug for your country.
* Access to the BurchED Sydney-X1 user login area.
* Five-Pack deal (five Sydney-X1 computers in a box) for
university customers that want to put the Sydney-X1s
into student laboratories. Fantastic value when
buying five at a time.
Order code: 5Pack-Sydney-X1 FPGA Computers.
Full details of the Sydney-X1, including pictures and
screenshots, are at http://www.burched.biz/sydneyx1.html
Other new BurchED products in July 2004:
* B5-Starter-Value-Pack
http://www.burched.biz/b5startervp.html
* B5-Audio-Out
http://www.burched.biz/b5audioout.html
* B5-Super-Mounting-Board
http://www.burched.biz/b5supermountingboard.html
* B5-Super-Perspex-Box
http://www.burched.biz/b5superperspexbox.html
The B5-Audio-Out or the Super-Mounting-Board / Box
may be very useful additions to your kit if you already
own a B5-Super-Value-Pack.
Article: 71568To aid debug with Xilinx chipscope, I've added some temporary signals to the design that are only for diagnostic purposes. However, these signals get optimized away in the XST -> map -> PAR tool chain. Looking for ways to preserve the diagnostic signals so they can be hooked up with the Chipscope Inserter tool.Article: 71569
Hello Guys, I am facing this chellenge for a long time now. I have TTL compatible clock (20MHz) with rise/fall time around 40 ns. It goes to my CPLD, which outputs 3 clks of 10MHz, 5MHz and 2MHz. And the CPLD (MAX3032) will also give around 40 ns rise/fall time I guess. I need rise/fall times of < 2ns for my application. I have tried different things including trying to buffer the clock but still doesnt work. I am sure many people have come across this problem. Anybody has a solution(s)! Thanks, DrewArticle: 71570
ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0407212237.26c40159@posting.google.com>... > Ok Christos, > > thanks a lot. > > Rgds > > "Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message news:<cdl7n4$rg0$1@sunnews.cern.ch>... > > "ALuPin" <ALuPin@web.de> wrote in message > > news:b8a9a7b0.0407202330.41ee13a0@posting.google.com... > > > Hi, > > > > > > I have a directory called "TOP_PROJECT" in which I have several > submodules. > > > > > > These submodules include VHDL files among each other. That can be done > > > in QuartusII -->Projekt --> Add/Remove Files in Project > > > There you have to specify the path of the VHDL file you want to include. > > > > > > But what if I want to change the name of "TOP_PROJECT" directory to > > > "TOP_PROJECT_X" ? > > > Is that a problem? Are the VHDL files still included correctly? > > > > > > And what if I change the directory name of a submodule ? Does > > > Quartus update the "links" by itself or do I have to change the links > > > manually? > > > > > > Thank you for your help. > > > > > > Kind regards > > > > Hi, > > > > After you open the moved project in the new directory, first thing is to > > change the 'User libraries' found in the settings menu. > > > > Most of the times this is the only thing I need to do. > > In the case though, you decide to change also the name or place of a > > subfolder then in the Add/remove files setting you have to remove and add > > again from the new folders the files affected. > > > > Hope I explained it clear enough for you to understand, if not let me know. > > > > Christos Zamantzas at cern dot ch. Be very careful here. I do version control by creating a new top directory V00-00 then V00-01 etc. I copy over all the files in the older directory and then open the project file in the new directory. It seems that I have to open and close that new project for all the directory links to be resolved but I haven't tested this completely to know that just once will work. The problem I come across is as I open bdf files in a heiarcial manner some times they refer to files in the previous directory (an earlier versioin in my case). In general it works but be careful. GeorgeArticle: 71571
Try looking at the material located at: http://www.engr.sjsu.edu/crabill This might be a good start. Eric Amit Olkar wrote: > > I am an M.Sc. Instrumentation Science student in Univ. of Pune,India. > I am supposed to cover six 1/2 hr. seminars on FPGAs & CPLDs. I would > like to know more infromation about what an FPGA or CPLD comprises of > completely. If you know of any such resource/white paper, pls reply > here or mail me at : arolk@hotmail.com > I am covering VHDL, Desigin considerations for FPGAs and its Boards, > and a few case studies. If you have any info. regarding this pls reply > or mail me.Article: 71572
I'm using iSystem's logic analyzer: http://www.isystem.com/Products/Logic%20Analyzer/iLA128_Page1.htm It's not state of the art, but you can build pretty complex triggers. It comes with decent SW, which is rare these days... Igi "ernie" <ernielin@gmail.com> wrote in message news:d7fe9825.0407191638.58b29e0c@posting.google.com... > Hi, > > Can anyone recommend any good (and cheap) 32-channel analyzers? By > cheap I mean less than or approximately $1000. It would be nice if > the software supported complex triggering and the analyzer had > decently fast sampling rates. Sample depth is not really a critical > issue but more is obviously better. > > Thank you!Article: 71573
Any modern FPGA or CPLD will give you a (lightly loaded) rise or fall time below 2 ns. Just stay away from the museum stuff. Peter Alfke ================================= > From: dhruvish@gmail.com (Drew) > Organization: http://groups.google.com > Newsgroups: comp.arch.fpga > Date: 22 Jul 2004 07:11:47 -0700 > Subject: Converting High Rise Time clock to Low Rise time clock - Chellenge! > >Article: 71574
Drew wrote: > > Hello Guys, > > I am facing this chellenge for a long time now. I have TTL compatible > clock (20MHz) with rise/fall time around 40 ns. It goes to my CPLD, > which outputs 3 clks of 10MHz, 5MHz and 2MHz. And the CPLD (MAX3032) > will also give around 40 ns rise/fall time I guess. I need rise/fall > times of < 2ns for my application. I have tried different things > including trying to buffer the clock but still doesnt work. I am sure > many people have come across this problem. Anybody has a solution(s)! What did you buffer the clock with? If you use any sort of TTL or CMOS inverter, buffer or gate, it should sharpen up the rising and falling edges. You could even run the clock through the CPLD if you have two spare pins, one input (not clock) and one output. Just have output := input. You may not get a 2 ns rise time depending on the type of device you use for a buffer. A faster logic family normally has a faster rise time. Check the data sheet. If you are going through any standard logic device as a buffer and you still have 40 ns rise time, there is something else wrong, like maybe the scope you are measuring it with? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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