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Hi everybody, while you are discussing asynchronous designs on FPGAs... Has anybody made experience with the balsa tools? http://www.cs.man.ac.uk/apt/projects/tools/balsa/ And YES! todays FPGAs are designed to work synchronously, but there are asynchronous chips around (e.g. part of the SPARC 2i and other µP) that seem to work sufficently. So, while it's still hard work its not impossible to do.. My final question is...when will there be FPGAs with C-Elements etc. ?? (Small market at this time, I think :-) ) Ray Andraka <ray@andraka.com> wrote in message news:<40F7154E.794740D5@andraka.com>... > I'm not. FPGAs are specifically designed for synchronous logic designs. > While an async design can be done if done very carefully, the lack of support > for this by the tools makes it excruciating at best. Every once in a while > someone comes along with the bright idea to use an FPGA as a platform for > async logic experiments. A search of the literature should provide a trail of > efforts that al come to the same conclusion: that the tools and FPGAs don't > support it. There are plenty of academics that have already plowed this > path. Read their work and be forewarned. >Article: 71376
I don't know. *that* part :) has always worked for me. Let me just describe what I do and maybe you will see something. This is NiosI BTW. 1. Small bootloader code in onchip ram at the reset location. This gets built and placed there during the SOPC generate and QII build process. In SOPC onchip ram contents I select build bootloader.c 2. bootloader.c wakes up and checks if I have any srec data in the unused portion (well unused isn't the correct word, but the non-harware configuration portion) of the asmi. I think I used the midway point of my 4Mbit asmi chip. Would/should work the same for any flash. 3. If it finds some then it blindly processes each srec by blindly memcpy'ing the srec data wherever it says it goes. (The srecs addresses are set during the build/link/creation of the srec file that has been copied to the asmi chip) 4. I'm a little fuzzy here since I wrote this a few months back, but I believe the last srec contains a start address and I jmp there and boom - I'm booted and running. (do a seach for srec on google and you'll find a/the spec for srec's) If it should work but doesn't try lowering your cpu clock and see if it works then. Ken "tns1" <tns1@cox.net> wrote in message news:SWAJc.1005$ml.940@lakeread05... > Thanks. I see where I can pick the reset location. My configuration is > just as you describe - a bootstrap routine onchip, and an app that gets > copied from flash to external sram before execution. > > My earlier statement about the bootstrap base address was wrong - the > base address is correct for this onchip code image. > > However, there is a bug in the way either my bootstrap or app gets > built, that causes the application to jump from sram to flash addresses > for any function call in main() (ISRs too). The base address for my app > is correctly set to sram, not flash. > > I believe the problem has to do with the initialization code before > main(), either the routines that set up new stack frames and the CWP > handler. To track down this bug I have been trying to make use of gdb > (no jtag port for OCI) for either my hw target or the cpu simulator > target. I'd like to step thru the init stuff. Using gdb for target hw > debug does work, but so far I can't step thru the init stuff (it locks > when stepping into flash - no surprise). > > Has anyone gotten the nios cpu simulator to work under gdb? I can load > an image and source but I can't step. I can't find the sim.ld script > that is mentioned in the gdb docs. > > > > Kenneth Land wrote: > > In SOPC builder you set the Reset Location in the Nios More tab. > > > > This is where the system will reset to. > > > > I always set this an internal ram that holds either Germs or my program. > > That program can load a larger program out of flash and then jump to it. > > (or whatever you want it to) > > > > The new NiosII has fancier automatic boot options but I haven't used it for > > that yet. > > > > Ken > > > > "tns1" <tns1@cox.net> wrote in message news:hSwJc.974$ml.802@lakeread05... > > > >>I am trying to understand the low level startup sequence on a custom > >>Nios board. When the Nios (3.2) resets, what determines where it fetches > >>its very first instruction? Is it always from the onchip bootstrap area > >>or is this configurable? I don't have the OCI so I assume I can't just > >>step thru from reset on my target (with gdb). > >> > >>As I understand it, SOPC(4.0) compiles my custom bootstrap and Quartus > >>(4.0sp1) adds this code to the pof, but not to the application srec. I > >>am confused that the objdump for the bootstrap shows it is compiled for > >>my SRAM base, not the onchip area. The Nios manuals say the code is not > >>generally relocatable so this does not seem right. I don't see how to > >>fix this base in the Nios dialog - it appears to be set correctly. > >> > >>TIA > >> > > > > > > >Article: 71377
Any one know of the most efficient method (seed and space wise) of implementing conversion of ones to twos and twos to ones compliment??? Currently using addition and subtraction, but this is very waist-full!!! thanks CArticle: 71378
chuk wrote: > Any one know of the most efficient method (seed and space wise) of > implementing conversion of ones to twos and twos to ones compliment??? > Currently using addition and subtraction, but this is very > waist-full!!! > thanks > C I'd say with XOR and +/-1.Article: 71379
Have a look at our new product Broaddown2. It can have a driver added using the expansion positions. Next batch available 6-8 weeks. Details here http://www.enterpoint.co.uk/moelbryn/broaddown2.html . -- John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:10fdfm7rqi5si78@corp.supernews.com... > > Well I almost bought a development kit from Xilinx's > Online Store, however, I was looking at the schematics > and saw that this is the same board designed by Digilent, > a board that I already had. So I guess my first question > is what do I get with the Xilinx kit that I might not already > have? > > I haven't pursued my Digilent board too much because > there didn't seem to be any software for it. I also bought > a board from Memec and it has a few software examples, > but no VGA port, which is an interest of mine. If anyone > has any more examples for the Memec board, that would > be of great interest to me. > > I would like to see a real VGA driver on a dev kit but I am > also interested in what this Digilent 3 bit shoestring VGA can > do. It seems to simple to believe. Has anybody done anything > with it? > > I think the XESS people were going to do a Spartan3 board. > Anyone know about this? > > Salutations, > > Brad > >Article: 71380
Sylvain Munaut wrote: > > chuk wrote: > > Any one know of the most efficient method (seed and space wise) of > > implementing conversion of ones to twos and twos to ones compliment??? > > Currently using addition and subtraction, but this is very > > waist-full!!! > > thanks > > C > I'd say with XOR and +/-1. By definition, converting between 2's comp and 1's comp is a matter of adding or subtracting 1. If you use XOR you still need a carry and you are just building your own half adder. Perhaps there is a different way to solve the larger problem? Can Chuk tell us why he is converting between 2's and 1's complement? Maybe we can find a way to combine this operation with something else or maybe it is not needed at all? So where is the data coming from and what are you trying to do with the converted number? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 71381
as far as i remember, if you are using a CLKIN input of DCM with that high frequency clock, its input clock should have 50 +/- 5% duty cycle. a division by 3 using counter would not give that. "Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:v4hef0pkh54lg6jgjs0sojpi8qju9sm95q@4ax.com... > On Thu, 15 Jul 2004 15:09:12 -0400, "Vladislav Muravin" > <xfilex2003@hotmail.com> wrote: > > >what is your refclk frequency?. > > 64B/66B coding is used in 10G Ethernet. I guess this is what the OP > is using. > One would assume that the output frequency would be 644.53125MHz or > perhaps 161.1328MHz or so, so refclk would be 625 or 156.25MHz. > > Jitter is really important for this sort of design. I recommend that > the OP uses an external analog PLL to generate the clock. > > Regards, > Allan. > > >"Patrik Eriksson" <no.spam@netinsight.net> wrote in message > >news:40f69fd4$1@fnewsa.telia.net... > >> Hi, > >> > >> I would like to generate a clock from a refclk according to the > >> following function: > >> > >> clk = refclk*(64/66) > >> > >> I will implement this function in an VirtexII Pro FPGA and my first > >> approach is to divide the refclk by 3 in logic and then use a DCM to > >> multiply with 32/11. > >> > >> clk = refclk*(1/3)*(64/22) > >> clk = refclk/3*(32/11) > >> > >> Will this work? The frequencies has to be locked to each other. > >> > >> > >> ------ > >> Patrik Eriksson > >> > > >Article: 71382
Hello all, I am kind of confused how is bidirectional pin displayed in the Waveform Simulation. In my waveform file I have A as an bidirectional pin but when I run simulation one more pin name appears called A~result. I guess that's the output and the other one which is displayed as A is input in simulation. But I need to know more like, are those pins supposed to be displaying same waveform? If not which one is a true waveform. I am trying to find some help on this in Quartus but I cannot see it. Your help is appreciated DrewArticle: 71383
Hi, I've made a schematic design with the Xilinx environment. When I load Xilinx PACE (to assign pins, etc) I only see the pins in the list my top level had in the past, not the updated situation Anyone knows how to fix this (it's gotta be simple, I just can't seem to find it) ? Thanx! MikeArticle: 71384
Title: FAE I Location(s): Merelbeke - Belgium -Assist and support customers with technical expertise to product design-in. -Aid customers through the full design cycle. -Conduct technical training of distributor personnel. -Provide field technical support, responding to customers' technical questions relative to products. -Effectively demonstrate and pitch products and software to customers. -Generate application notes, technical articles, and technical presentations. -Design and create customer templates, reference designs, and solutions (i.e., SONET/Framers/Controllers, ATM, Utopia, AALx, PLCP, CRC, POS, GSM, GPRS, EDGE, 3G, GigEthernet, RMII/MII, T1/E1, MAC, FIR, Reed Solomon, SCSI, Fiber Channel and SPI4-2.0) -Execute sales plans developed by the Regional Sales Manager (RSM) or Area Technical Manager (ATM). -BS Electrical Engineering. -1+ years design experience and providing applications support, making technical presentations. -Knowledge of VHDL or Verilog design for ASIC and FPGA. -Good understanding of competitive PLD, FPGA, HDPLD and ASIC design alternatives. -System knowledge of ATM networks, radio networks and/or interface protocols. -Self-motivated and driven. -Strong written and verbal communication skills and the ability to work with multiple groups. -Must be detail oriented with strong customer service skills. -High level of PC skills with knowledge of MS Office Suite.Article: 71385
ibis@tiscalinet.de (E. Backhus) wrote in message news:<e5e7ca2e.0407160017.61ceb013@posting.google.com>... > Hi everybody, > while you are discussing asynchronous designs on FPGAs... > > Has anybody made experience with the balsa tools? > > http://www.cs.man.ac.uk/apt/projects/tools/balsa/ > > And YES! todays FPGAs are designed to work synchronously, > but there are asynchronous chips around (e.g. part of the SPARC 2i and > other µP) > that seem to work sufficently. So, while it's still hard work its not > impossible to do.. > My final question is...when will there be FPGAs with C-Elements etc. > ?? > (Small market at this time, I think :-) ) > An outgrowth of the Amulet project! Well Manchester always had a great reputation for these sorts of things but even in full custom design Async design is pushing a rock up a hill, there are few $ EDA tools in the ASIC market to my knowledge and few takers. I suspect that for large asics, a better aproach is to design clocked subsystems with pseudo async interfaces so any no of free cycles can pass by between clocked blocks. Its still really a synced design with sync handshakes but more tolerant of delays that are in clock periods. Still thats hard too. Mind you with Xilinx talking up 500MHz and my timing reports giving me many single wire nets in 1-4ns zone, maybe FPGAs will have to do same thing. regards johnjakson Whats a C-Elements?Article: 71386
Rick, Bad sleepless night. But really, I was offended by the silly response, talking about applications that have 'no power' where DCI is all of the power. Let's face it, I can create any example I want (the part is programmable after all). So I can 'prove' that any current is either a major issue, and can not be tolerated whatsoever, or than it is totally insignificant. That was the point of my 'school yard' comment. Sorry to have offended you. I have so many friends out there, I was actually surprised when no one called me on that one.....they call me on just about everything else! AustinArticle: 71387
Have you installed a PCI driver for the board on the host PC? What Os are you using?Article: 71388
Austin Lesea wrote: > > Rick, > > Bad sleepless night. But really, I was offended by the silly response, > talking about applications that have 'no power' where DCI is all of the > power. > > Let's face it, I can create any example I want (the part is programmable > after all). > > So I can 'prove' that any current is either a major issue, and can not > be tolerated whatsoever, or than it is totally insignificant. > > That was the point of my 'school yard' comment. > > Sorry to have offended you. > > I have so many friends out there, I was actually surprised when no one > called me on that one.....they call me on just about everything else! At least you realized that you were going off a bit. The bad ones think they are totally justified. :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 71389
Rick, I am really so easy. I recognized a long time ago that most engineers are insufferable prima donnas, with egos that encompass small planetary systems.... Thus, if I can not nurture my idiosyncracies, I would not have any personality at all.... Austin rickman wrote: > Austin Lesea wrote: > >>Rick, >> >>Bad sleepless night. But really, I was offended by the silly response, >>talking about applications that have 'no power' where DCI is all of the >>power. >> >>Let's face it, I can create any example I want (the part is programmable >>after all). >> >>So I can 'prove' that any current is either a major issue, and can not >>be tolerated whatsoever, or than it is totally insignificant. >> >>That was the point of my 'school yard' comment. >> >>Sorry to have offended you. >> >>I have so many friends out there, I was actually surprised when no one >>called me on that one.....they call me on just about everything else! > > > At least you realized that you were going off a bit. The bad ones think > they are totally justified. :) >Article: 71390
The clock that operates the ICAP module in the OPB_HWICAP Peripheral is the same as the OPB BUS, this can be a problem because the maximum frequency for operating the ICAP is 33MHZ, and it' s very common to have the BUS running at higher speeds. The PLB_ICAP core presented at XAPP662 didn't have this problem because it could operate with a controlled ICAP Clocking, but this core doesn't have the same features as the OPB_HWICAP. An obvious solution to my problem could be having two different OPB BUS running at different speeds, but unfortunately the PLB2OPB takes to much space and I kind of need it. So my question is this, his it possible to change OPB_HWICAP so it runs with a controlled ICAP Clocking, as anyone done it? Or alternatively is it possible to have two OPB BUS running at different speeds without using two different PLB2OPB? Thanks Miguel SilvaArticle: 71391
Is it possible to use ChipScope Pro to stimulate signals? I'm trying to figure out if i can use ChipScope Pro to drive some signals in my FPGA.Article: 71392
Why?
Tom Seim wrote many many times:
> I would avoid Nu Horizons at all costs.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 71393
That depends on the sophistication of the motor controller. If you are
producing sinusoids for each winding, along with non-linear
acceleration/deceleration and precise positioning, the controller can pretty
quickly exceed the resources of a CPLD. I did some motor controls several
years ago for a photo printer application that included DPLLs on the motor
feedback, and very precise control of position, velocity, acceleration as well
as corrections for web tension and movement. Got to be a rather interesting
DSP app.
Kelvin wrote:
> it seems most likely your FPGA will be very underutilized...Go for CPLD...
>
> Kelvin
>
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 71394Joe Avnet does not make host drivers. Either way it should still show up on the Device Manager in Windows or lspci in Linux as an undefined device if the configuration cycles of the PCI core are working correctly. I tried to find this out with a logic analyzer but no luck. Thanks for you help though. -Jackson <joe> wrote in message news:ee878f6.0@webx.sUN8CHnE... Have you installed a PCI driver for the board on the host PC? What Os are you using?Article: 71395
Vivek, Not detailed in the product literature for Chipscope Pro (at least I couldn't find it) is the "virtual front panel" which allows a GUI interface for pushbuttons, switches, leds, etc. in order to not only 'listen to', but to 'talk to' the logic in your FPGA design. Since this is a new feature since 6.1i, it has already seen improvements, and even more improvements are in the works for the next release. We use it internally more and more, as it makes prototyping far simpler. Contact your FAE, or the hotline for support, Austin Vivek Joshi wrote: > Is it possible to use ChipScope Pro to stimulate signals? I'm trying to > figure out if i can use ChipScope Pro to drive some signals in my FPGA.Article: 71396
ok ! gonna use 1 mcu ! one with bluetooth & usb port 8/16 bit and external adc 8 channel hd 16 bit ! thanks for your help !!Article: 71397
On 14 Jul 2004 06:24:26 -0700, M Shehzad Hanif <lists_shehzad@softhome.net> wrote: > Hi > > I want to configure my Virtex-II (Avnet Development Board)using > MultiLINX download Cable. I am using Slave Serial Mode. But iMPACT > Software do not programme the FPGA and it says "DONE pin did not go > low" . Try, maybe, set or unset that bit by setting properities in "generating bit-file" stage. Best Regards Jerzy Gbur -- JGArticle: 71398
Yes, you can. They have an asynchronous(or synchronous) virtual I/O module. You can also build a simple GUI with LEDs, push butttons, numeric entries, etc. I've used it recently to control all of the RF attenuators and switches on a radio product. In the past I've had to run the processor under emulator at early stages to have this kind of control. It's great not having to monkey with the embedded software.Article: 71399
( reposting this, as the first try never showed up )
Austin,
Responding slightly out of order:
>
> It is always preferable to provide the customer with solutions
> that involve changing bits,
>
It's much more preferable to provide the customer with a DCI
adjustment circuit which doesn't glitch the impedance so much
when updating, and require years of subsequent BitGen tweaking.
You even said as much yourself, over on this thread in 2001:
http://www.fpga-faq.com/archives/28575.html#28576
Wherein you stated that the magnitude of the DCI impedance
updates was insignificant.
In that same thread, you also suggested that there was only
a 25mW power hit for each VRP/VRN pair:
http://www.fpga-faq.com/archives/28500.html#28510
Would you care to update either of those claims for Virtex2 ?
>
>I would appreciate it if you did detail every single omission,
>distortion, or mis-representation.
>
Coming soon to a newsgroup near you...
>
>In fact, I demand it, or an apology.
>
The only apologies due here are:
- from Xilinx, to its' customers, for failing to properly
document the plethora of Virtex2 DCI HW and SW problems,
now at 3.5 years after V2 product launch and counting.
- from you, for posting another sarcastic, condescending,
and disingenuous response to an accurate and level-headed post
>
>> In a small Spartan3 design drawing little current on VCCINT,
>>power consumption would be dominated by "sooooo much current",
>>especially if using 33 ohm VRP/N resistors as you suggested
>>earlier in the thread.
>
>To say "if you are already drawing no power, then 200 mW is
> a lot of power" is a pretty inane response.
>
Inane, huh? I found my original sentence quite pithy when
contrasted to your three paragraph "Nobody cares about 2 W
per chip" denial.
Just how much power do you think a <50 MHz 3S50 design
will be drawing on VCCINT ?
Or, perhaps that was some other FPGA company starting with "X"
that just announced a low power Spartan3 ???
>
>Peter's comment is perfectly accurate: series terminations dissipate
>virtually no power in the series termination resistors.
>
And what, pray tell, does that have to do with my statement:
'Peter's claim of "zero additional system power" was inaccurate'
In Austin's world, has the term "system power" been explicitly
redefined to exclude per-bank DCI overhead?
Brian
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