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Hello, I´m a Spanish student and i need to program a Hitachi LCD using
a Celoxica RC100 Spartan II and I can't do that the code show nothing
in the display. If somebody know how program it please tell me. I put
my code to all can see what i'm doing.
Thanks.
*******************************************************************************
*******************************************************************************
/*inculde standard header file*/
#include <stdlib.hch>
#ifdef DEBUG
/*set up a dummy clock*/
set clock = external "P1";
#else
#define RC100_BOARD
#define RC100_CLOCK_DIVIDE 4
#include <rc100.hch>
#endif
/***********************************************************************************************/
/* Definimos una serie de señales necesarias para el manejo */
unsigned int 8 Datos; // 8 lineas de datos
unsigned int 1 EN; // Linea de Enable
unsigned int 1 RS; // Linea de Selector de Registros
unsigned int 1 RW; // Linea de Lectura/Escritura
unsigned int 8 AAC; // Acumulador, solo usamos el bit 7 del mismo
unsigned int 8 A; // Donde guardamos lo que vamos a mostrar por el LCD
unsigned int 8 posicion; // Variables que usamos cuando queremos mover
el cursor
unsigned int 1 salir;
unsigned int 1 condicion; // Condicion para leer/escribir en el bus de
datos
unsigned int 8 x; // Variable que usamos en las operaciones de
leer/escribir del bus de datos
unsigned int 1 Z; // Variable que usamos para salir del buscle de
Wait_LCD()
// Variables a usar en los delays
unsigned int 8 TIEMPO1;
unsigned int 8 TIEMPO2;
unsigned int 1 LUZ; // luz del display
/***********************************************************************************************/
/******************ASIGNACION DE PINES A LAS DIFERENTES SEÑALES
USADAS**************************/
#ifndef DEBUG
/* Asignamos los pines a las señales declaradas con anterioridad */
// Datos ==> 8 pines ; Es de entrada/salida por lo que hay que
declararse 2 buses
/* Bus bidireccional de entrada y salida, cuando enable es 1 escribe
"write" en los pines
indicados, write contendra el valor a enviar a los pines,
cuando quiera leer los hara
de BiBus.read y leera los datos de los pines*/
interface bus_ts(unsigned int 8 read) BiBus(unsigned int write = x,
unsigned 1 enable = condicion)
with {data =
{"W18","AA20","Y18","V17","AA19","AB20","W17","V13"}};
/* En las señales de control siempre se escribe por lo que los buses
de las mismas basta
con que sean de salida */
// EN ==> 1 pin ;
interface bus_out() bus_en(unsigned int 1 en_out = EN) with {data =
{"Y13"}};
// RS ==> 1 pin ;
interface bus_out() bus_rs(unsigned int 1 rs_out = RS) with {data =
{"AA13"}};
// RW ==> 1 pin ;
interface bus_out() bus_rw(unsigned int 1 rw_out = RW) with {data =
{"AB13"}};
// Luz ==> 1 pin
interface bus_out() bus_lz(unsigned int 1 lz_out = LUZ) with {data =
{"W13"}};
#endif
/***********************************************************************************************/
/* Definimos las operaciones del LCD */
// Macros para la temporizacion de los delays
static macro proc espera2 (time)
{
unsigned 64 i;
for (i=0; i<(time/1000000)*80000000;i++)
delay;
}
static macro proc espera (time)
{
unsigned 64 i;
for (i=0; i<(time/1000)*80000000;i++)
delay;
}
macro proc Init_LCD ()
{
// Modo 8 bits
#ifndef DEBUG
RW = 1;
EN = 1;
RS = 0;
condicion = 0;
x = 0x38;
condicion = 1; // Escribimos en el bus de datos en valor de x
EN = 0;
espera2(100);
EN = 1;
RS = 0;
condicion = 0;
x = 0x0e;
condicion = 1; // Escribimos en el bus de datos el valor de x
EN = 0;
espera2(100);
EN = 1;
RS = 0;
condicion = 0;
x = 0x06;
condicion = 1; // Escribimos en el bus de datos el valor de x
EN = 0;
espera2(100);
#else
EN = 1;
RS = 0;
Datos = 0x38; // Movemos 0x38 a Datos
EN = 0;
espera2(100); // Rutina que espera 40microseg
EN = 1;
RS = 0;
Datos = 0x0e;
EN = 0;
espera2(100); // Rutina que espera 40microseg
EN = 1;
RS = 0;
Datos = 0x06;
EN = 0;
espera2(100); // Rutina que espera 40microseg
#endif
}
macro proc Clear_LCD ()
{
// Modo 8 bits
#ifndef DEBUG
RW = 1;
EN = 1;
RS = 0;
condicion = 0;
x = 0x01;
condicion = 1; // Escribimos en el bus de datos el valor de x
EN = 0;
espera(10);
#else
EN = 1;
RS = 0;
Datos = 0x01;
EN = 0;
espera(8); // Rutina que espera 1,64mseg
#endif
}
macro proc Write_Text (car)
{
// Modo 8 bits
#ifndef DEBUG
EN = 1;
RS = 1;
RW = 0;
condicion = 0;
x = car;
condicion = 1; // Escribimos en el bus de datos el valor de x
EN = 0;
espera(10);
#else
EN = 1;
RS = 1;
RW = 0;
Datos = car;
EN = 0;
espera2(8); // Rutina que espera 1,64mseg
#endif
}
macro proc Cursor_Pos (linea, pos)
// Operacion adicional para poder situar el cursor en la posicion que
queramos
/* Sinceramente no se si esto funcionara bien */
{
#ifndef DEBUG
EN = 1;
RS = 0;
if (linea == 1)
{posicion = pos;} // 0@pos
else if (linea == 2)
{posicion = 0x04 @ (pos<-4);} // Nos quedamos con, los ultimos 4
bits, pues los
// 4 primeros no los necesitamos y concatenamos con
// un 4; No estoy seguro de que esto sea asi!!!!????
else
delay; // Otro valor distinto de 1 ó 2 no es válido, por lo que no
hace nada
condicion = 0;
x = 0x80 + posicion;
condicion = 1; // Escribimos en el bus de datos el valor de x
EN = 0;
// Wait_LCD();
espera(8); // Rutina que espera 1,64mseg
#else
// Linea solo puede valer 1 ó 2 y posicion de 0 a 15
EN = 1;
RS = 0;
if (linea == 1)
{posicion = pos;} // 0@pos
else if (linea == 2)
{posicion = 0x04 @ (pos<-4);} // Nos quedamos con, los ultimos 4
bits, pues los
// 4 primeros no los necesitamos y concatenamos con
// un 4; No estoy seguro de que esto sea asi!!!!????
else
delay; // Otro valor distinto de 1 ó 2 no es válido, por lo que no
hace nada
Datos = 0x80 + posicion; // 80h, instruccion de "Set Cursor
Position", + posicion
// en la linea, esta va de 0 a 15
EN = 0;
// Wait_LCD();
espera(8); // Rutina que espera 1,64mseg
#endif
}
void main(void)
{
#ifndef DEBUG
LUZ = 1;
#endif
/*Sacamos el init y el clear fuera del bucle*/
Init_LCD();
Clear_LCD();
// Programa de ejemplo que escribe en el LCD "Hello_World"
A = 0b01001000; // Valor de la "H" en binario; Para pasarlo como
letras tengo que definir
// el tipo como char, pues como integer, aun poniendo la
almoadilla, falla
Write_Text(A);
}
Article: 71651Hi, As a licensed user of the Xilinx PCI core, you can go to the download lounge and access a tool called the "UCF Generator". You can use this to make a variety of UCF files. An implementation of PCI 32/33 in any Virtex or Spartan2 device is fairly "slam dunk", even without any logic placement at all -- as long as you don't do something bizarre with the pinout. EricArticle: 71652
Hi Seb I used EDK 6.2 Here's the .mhs PARAMETER VERSION = 2.1.0 PORT clk_40mhz = clk_40mhz, DIR = I, SIGIS = CLK PORT pci_TRDY_N = pci_TRDY_N, DIR = IO PORT pci_CBE = pci_CBE, VEC = [0:3], DIR = IO PORT pci_DEVSEL_N = pci_DEVSEL_N, DIR = IO PORT pci_FRAME_N = pci_FRAME_N, DIR = IO PORT pci_AD = pci_AD, VEC = [0:31], DIR = IO PORT pci_SERR_N = pci_SERR_N, DIR = IO PORT pci_IDSEL = pci_IDSEL, DIR = I PORT pci_INTR_A = pci_INTR_A, DIR = O PORT pci_IRDY_N = pci_IRDY_N, DIR = IO PORT pci_PAR = pci_PAR, DIR = IO PORT pci_GNT_N = pci_GNT_N, DIR = I PORT pci_Freeze = pci_Freeze, DIR = I PORT pci_PCLK = pci_PCLK, DIR = I PORT pci_STOP_N = pci_STOP_N, DIR = IO PORT pci_RST_N = pci_RST_N, DIR = I PORT pci_REQ_N = pci_REQ_N, DIR = O PORT pci_PERR_N = pci_PERR_N, DIR = IO PORT RS232_RX = RS232_RX, DIR = I PORT RS232_TX = RS232_TX, DIR = O PORT led_pin = led_pin, VEC = [0:7], DIR = IO PORT sw_pin = sw_pin, VEC = [0:7], DIR = IO PORT sys_clk = sys_clk, DIR = I, SIGIS = Clk PORT sys_rst = sys_rst, DIR = I BEGIN microblaze PARAMETER INSTANCE = mblaze PARAMETER HW_VER = 2.00.a BUS_INTERFACE DLMB = d_lmb BUS_INTERFACE ILMB = i_lmb BUS_INTERFACE DOPB = d_opb BUS_INTERFACE IOPB = d_opb PORT CLK = clk_40mhz PORT INTERRUPT = mblaze_int END BEGIN bram_block PARAMETER INSTANCE = bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = data BUS_INTERFACE PORTB = inst END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = i_bram_cntrl PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007FFF BUS_INTERFACE SLMB = i_lmb BUS_INTERFACE BRAM_PORT = data PORT LMB_Clk = clk_40mhz END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = d_bram_cntrl PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007FFF BUS_INTERFACE SLMB = d_lmb BUS_INTERFACE BRAM_PORT = inst PORT LMB_Clk = clk_40mhz END BEGIN opb_pci PARAMETER INSTANCE = pci PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00009000 PARAMETER C_HIGHADDR = 0x00009FFF PARAMETER C_PCIBAR_NUM = 2 PARAMETER C_PCIBAR_LEN_0 = 15 PARAMETER C_PCIBAR2IPIF_0 = 0x00008000 PARAMETER C_PCIBAR_ENDIAN_TRANSLATE_EN_0 = 1 PARAMETER C_PCI_PREFETCH_0 = 1 PARAMETER C_PCI_SPACETYPE_0 = 1 PARAMETER C_IPIFBAR_NUM = 1 PARAMETER C_IPIF_HIGHADDR_0 = 0x0000FFFF PARAMETER C_IPIFBAR2PCI_0 = 0x0 PARAMETER C_IPIFBAR_ENDIAN_TRANSLATE_EN_0 = 1 PARAMETER C_IPIF_PREFETCH_0 = 1 PARAMETER C_IPIF_SPACETYPE_0 = 1 PARAMETER C_NUM_INTERRUPTS = 13 PARAMETER C_OPB_CLK_PERIOD_PS = 25000 PARAMETER C_CLASS_CODE = 0x028000 PARAMETER C_DEVICE_ID = 0x9050 PARAMETER C_DMA_HIGHADDR = 0x0000A77F PARAMETER C_DMA_CHAN_TYPE = 0 PARAMETER C_DMA_LENGTH_WIDTH = 15 PARAMETER C_DEV_MIR_ENABLE = 1 PARAMETER C_INCLUDE_DEV_ISC = 1 PARAMETER C_IPIFBAR_1 = 0x0000A600 PARAMETER C_IPIF_HIGHADDR_1 = 0x0000A61F PARAMETER C_IPIFBAR2PCI_1 = 0x0 PARAMETER C_IPIFBAR_ENDIAN_TRANSLATE_EN_1 = 1 PARAMETER C_IPIF_PREFETCH_1 = 1 PARAMETER C_IPIF_SPACETYPE_1 = 1 PARAMETER C_PCIBAR_1 = 0xFFFFFFF8 PARAMETER C_PCIBAR_LEN_1 = 4 PARAMETER C_PCIBAR2IPIF_1 = 0x0000A600 PARAMETER C_PCIBAR_ENDIAN_TRANSLATE_EN_1 = 1 PARAMETER C_PCI_PREFETCH_1 = 1 PARAMETER C_PCI_SPACETYPE_1 = 1 PARAMETER C_VENDOR_ID = 0x10B7 PARAMETER C_INCLUDE_PCI_CONFIG = 1 PARAMETER C_REV_ID = 0x01 PARAMETER C_MAX_LAT = 0x08 PARAMETER C_MIN_GNT = 0x03 PARAMETER C_NUM_IDSEL = 1 PARAMETER C_DMA_BASEADDR = 0x0000A700 PARAMETER C_PCIBAR_0 = 0xFFFF0008 PARAMETER C_IPIFBAR_0 = 0x00008000 BUS_INTERFACE MSOPB = d_opb PORT TRDY_N = pci_TRDY_N PORT OPB_Clk = clk_40mhz PORT CBE = pci_CBE PORT DEVSEL_N = pci_DEVSEL_N PORT FRAME_N = pci_FRAME_N PORT AD = pci_AD PORT SERR_N = pci_SERR_N PORT IDSEL = pci_IDSEL PORT INTR_A = pci_INTR_A PORT IRDY_N = pci_IRDY_N PORT PAR = pci_PAR PORT GNT_N = pci_GNT_N PORT Freeze = pci_Freeze PORT PCLK = pci_PCLK PORT STOP_N = pci_STOP_N PORT RST_N = pci_RST_N PORT REQ_N = pci_REQ_N PORT PERR_N = pci_PERR_N END BEGIN opb_uartlite PARAMETER INSTANCE = uart PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x0000A000 PARAMETER C_HIGHADDR = 0x0000A0FF PARAMETER C_DATA_BITS = 8 PARAMETER C_CLK_FREQ = 40000000 PARAMETER C_BAUDRATE = 9600 PARAMETER C_USE_PARITY = 0 PARAMETER C_ODD_PARITY = 0 BUS_INTERFACE SOPB = d_opb PORT OPB_Clk = clk_40mhz PORT RX = RS232_RX PORT TX = RS232_TX PORT Interrupt = net_gnd END BEGIN opb_jtag_uart PARAMETER INSTANCE = jtag_uart PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x0000A100 PARAMETER C_HIGHADDR = 0x0000A1FF BUS_INTERFACE SOPB = d_opb PORT Interrupt = net_gnd PORT OPB_Clk = clk_40mhz END BEGIN lmb_v10 PARAMETER INSTANCE = d_lmb PARAMETER HW_VER = 1.00.a PORT SYS_Rst = sys_rst PORT LMB_Clk = clk_40mhz END BEGIN lmb_v10 PARAMETER INSTANCE = i_lmb PARAMETER HW_VER = 1.00.a PORT SYS_Rst = sys_rst PORT LMB_Clk = clk_40mhz END BEGIN opb_v20 PARAMETER INSTANCE = d_opb PARAMETER HW_VER = 1.10.b PARAMETER C_BASEADDR = 0xFF020000 PARAMETER C_HIGHADDR = 0xFF0201FF PARAMETER C_PROC_INTRFCE = 1 PORT SYS_Rst = sys_rst PORT OPB_Clk = clk_40mhz END BEGIN opb_gpio PARAMETER INSTANCE = led PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x0000A200 PARAMETER C_HIGHADDR = 0x0000A2FF PARAMETER C_GPIO_WIDTH = 8 BUS_INTERFACE SOPB = d_opb PORT OPB_Clk = clk_40mhz PORT GPIO_IO = led_pin END BEGIN opb_gpio PARAMETER INSTANCE = sw PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x0000A300 PARAMETER C_HIGHADDR = 0x0000A3FF PARAMETER C_GPIO_WIDTH = 8 BUS_INTERFACE SOPB = d_opb PORT GPIO_IO = sw_pin PORT OPB_Clk = clk_40mhz END BEGIN opb_intc PARAMETER INSTANCE = intc PARAMETER HW_VER = 1.00.c PARAMETER C_BASEADDR = 0x0000A400 PARAMETER C_HIGHADDR = 0x0000A4FF PARAMETER C_IRQ_IS_LEVEL = 0 BUS_INTERFACE SOPB = d_opb PORT OPB_Clk = clk_40mhz PORT Intr = bar_int_Intr PORT Irq = mblaze_int END BEGIN opb_interrupt_generator PARAMETER INSTANCE = bar_int PARAMETER C_BASEADDR = 0x0000A600 PARAMETER C_HIGHADDR = 0x0000A60F BUS_INTERFACE SOPB = d_opb PORT opb_clk = sys_clk PORT Interrupt = bar_int_Intr END BEGIN opb_bram_if_cntlr PARAMETER INSTANCE = pk_mem PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0x00008000 PARAMETER C_HIGHADDR = 0x0000FFFF END "seb" <sebastien.longueville@fr.thalesgroup.com> wrote in message news:ee878f6.2@webx.sUN8CHnE... Which EDK version do you use ? Could you paste your MHS file ?Article: 71653
rickman wrote: > starfire wrote: > >>Are there any FPGA parts available today that can contain a 32-bit, >>free-running counter running at 1GHz and a 32-bit storage register to take a >>snapshot of the count and read it to a slower external interface? >> >>The Xilinx Virtex II Pro seems to go up to about 325MHz... > > > I am surprised that no one has mentioned that you can pipeline a counter > to get much higher speeds. This takes more logic and your capture > registers must also be pipelined, but you can get much higher speeds > this way. Each bit of the counter has two FF outputs, one is that bit > of the count and the other is the carry out to the next stage. So each > bit of the counter will be one clock behind the next lower bit. It only > requires a single stage of carry propogation, so longer counters do not > run slower. This will run at about the same speed as a toggle FF. > > > Ci-1 ---- ---- > -------| & |--------|D Q|--- Ci > +---| | | | > | ---- clk---|> | > +------------+ ---- > ---- | > |D Q|---+-------- Bi > clk | | > -------|> | > ---- Well spotted. One key to pushing FPGAs is you can trade logic for speed, and as these devices have a ton of registers anyway, it does not matter if you use x8 or x16 the possible minimum number, if it means you can get to x4 the time precision. -jgArticle: 71654
Peter Alfke wrote: > I think your safest bet is to sample the input with four staggered 250 MHz > clocks, feeding four shift registers.Then differentialte the edges and move > them into a common 250 MHz clock domain. Or you use 8 phases for an even > safer circuit. Virtex-II can adjust the clock in 50 ps increments, and 250 > MHz is reasonable, while 125 MHz is easy, and definitely guaranteed to work. > You can capture the data, store the arrival time of 512 input pulses in a > BlockRAM and read the data out at your convenience. > The trick of using MGTs has not been proven yet, but this thread rekindled > my interest... Good to hear that :) - thinking aloud... What about a design that uses all the tricks, to push time-resolve as far as possible ? ( with maybe some FPGA family splits ) : * Pilelined counter (rickman) - what about a pipelined Gray counter ? * Multiple Phase counters/captures x4 is simplest, x8 is using more resource. What is the limit - x16 / x32 ... ( 'limit' would be when the routing/delay/capture uncertainty jitter meets the minimum time resolve - tho like ADCs, you can generate LSB that needs further averaging/filtering to be usefull ) With simple phased clocks, you can syncronise the sample/unknown pulse in each domain, which allows binary pipeline capture. Gray counters would need post-conversion for maths, but they do avoid the aperture effects of the capture pulse arriving, and so they open the option of fractional LSB extension via clock-capture & delay lines. -jgArticle: 71655
How to run the software? I downloaded it and double clicked it, all I saw is a command window come and go, what am I missing? "Adrian" <adrian@nospam.com> wrote in message news:4104F20D.4090004@nospam.com... > Hi all, > > > I have just made the last release 0.7 of the freeware WinFilter > available on the web. > http://www.winfilter.20m.com > > WinFilter is a software tool provided as freeware to design digital > filter. A GUI makes it very user friendly. This software can design as > well IIR filters as FIR filters and can generate the C and VHDL code. > > The filter coefficients are now quantizied in float, 16-bit or 8-bit. > FIR filter are now synthezis in VHDL (speed or size optimization) with a > Resources Usage Estimation. > > Cheers, > Adrian > > > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- > http://www.newsfeeds.com - The #1 Newsgroup Service in the World! > -----== Over 100,000 Newsgroups - 19 Different Servers! =-----Article: 71656
It's not just down, I get a redirect to some BS search site. Hacked, down, or is it just me? Thanks, SteveArticle: 71657
Joseph H Allen wrote: > Maybe they forgot to pay their domain name registration bill? Anyway the > IP address works: http://193.189.173.98 > > In article <ce4e3h$pj6$1@grandcanyon.binc.net>, > Steve <nospam@bit.bucket> wrote: >>It's not just down, I get a redirect to some BS search site. Hacked, >>down, or is it just me? >> >>Thanks, Steve The IP address works. Indeed they have been spoofed and have more info about it in one of their forums. Thanks, SteveArticle: 71658
Maybe they forgot to pay their domain name registration bill? Anyway the IP
address works: http://193.189.173.98
In article <ce4e3h$pj6$1@grandcanyon.binc.net>,
Steve <nospam@bit.bucket> wrote:
>It's not just down, I get a redirect to some BS search site. Hacked, down,
>or is it just me?
>
>Thanks, Steve
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 71659
etvive@wanadoo.es wrote:
> Hello, I´m a Spanish student and i need to program a Hitachi LCD using
> a Celoxica RC100 Spartan II and I can't do that the code show nothing
> in the display. If somebody know how program it please tell me. I put
> my code to all can see what i'm doing.
>
> Thanks.
>
> *******************************************************************************
> *******************************************************************************
> /*inculde standard header file*/
> #include <stdlib.hch>
>
>
> #ifdef DEBUG
>
> /*set up a dummy clock*/
> set clock = external "P1";
>
> #else
>
> #define RC100_BOARD
> #define RC100_CLOCK_DIVIDE 4
> #include <rc100.hch>
>
> #endif
> /***********************************************************************************************/
>
>
>
> /* Definimos una serie de señales necesarias para el manejo */
> unsigned int 8 Datos; // 8 lineas de datos
> unsigned int 1 EN; // Linea de Enable
> unsigned int 1 RS; // Linea de Selector de Registros
> unsigned int 1 RW; // Linea de Lectura/Escritura
> unsigned int 8 AAC; // Acumulador, solo usamos el bit 7 del mismo
> unsigned int 8 A; // Donde guardamos lo que vamos a mostrar por el LCD
> unsigned int 8 posicion; // Variables que usamos cuando queremos mover
> el cursor
> unsigned int 1 salir;
> unsigned int 1 condicion; // Condicion para leer/escribir en el bus de
> datos
> unsigned int 8 x; // Variable que usamos en las operaciones de
> leer/escribir del bus de datos
> unsigned int 1 Z; // Variable que usamos para salir del buscle de
> Wait_LCD()
>
> // Variables a usar en los delays
> unsigned int 8 TIEMPO1;
> unsigned int 8 TIEMPO2;
>
>
> unsigned int 1 LUZ; // luz del display
>
> /***********************************************************************************************/
> /******************ASIGNACION DE PINES A LAS DIFERENTES SEÑALES
> USADAS**************************/
>
>
> #ifndef DEBUG
>
> /* Asignamos los pines a las señales declaradas con anterioridad */
> // Datos ==> 8 pines ; Es de entrada/salida por lo que hay que
> declararse 2 buses
> /* Bus bidireccional de entrada y salida, cuando enable es 1 escribe
> "write" en los pines
> indicados, write contendra el valor a enviar a los pines,
> cuando quiera leer los hara
> de BiBus.read y leera los datos de los pines*/
>
>
> interface bus_ts(unsigned int 8 read) BiBus(unsigned int write = x,
> unsigned 1 enable = condicion)
> with {data =
> {"W18","AA20","Y18","V17","AA19","AB20","W17","V13"}};
>
>
> /* En las señales de control siempre se escribe por lo que los buses
> de las mismas basta
> con que sean de salida */
> // EN ==> 1 pin ;
> interface bus_out() bus_en(unsigned int 1 en_out = EN) with {data =
> {"Y13"}};
> // RS ==> 1 pin ;
> interface bus_out() bus_rs(unsigned int 1 rs_out = RS) with {data =
> {"AA13"}};
> // RW ==> 1 pin ;
> interface bus_out() bus_rw(unsigned int 1 rw_out = RW) with {data =
> {"AB13"}};
> // Luz ==> 1 pin
> interface bus_out() bus_lz(unsigned int 1 lz_out = LUZ) with {data =
> {"W13"}};
>
> #endif
>
> /***********************************************************************************************/
>
> /* Definimos las operaciones del LCD */
> // Macros para la temporizacion de los delays
>
> static macro proc espera2 (time)
> {
> unsigned 64 i;
>
> for (i=0; i<(time/1000000)*80000000;i++)
> delay;
>
> }
>
>
> static macro proc espera (time)
> {
> unsigned 64 i;
>
> for (i=0; i<(time/1000)*80000000;i++)
> delay;
> }
>
>
>
> macro proc Init_LCD ()
> {
> // Modo 8 bits
> #ifndef DEBUG
> RW = 1;
> EN = 1;
>
> RS = 0;
>
> condicion = 0;
>
> x = 0x38;
>
> condicion = 1; // Escribimos en el bus de datos en valor de x
>
> EN = 0;
>
>
> espera2(100);
>
> EN = 1;
>
> RS = 0;
>
> condicion = 0;
>
> x = 0x0e;
>
> condicion = 1; // Escribimos en el bus de datos el valor de x
>
> EN = 0;
>
>
> espera2(100);
>
>
> EN = 1;
>
> RS = 0;
>
> condicion = 0;
>
> x = 0x06;
>
> condicion = 1; // Escribimos en el bus de datos el valor de x
>
> EN = 0;
>
>
> espera2(100);
> #else
> EN = 1;
> RS = 0;
> Datos = 0x38; // Movemos 0x38 a Datos
> EN = 0;
> espera2(100); // Rutina que espera 40microseg
> EN = 1;
> RS = 0;
> Datos = 0x0e;
> EN = 0;
> espera2(100); // Rutina que espera 40microseg
> EN = 1;
> RS = 0;
> Datos = 0x06;
> EN = 0;
> espera2(100); // Rutina que espera 40microseg
> #endif
> }
>
> macro proc Clear_LCD ()
> {
> // Modo 8 bits
> #ifndef DEBUG
> RW = 1;
> EN = 1;
>
> RS = 0;
>
> condicion = 0;
>
> x = 0x01;
>
> condicion = 1; // Escribimos en el bus de datos el valor de x
>
> EN = 0;
>
>
> espera(10);
> #else
> EN = 1;
> RS = 0;
> Datos = 0x01;
> EN = 0;
> espera(8); // Rutina que espera 1,64mseg
> #endif
> }
>
> macro proc Write_Text (car)
> {
> // Modo 8 bits
> #ifndef DEBUG
> EN = 1;
>
> RS = 1;
>
> RW = 0;
>
> condicion = 0;
>
> x = car;
>
> condicion = 1; // Escribimos en el bus de datos el valor de x
>
> EN = 0;
>
>
> espera(10);
> #else
> EN = 1;
> RS = 1;
> RW = 0;
> Datos = car;
> EN = 0;
> espera2(8); // Rutina que espera 1,64mseg
> #endif
> }
>
> macro proc Cursor_Pos (linea, pos)
> // Operacion adicional para poder situar el cursor en la posicion que
> queramos
> /* Sinceramente no se si esto funcionara bien */
> {
> #ifndef DEBUG
> EN = 1;
>
> RS = 0;
>
> if (linea == 1)
> {posicion = pos;} // 0@pos
> else if (linea == 2)
> {posicion = 0x04 @ (pos<-4);} // Nos quedamos con, los ultimos 4
> bits, pues los
> // 4 primeros no los necesitamos y concatenamos con
> // un 4; No estoy seguro de que esto sea asi!!!!????
> else
> delay; // Otro valor distinto de 1 ó 2 no es válido, por lo que no
> hace nada
> condicion = 0;
>
> x = 0x80 + posicion;
> condicion = 1; // Escribimos en el bus de datos el valor de x
>
> EN = 0;
>
> // Wait_LCD();
> espera(8); // Rutina que espera 1,64mseg
> #else
> // Linea solo puede valer 1 ó 2 y posicion de 0 a 15
> EN = 1;
> RS = 0;
> if (linea == 1)
> {posicion = pos;} // 0@pos
> else if (linea == 2)
> {posicion = 0x04 @ (pos<-4);} // Nos quedamos con, los ultimos 4
> bits, pues los
> // 4 primeros no los necesitamos y concatenamos con
> // un 4; No estoy seguro de que esto sea asi!!!!????
> else
> delay; // Otro valor distinto de 1 ó 2 no es válido, por lo que no
> hace nada
> Datos = 0x80 + posicion; // 80h, instruccion de "Set Cursor
> Position", + posicion
> // en la linea, esta va de 0 a 15
> EN = 0;
> // Wait_LCD();
> espera(8); // Rutina que espera 1,64mseg
> #endif
> }
>
> void main(void)
> {
>
> #ifndef DEBUG
> LUZ = 1;
> #endif
>
> /*Sacamos el init y el clear fuera del bucle*/
> Init_LCD();
> Clear_LCD();
>
> // Programa de ejemplo que escribe en el LCD "Hello_World"
>
> A = 0b01001000; // Valor de la "H" en binario; Para pasarlo como
> letras tengo que definir
> // el tipo como char, pues como integer, aun poniendo la
> almoadilla, falla
> Write_Text(A);
> }
Hi
in Init_LCD after #else, don't you need some RW control ??
The Lcd display I have used has a init flow like this
enable
write 0x30 // don't check busy flag
delay
write 0x30 // don't check busy flag
delay
write 0x30 // don't check busy flag
write 0x38 // check busy flag
--
Thomas
registered user number 350300 http://counter.li.org/
Article: 71660
I'm new to fpga world, I've worked with DSPs for years and now i'm
moving to fpga interested for their high rate count potential (high energy
physics) .
I think that the limit will be the jitter as said jim.
Anyone knows the max rate that could be achieved with the Spartan 3
family?
--
Luis Vaccaro
"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:02gNc.497$zS6.75093@news02.tsnz.net...
> Good to hear that :) - thinking aloud...
> What about a design that uses all the tricks, to push time-resolve as
> far as possible ? ( with maybe some FPGA family splits ) :
> * Pilelined counter (rickman) - what about a pipelined Gray counter ?
> * Multiple Phase counters/captures x4 is simplest, x8 is using more
> resource. What is the limit - x16 / x32 ...
> ( 'limit' would be when the routing/delay/capture uncertainty jitter
> meets the minimum time resolve - tho like ADCs, you can generate LSB
> that needs further averaging/filtering to be usefull )
>
> With simple phased clocks, you can syncronise the sample/unknown pulse
> in each domain, which allows binary pipeline capture.
> Gray counters would need post-conversion for maths, but they do avoid
> the aperture effects of the capture pulse arriving, and so they
> open the option of fractional LSB extension via clock-capture & delay
lines.
>
> -jg
>
>
Article: 71661Hello everybody, I am not new to the world of FPGAs but have not found enough literature regarding the SRAMs used for configuration. I need some inputs, help or pointers(papers, articles) from the FPGA community regarding these. There are very few literature relating to this(May be I am not looking in the right places). 1. Are these SRAM cells arranged in a big nxn array like normal SRAM memory, or they are in small chunks of memories distributed all over the FPGA layout. 2.Are they physically placed adjacent to their corresponding CLB/Switch boxes. 3. As interconnects are fixed after configuration i guess they should always be read only mode, hence should be different from LUTs SRAM cells. Your inputs will really be helpful to me. regards --rajArticle: 71662
Why can't i download it? There's always an error such as "can't open the website..."! Have you got an idea? Thanks.Article: 71663
http://www.geocities.com/leon_heller "phuture_project" <phuture_project@yahoo.fr> wrote in message news:25fe518f.0407262320.8f139a5@posting.google.com... > Why can't i download it? There's always an error such as "can't open > the website..."! Have you got an idea? Thanks. There are two downloads, one works and one doesn't. Leon -- Leon Heller, G1HSMArticle: 71664
It looks good. Try to get a PCI design example from Avnet to underline differencesArticle: 71665
Jim Granville <no.spam@designtools.co.nz> wrote: > What about a design that uses all the tricks, to push time-resolve as > far as possible ? ( with maybe some FPGA family splits ) : > * Pilelined counter (rickman) - what about a pipelined Gray counter ? You could just as well use a shift register for the lower 4 bits of the counter (16 FFs), and use the pulse from the last FF to increment a (16x slower) normal counter. *Somehow*. > * Multiple Phase counters/captures x4 is simplest, x8 is using more > resource. What is the limit - x16 / x32 ... > ( 'limit' would be when the routing/delay/capture uncertainty jitter > meets the minimum time resolve - tho like ADCs, you can generate LSB > that needs further averaging/filtering to be usefull ) The most obvious limit here would be the amount of clock resources - global clock lines (I suppose you don't want to use local clocks), and to a lesser degree DCMs. -gArticle: 71666
jakespambox@yahoo.com (Jake Janovetz) wrote in message news:<d6ad3144.0406171545.68f3e376@posting.google.com>... > (I'm not sure why, but Google apparently loses about 50% of my posts, > so I'll try this again) > > I have a few modules that I would provide to customers. They are all > quite simple, but by not providing Veriog/VHDL I shelter them from the > implementation details and possible warnings that would come from > synthesis. So, I'd prefer to provide library "objects" in NGC format. > > Most of the modules are 'internal' (not requiring IOBs), but one needs > to map to IO pins, including an 8-bit bidirectional bus. If I -don't- > include IOBs in the module, the parent design synthesizes OBUFs for > the bidir bus and completely ignores the inputs. If I manually map > the OBUFTs within the module, I get complaints during parent synthesis > because apparently the parent is adding OBUFs which compete with the > OBUFTs in the module. > > I'd prefer a solution which requires as little 'extra' work on the > parent side of things, but would appreciate any suggestions. > > Cheers, > Jake Using .ngc files for sub-modules would be a good solution - not only in your case !! But problems arises soon after you try it - not only with the iobufs: i.e.: how do you want to provide a 'good' simulation-netlist? backannotating your netlist to a vhdl-netlist using "ngdbuild" and "netgen" results in a very poor performance of your simulation, because of the timing-information within that simulation-netlist driving modelsim 'almost' crazy... Any tips from "xilinx", how to use this interesting design-flow? Cheers JokoArticle: 71667
I set it in S/W setting->Processor and Driver Parameters-> CORE_CLOCK_FREQ_HZ. But I can not prove Microblaze work in that frequence. How can I set it and prove it. Thank you.Article: 71668
"Steve" <nospam@bit.bucket> wrote in message news:ce4k55$r25$1@grandcanyon.binc.net... > Joseph H Allen wrote: > > > Maybe they forgot to pay their domain name registration bill? Anyway the > > IP address works: http://193.189.173.98 > > > > In article <ce4e3h$pj6$1@grandcanyon.binc.net>, > > Steve <nospam@bit.bucket> wrote: > >>It's not just down, I get a redirect to some BS search site. Hacked, > >>down, or is it just me? > >> > >>Thanks, Steve > > The IP address works. Indeed they have been spoofed and have more info about > it in one of their forums. > > Thanks, Steve It's back now. They say it was due to server upgrades (you'd think they would have a temporary server).Article: 71669
Gerd wrote: > Jim Granville <no.spam@designtools.co.nz> wrote: > > >> What about a design that uses all the tricks, to push time-resolve as >>far as possible ? ( with maybe some FPGA family splits ) : >>* Pilelined counter (rickman) - what about a pipelined Gray counter ? > > > You could just as well use a shift register for the lower 4 bits of the > counter (16 FFs), and use the pulse from the last FF to increment > a (16x slower) normal counter. *Somehow*. Yes, you can use prescaler schemes, which can be shift register / Johnson counters, but that presents problems on capture. > >>* Multiple Phase counters/captures x4 is simplest, x8 is using more >>resource. What is the limit - x16 / x32 ... >>( 'limit' would be when the routing/delay/capture uncertainty jitter >>meets the minimum time resolve - tho like ADCs, you can generate LSB >>that needs further averaging/filtering to be usefull ) > > > The most obvious limit here would be the amount of clock resources - > global clock lines (I suppose you don't want to use local clocks), and to > a lesser degree DCMs. The DCMs look to have all the nice logic, but a rather limited number of taps for this type of time-extension (pity). Their advantage is they are there already, and are easy to deploy, and if this is your prime usage, who cares if all the DCMs are used ?. You can, of course, make a similar fine-time device using the FPGA itself, but that becomes a much more process and tool dependant path. But it would be interesting, and may approach 100ps in resolution. -jgArticle: 71670
wjbonline@126.com wrote: > I set it in S/W setting->Processor and Driver Parameters-> > CORE_CLOCK_FREQ_HZ. > But I can not prove Microblaze work in that frequence. > How can I set it and prove it. > Thank you. The frequency the MicroBlaze runs at can not be easily changed in EDK. The setting in the S/W-settings is just a pointer to tell the software what speed the CPU runs at, so that e.g. sleep() knows how many cycles it has to wait for a second. But the frequency the CPU actually runs at is determined by the clock you supply it with, which is usually generated by an oscillator on your board (maybe it's multiplied by a DCM inside the FPGA). cu, SeanArticle: 71671
Hi,
Is there any place where I can find a sample template PCI device
driver for the "PCI card with ARM9 processor" Or can anybody mail me
the skeletal driver of the PCI driver. I am new and have to write a
device driver for a PCI based device on OSE RTOS.
Thanks in advance,
Chanemou
Article: 71672Jim Granville <no.spam@designtools.co.nz> wrote: > Yes, you can use prescaler schemes, which can be shift register / > Johnson counters, but that presents problems on capture. Indeed, but not that big I guess. > > The most obvious limit here would be the amount of clock resources - > > global clock lines (I suppose you don't want to use local clocks), and to > > a lesser degree DCMs. > The DCMs look to have all the nice logic, but a rather limited number > of taps for this type of time-extension (pity). > Their advantage is they are there already, and are easy to deploy, > and if this is your prime usage, who cares if all the DCMs are used ?. Emphasis on 'to a lesser degree'. Even the small devices have 4 DCMs, each of which should supply you with four clocks (0/90/..). Starting with the 2vp20 you get 8 of them, but by then you are already running out of global clock nets (8/16). > You can, of course, make a similar fine-time device using the FPGA > itself, but that becomes a much more process and tool dependant path. > But it would be interesting, and may approach 100ps in resolution. It does. "Process dependance" is a really nice understatement *g* I'm thinking more along environmental conditions, the exact placement you choose, etc. But again, it's not much help if you can't distribute your clocks. "Tools" are down to fpga_editor & co, too. regards, -gArticle: 71673
ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0407260010.5bfa0c02@posting.google.com>... > Hi newsgroup people, > > does someone know where to find some information about an Altera Cyclone Memory > Evaluation Board for DDR SDRAM ? > > The only board I could find is the Lancelot from www.fgpa.nl > Are there other boards? > > Thank you for your help. Sorry, I mean the Twister board ...Article: 71674
raj wrote: > > Hello everybody, > > I am not new to the world of FPGAs but have not found enough > literature regarding the SRAMs used for configuration. > I need some inputs, help or pointers(papers, articles) from the FPGA > community > regarding these. There are very few literature relating to this(May be > I am not looking in the right places). > > 1. Are these SRAM cells arranged in a big nxn array like normal SRAM > memory, or they are in small chunks of memories distributed all over > the FPGA layout. Physically they are scattered all over the chip. Each bit of memory controls a single transistor or mux input in the chip. The (pass) transistors are used to control routing or are used in the LUT ram mux. The muxes are used inside the logic elements to connect different inputs and outputs to provide the exact configuration of logic and FFs that you need. > 2.Are they physically placed adjacent to their corresponding > CLB/Switch > boxes. Yes, or even integrated. > 3. As interconnects are fixed after configuration i guess they should > always be read only mode, hence should be different from LUTs SRAM > cells. In reality they don't typically distinguish between routing and LUT config memory. Both can be read back. This is useful for high reliability systems where the device is read back to verify the configuration has not changed due to electrical noise and/or radiation. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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