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>If your input clock (to the FPGA) is connected to an IBUFG (a clock-capable >IOB), then to a DLL or DCM, then to a BUFG (with the output of the BUFG >connected to the DLL/DCM's feedback port), then the edges of your input >clock will be coincident with the clock edges on the FPGA's internal clock >net (i.e., the output of the BUFG). This is known as "de-skewing" an input >clock. This clock net can be used to clock the IOB registers -- and when you >do this, the timing relationship, at the IOB's register input, is known with >respect to your external clock. This is critical when your data rate is >fairly high. Good point. Thanks. Note that any delay in the clock distribution turns into hold time requirements at the input to the IOB. Hold times are evil. They hurt even if the clock is not running fast. Older Xilinx chips had a delay in the IOB that was long enough to cover that hold time, and an option to bypass it in order to reduce the setup time. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 71176
Hello, There is a module provided online at Xilinx website for CLOCKGEN. In the EDK tools, when you perform synthesis it will create a top level VHDL code for the entire FPGA, that includes Microblaze, OPB, and your own design, etc. The clock going into this top level is the sys_clk, and this clock is going through a BUFG (inserted by EDK) and becomes sys_clk_s in the top level VHDL. The top level shows that this sys_clk_s is driving all the peripherals (i.e. Microblaze and OPB). In order to generate a clock for the external ZBT-memory, a "memory_27mhz" clock is generated by this CLOCKGEN module. My questions are: 1) Should I drive this CLOCKGEN module using this "sys_clk_s"? Note: In order to get the EDK working, the IBUFG (MASTER_CLOCK) in the CLOCKGEN needs to be removed manually, because there is one inserted already by EDK as mentioned above. 2) If #1 is correct, then is the "clk_27mhz" after the DCM would be exactly the same as "sys_clk_s" that enters the CLOCKGEN? 3) In #2 is correct, is it okay to drive my own logic (not the Microblaze stuff or other peripherals) using the "clk_27mhz"? You can reference page 18 of the MicroBlaze and Multimedia Development Board User Guide - there's a good diagram of the Clock Generator Module: http://www.xilinx.com/products/boards/multimedia/docs/UG020.pdf Any help is much appreciated! DavidArticle: 71177
>What is an input for one chip of the bus is an output for another one. >So : > Why does t_val need to be min 2ns ? For the one that samples the signal, t_h must be 0ns. > Why max 11ns ? Since setup time is min 7ns ... > Also, I suppose that the output signal that must be set within 2ns->11ns will only be sampled by the receiver side at the next clock cycle. The differences in times from what you might quickly calculate cover two areas. One is clock skew between the chips. The other is the time for the signal to get from one chip to the other. With several chips on a "bus", that can be a lot longer than the simple speed of light delays. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 71178
Hal Murray wrote: >>What is an input for one chip of the bus is an output for another one. >>So : >>Why does t_val need to be min 2ns ? For the one that samples the signal, t_h must be 0ns. >>Why max 11ns ? Since setup time is min 7ns ... >>Also, I suppose that the output signal that must be set within 2ns->11ns will only be sampled by the receiver side at the next clock cycle. > > > The differences in times from what you might quickly calculate cover > two areas. One is clock skew between the chips. The other is the time > for the signal to get from one chip to the other. With several chips > on a "bus", that can be a lot longer than the simple speed of light delays. > Ok, so that means that the output of my FPGA must be stable for at least 2ns after receiving the clock and then change before 11ns after clock. How can I ensure that in my VHDL code ... Sylvain MunautArticle: 71179
Hi, Has anybody managed to get the C16 processor from opencores.org to function correctly? I am trying to use it with a Digilent board with a Spartan IIe XC2S300E and Xilinx tools version 6.2.03i. The code required modification to port it to this board and it simulates fine with Modelsim but when the code executes it ignores even simple instructions such as JUMP. The program counter just keeps incrementing. I can see that the instructions are in memory OK. Its as if the Xilinx tools are not synthesizing the VHDL correctly. Any hints will be welcome. thanks KevinArticle: 71180
On Fri, 09 Jul 2004 09:16:06 -0700, Austin Lesea wrote: > Dan, > > Simulate it. > > I doubt seriously that picking off the signal before or after a resistor > at the receiver will make any difference at all (after all, the receiver > has nearly infinite input impedance, and about 7-8 pF of capacitive > loading, so what does a 82 ohm resistor to a 7 pF cap look like? not > much I assure you). > > As for setting the DCI resistance, use 82 ohm, or 33 ohm reference > resistors to set the DCI series drive impedance to 82 or 33 ohms. > > I would simulate it in Hyperlynx using the various IBIS models fromt he > different vendors to prove that it works with high and low Vcc, and with > fast and slow process corners. > > A standard is a starting point. Either meet it exactly, and not worry, > or simulate what you waht to do differently to prove it will always work > the way you intend it to. > > Your choice. By the way, I even simulate a standard interface, as I do > not trust that the standard's body could anticipate every possible use > of their precious standard, or that every vendor really 'met' the > standard when combined with the other vendors in the design. > Hyperlynx seemed like a good tool, but IIRC it didn't handle cables and connectors very well. The best thing you can do on an ATA interface besides all the resistors is to use the 80 conductor ultra-ATA cables. The extra return lines really help. Obviously keep the ATA cable as short as possible. If you can only put one device on the cable at the far end. The ATA standard termination scheme is really ad-hoc, it was never really addressed until the standard started to push the speed envelope. As for the DCI it does work, but my experience it's a real power hog. We had a 64-bit DDR interface and turned it on for a trial, and what used to be only a moderately warm FPGA turned into a burn-your-finger cooker.Article: 71181
Hello :)
I have board with Altera stratix FPGA. Because of board
design mistake, MSEL[2:0] pins are always logic 1. I can not cut
or modify because tarce are not visible (burried).
Can i use this board? if yes what configurtaion i should use.
can i use JTAG configuration?
Thanks
Article: 71182Hi all, I need to dynamically reconfigure the pin connections. For example, say, I have a port in my code which is attached to pin H3 of the virtex-2 chip. Now, I want to reconfigure it using ICAP to attach to pin G3. Did anyone do anything of this sort before? I will be thankful if someone can help me on this? Thanks, RamtilakArticle: 71183
Is EDK purchase neccessary to use the microblaze.zip file? I am a hobbiest and cannot afford to purchase EDK. Thanks. Pratip Shalin Sheth <Shalin.Sheth@xilinx.com> wrote in news:ccp2b6$oh41@cliff.xsj.xilinx.com: > The MicroBlaze zip file on the web site includes an OPB VGA character > mapped core with software drivers to use the core. The MicroBlaze > Master system also includes a FSL PS/2 keyboard core with drivers. > > The web site with the reference designs is: > http://www.xilinx.com/products/spartan3/s3boards.htm > > Shalin- > > Hank wrote: >> "Hank" <nospam@nospam.com> wrote in message >> news:_XHHc.43876$qw1.43300@nwrddc01.gnilink.net... >> >>><snip> >>> >>>>There are zip files for two reference designs at the bottome of this >>>>page: >>>> >>>>http://www.xilinx.com/products/spartan3/s3boards.htm >>>> >>>>The MicroBlaze Master System file contains code for, among other >>>>things, a vga controller. I don't know if it's the same controller >>>>that's programmed into the board's config PROM. >>>> >>>>Seems pretty strange that the source files weren't on the CDs that >>>>came with the board. >>>> >>>>Bob Perlman >>>>Cambrian Design Works >>>> >>> >>>Hey Bob, >>> >>>Thanks, I will look at those files...I saw them earlier, but >>>thought/think >> >> they >> >>>are not what is on this starter kit board. There is no mention of >>>this board using the microblaze core. >>> >>> >> >> >> Actually, I think the zip files you mentioned might indeed be what I >> was looking for. Thanks Bob! >> >> Hank >> >> > >Article: 71184
I am using a library prepared for testbenching a future core by a core vendor. In some simulations, the library works fine, but in others it causes Modelsim to crash during a vsim. When it crashes, it gives a code of 211 which is a segmentation fault. The crash is total - Modelsim exits immediately, printing a stack trace to its stderr, but nothing to its main console. I believe the crashes may have something to do with how large the simulation is - simulation in a small design doesn't crash, but in a large design it crashes. Strangely enough, in one case the determining factor was how I vmap'd a library - if I had the complete absolute library path, it would crash, but if I gave it a relative path, it ran. I was later able to get this same testbench running with an absolute library path after eliminating two libraries I realized weren't being used (which is in part why I believe that design size is a factor). Modelsim support wasn't much help (as usual). Any suggestions for things that I might try? Will upgrading the PC (more memory) help the situation? Are there Modelsim settings that would help? I can also request that the core vendor recompile the core with certain options if that is advisable (although they will want to use the nodebug option to protect their IP). Thanks, DougArticle: 71185
Doug Miller wrote: > I am using a library prepared for testbenching a future core by a core > vendor. In some simulations, the library works fine, but in others it > causes Modelsim to crash during a vsim. When it crashes, it gives a code > of > 211 which is a segmentation fault. The crash is total - Modelsim exits > immediately, printing a stack trace to its stderr, but nothing to its main > console. Make sure you are using exactly the same revision of modelsim and OS to use the library that the vendor is using to compile it. > Any suggestions for things > that I might try? If this is a commercial application consider buying source code (maybe from another vendor) or writing your own. The inability to view, edit and trace code may hamper development and maintenance of your fpga image. > Will upgrading the PC (more memory) help the situation? More memory might speed up a working sim, but it is unlikely to fix a crashing one. The crash is most likely due to a bug in the model. It could be a windows or modelsim bug. > Are there Modelsim settings that would help? I can also request that the > core vendor recompile the core with certain options if that is advisable > (although they will want to use the nodebug option to protect their IP). Send all your files and a crash recipe to the core vendor. If the vendor needs your business he will make it work for you. -- Mike TreselerArticle: 71186
ndesi wrote: > Hello :) > > I have board with Altera stratix FPGA. Because of board > design mistake, MSEL[2:0] pins are always logic 1. I can not cut > or modify because tarce are not visible (burried). > > Can i use this board? if yes what configurtaion i should use. > can i use JTAG configuration? > > Thanks Well you didn't tell us what sort of configuration method you were intending to use and/or what configuration options exist (or not) on your board. Forgive me if I can't help there. I suggest RTFineM. Seriously, I will make a hopefully more useful comment. Have you considered drilling a well placed hole or two in your board to remove the undesired internal traces? I've used this method to deal with buried PCB mistakes. Even re-ground a drill bit to make a flat bottomed hole. A milling machine, to precisely guide the cut is ideal. Other times, a hole straight through the board can be done with a hand drill. Sometimes you have take a few steps backward and create more damage, but a few mod wires may be able to fix the new damage and original problem. Good Luck, SteveArticle: 71187
I am currently using Cypress programmable logic but they have announced some that some products will be discontinued. I am looking at the Xilinx 4.2i (obtained via Wakerly's book) I am wondering how the Xilinx chips supported by 4.2i are programmed. I am using the JTAG stuff from Cypress right now. Also, how extensive is the product support in 4.2i. Can "reasonably" big chips be programmed, etc. DaveArticle: 71188
I'm learning how to program FPGAs using Handel-C and an RC100 board. I've written code to simulate a direct digital synthesiser, but can't figure out how to get the video dac driver on the RC100 board to output the generated 8-bit sinewave to an oscilloscope. Any advice would be appreciated. Thanks, MeesArticle: 71189
"Jacek Wawrzaszek" <no.mail@no.spam> wrote in message news:<cc1qvf$jmd$1@atlantis.news.tpi.pl>... > > I didn't check the specs, but I saw some tiny FPGA boards > at www.fpga4fun.com > > J. Yeah, I looked at those, but they are just a little too big for what I need unfortunately. -DAGArticle: 71190
Hi All, I'm need to interface a Xilinx Virtex to a PCI Bus. The Xilinx PCI IP core is too costly for the volumes I will be building, so I'm looking at PCI controller chips. From experience can anybody recommend a vendor, such as Quicklogic, AMCC, Tundra, etc. Thanks, Andy.Article: 71191
"Jerker Hammarberg (DST)" wrote: > > > That depends entirely on your timing specs. If you have none, then > > they are not likely to be wrong ;) XST will be trying to make every > > path meet single clock timing. > > Sure! I have specified a clock period constraint, which I thought would > be enough. See further my reply to Philip. > > > As others have suggested, if it fails on startup, it could easily be > > the async reset vs. clock. I think you made two bad assumptions from > > the way you describe your initial state. You indicated you used > > "initial values by declarations". I don't think synthesis tools use > > initial values as reset values. I have never asked if XST does this > > or not since I don't depend on this. Accepted style is to put it > > explicitly in your hdl code like this... > > But this is a well documented feature in XST, see XST User guide, > Chapter 6, Initial Values. It says "When you give a register an initial > value in a declaration, XST sets this value on the output of the > register at global reset, or at power up.". So if the feature is there, > it must be OK to use it, and to skip explicit resets? Ok, if you are sure this works for XST, then that is ok. But it won't work with other synthesis tools which will make your code not portable. If you later want to use a better tool, you will have to go back and use the standard method on every signal you are initializing. Either way, if it is being reset, then that is covered. But this does not necessarily mean it will come out of reset correctly. Since the clock is async with respect to the reset, and the reset has variable delays throughout the chip, you can release reset on different parts of the chip (including different FFs in the same state machine) on different clock cycles. One way to fix this is to make sure the global reset path delay is less than one clock cycle and to sync the reset to the global clock. I believe there is a config bit stream option to synchonize the end of reset with your global clock. Check the docs. This is something you will set when you generate the bit stream. I am not sure how to find out how long the reset delay paths are. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 71192
Hi I need to record XC3042 but the software I have is xilinx foundation 1.5 and it only record the XC3042A . The software I need is Xact 4.12 or 5.0 Could anyone somehow help me?Article: 71193
AndyAtHome wrote: > > Hi All, > > I'm need to interface a Xilinx Virtex to a PCI Bus. The Xilinx PCI IP > core is too costly for the volumes I will be building, so I'm looking > at PCI controller chips. > > From experience can anybody recommend a vendor, such as Quicklogic, > AMCC, Tundra, etc. I used a PLX chip a few years ago and had very little trouble with it. PCI was not so easy to learn, but otherwise it was no big issue. I would recommend that you use a PCI bus analyzer to help you debug your low level protocol. Or you might not need it if you are doing a simple memory mapped interface. We were doing DMA and needed all the help we could get since we didn't have much info on the disk controller bus master. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 71194
> > The 3000 series hasn't been supported for years. As for programing it in > > Linux, Linus was in grade school when the 3000s were current so you aren't > > going to find any Linux native tools that support them. However you should > > be able to run the old DOS based XACT tools under wine. > > I believe Foundation series 1.4, 2.1,...support the 3000 parts, and > they were window sw, nice tools but they are also obsolete. :( Hi You have the same problem I have the difference is that my component in XC3042 we have to get XACT 4.12 or 5.0, the foundation series only support the family XC3000A to up,if you get one of these programs please send me and if I get them I will send you It`s a shame what xilinx does to force to purchase of newer components and not putting in her website the old softwares In my case I`m a professor and received a donation of these components to iniciate the study of my students and we don`t have money to buy newer components Regards Thales BelchiorArticle: 71195
On Sun, 11 Jul 2004 21:09:20 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >AndyAtHome wrote: >> >> Hi All, >> >> I'm need to interface a Xilinx Virtex to a PCI Bus. The Xilinx PCI IP >> core is too costly for the volumes I will be building, so I'm looking >> at PCI controller chips. >> >> From experience can anybody recommend a vendor, such as Quicklogic, >> AMCC, Tundra, etc. > >I used a PLX chip a few years ago and had very little trouble with it. >PCI was not so easy to learn, but otherwise it was no big issue. I >would recommend that you use a PCI bus analyzer to help you debug your >low level protocol. Or you might not need it if you are doing a simple >memory mapped interface. We were doing DMA and needed all the help we >could get since we didn't have much info on the disk controller bus >master. I've also worked on boards with PLX chips on them. One (family of boards) in particular had a PLX PCI 9030 to bridge between the PCI and a simple synchronous local bus that went to a number of FPGAs. It didn't have amazing performance, but it was simple and worked. Regards, Allan.Article: 71196
Does anybody have experience with the Altium CircuitStudio 2004 product compared with Altera's MAX+PLUS II Baseline (or other such products) that he could share? BruceArticle: 71197
I've got an FIR design that runs out of FPGA memory in an ep1s60 when I set the data width to 24-bit (The design fits with a data width of 16-bit). However only 13% of the total memory is used. I assume the problem is that I have lots of smaller memories, and they cannot share the same memory blocks (M512, M4K, M-RAM). Can anyone who has experienced this problem share their strategies for dealing with this.Article: 71198
AndyAtHome <fpgadev@yahoo.com> wrote: : Hi All, : I'm need to interface a Xilinx Virtex to a PCI Bus. The Xilinx PCI IP : core is too costly for the volumes I will be building, so I'm looking : at PCI controller chips. : From experience can anybody recommend a vendor, such as Quicklogic, : AMCC, Tundra, etc. Look at the Opencore PCI Core -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 71199
Hi All, This may be a strange question .. I program 9 Xilinx Devices with the same bitstream file. But some of them behave differently from the others. Can anyone give me any suggestions on why this could be happening ? Is the problem internal to Xilinx (if i am on the edge of timing on some signals) or it is outside in the signals coming to them ? Any pointers will be really appreciated, Thanks, Adarsh
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Compare FPGA features and resources
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