Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On 20 Jul 2004 09:13:40 -0700, dhruvish@gmail.com (Drew) wrote: >Hi all, > >I need Open Collector Active-Low analog circuit's logical >representation. I am having pretty hard time putting it togather. I >used bidirectional tristated bus, but it doesnt solve my problem. >There are some contentions as I have to read what I write to the Bidir >Pin (always) and at some point the Bidir Pin works as an output too. Actually it should. An open collector (which would be for almost all fpgas) configuration can be modeled with a tri-state output which can be driven low or tri-stated, not driven-high. You should be able to use a regular tri-state bi-directional io to do what you need. Try this: module od_io(pad, in, oeb); inout pad; output in; input oeb; wire pad = oeb ? 1'bz : 1'b0; wire in = pad; endmodule this should map to a bi-dir io or you can instantiate one from your device's library.Article: 71501
There is a nice parametarizable MUX but how about a DEMUX ??? I have already implemented my own 1-bit 4-input DEMUX, but for the 8-bit 4-input version thought Altera would provide something... Thanks in advance, VadimArticle: 71502
In article <40fa495d_1@127.0.0.1>, Andrew Rogers <andrew@_NO_SPAM_rogerstech.co.uk> wrote: >Simon wrote: > >.... > >> This was after I'd 'upgraded' to something I thought would handle large >> amounts of memory well and synthesize/P&R faster... Oh well, back to >> windows :-( Xilinx now has the dubious honour of being the only company >> for which I maintain a Windows partition :-( >> >> Simon. > >I wonder how much Microsoft are paying Xilinx! After all Xilinx don't >release ISE WebPACK for Linux. Has anyone heard a REAL reason for Xilinx >not releasing WebPACK for Linux? > I think it's because they use that MainWin to port from Windows to Linux and there is a per-seat license charge they pay for it. They could have used Wine and Winelib to port from Windows to Linux for free, of course, and then we wouldn't be asking all these questions ;-) While the big EDA companies (that cater to ASICs) now consider Linux to be a first-class citizen, the FPGA vendors (and EDA companies that cater to FPGAs) still don't seem to know much about Linux. At least they've started porting to Linux, but they're still developing on Windows and porting to Linux (and other Unices) whereas the big guys are developing on Linux and porting to Windows (I know this is true at Mentor Graphics for example). The interesting thing is that if you're coming from the Windows world (as Xilinx is) all you know about are proprietary tools whereas when you're coming from the Linux world you tend to use cross-platform, open source tools from the start. So porting from Linux to Windows is fairly easy because you're probably using a cross platform GUI toolkit like Tk, gtk or perhaps Qt. When you're locked into Windows as your development platform, porting to Linux can be a pain (especially if you don't know about Wine/Winelib, and you probably wouldn't if you're coming from the Windows world). So, as someone else mentioned, it's not a conspiracy with Micro$oft so much as ignorance of the market and of the Linux world that leads to these problems. We need to educate the vendors about Linux and about what's possible (like we did the big EDA vendors several years ago). For example, Xilinx could save a lot of $$ if they didn't use MainWin for porting and used Wine/Winelib instead - perhaps they didn't know about that option - and as an added bonus their product would (of course) work under Wine. BTW: The other issue with getting the Xilinx tools to work under Wine is the Jungo parallel port driver. You may be able to get the development tools to work under Wine, but you won't be able to program any parts with Impact (unless something has changed very recently). PhilArticle: 71503
>Modern high-performance sub-150 nm conventional CMOS technology has leakage >currents that make that goal unattainable (by a long shot). >Such a requirement is not mainstream... A million to one may not be mainstream, but there is a lot of interest in low leakage parts where modest performance is adaquate. Think of all those battery operated gizmos. An AA cell is roughly 2800 mA hours. Suppose you use half the energy in idle current and the other half for real work, and want the system to run for a year on a battery. That's an idle current of 0.16 mA, for the whole system. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 71504
In article <WYsKc.451$h_3.116@newsfe6-gui.ntli.net>, Simon <news@gornall.net> wrote: >Andrew Rogers wrote: > >> >> I wonder how much Microsoft are paying Xilinx! After all Xilinx don't >> release ISE WebPACK for Linux. Has anyone heard a REAL reason for Xilinx >> not releasing WebPACK for Linux? > >Well, annoying though it is, I don't think it's a conspiracy :-) It's >probably a combination of: > > o Most Linux WebPack users will never contribute sufficient funds back >to Xilinx to make it worth their while. > > o They pay a per-seat licence for their officially-supported >foundation package on Linux to the GUI-library owners. They therefore >can't offer it as a download for WebPack. > >What it would probably take would be a large customer saying "we're >going to move to Altera/whoever unless you do the port before XXX", with >XXX being a realistic target in the future. At that point, there's a >commercial pressure to do the port, and Xilinx can take a view on >whether it's worth it. Even then, their view might be 'see that lake, >run and jump' :-) > >Another route for Xilinx to get their finger out would be if >Altera/whoever did it first - Xilinx wouldn't be far behind then, I'd >imagine, bragging rights and image are nowhere near as important as >commercial pressures, but they still count :-) > It's interesting that for the big EDA companies (Synopsys, Mentor, Cadence) the switch to supporting Linux happened several years ago and now Linux is probably the majority platform for most of them. Sure, it was easier for them to make the switch because they already did all their development on some flavor of Unix, but there was still inertia to overcome to get them to move to Linux. When serious customers started asking for Linux, they bagan to take notice. Now, just as then, It will take a lot of customer pressure to get the FPGA companies (and the FPGA EDA companies) to properly support Linux. As a Linux software developer who has done a bit of consulting I've seen several environments that were primarily Windows development houses. The people in these groups might be very good developers, but they have no idea of what exists in the Linux world (or the open source world in general). They tend to view it as if it were a dangerous foreign country that they want to keep their distance from. So what happens is that Linux developers have a hard time communicating with Windows developers (and vice-versa). Right now in Xilinx, I would bet that you've got a primarily Windows development culture. Sure they've made steps toward Linux-land, but they're very cautious steps. With time they'll discover that the Linux waters aren't shark-infested and they'll become more adventurous ;-) PhilArticle: 71505
In article <40fa5b5e_1@127.0.0.1>, Andrew Rogers <andrew@_NO_SPAM_rogerstech.co.uk> wrote: >Simon wrote: >> Andrew Rogers wrote: >> >>> >>> I wonder how much Microsoft are paying Xilinx! After all Xilinx don't >>> release ISE WebPACK for Linux. Has anyone heard a REAL reason for >>> Xilinx not releasing WebPACK for Linux? >> >> >> Well, annoying though it is, I don't think it's a conspiracy :-) It's >> probably a combination of: >> >> o Most Linux WebPack users will never contribute sufficient funds back >> to Xilinx to make it worth their while. > >Equally applicable to Windows WebPACK users in my opinion. I'll buy >FPGAs if the software is free, I'll buy nothing if the software isn't free. >> >> o They pay a per-seat licence for their officially-supported foundation >> package on Linux to the GUI-library owners. They therefore can't offer >> it as a download for WebPack. > >How about the command line tools; xst, map, par, bitgen, etc? That still won't help when it comes to programming devices. The Jungo parallel port driver doesn't work under Wine. PhilArticle: 71506
"Ed" <Ed@nospam.com> wrote in message news:cdjh0q$uvr$1@news8.svr.pol.co.uk... > Hi, > > Does anyone have any experience in programming Altera FPGA's? In particular > a FLEX8000. What development environment do you use and how much does it > cost? Do any free development environments exist for it (VHDL or Verilog)? > Also, is the programming hardware expensive? The free Quartus software you can download from the Altera web site doesn't support the FLEX 8000, which Altera describes as 'mature'. More recent devices are supported with VHDL and Verilog. You should use one of those. The ByteBlaster required for programming Altera devices is quite expensive at $150, but I made my own. Details are on my web site. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 71507
I am not arguing against Low Power. Yes, there would be a market for ultra-low-power battery-operated circuitry. But this requirement is, unfortunately, in conflict with the mainstream that cries for "cheaper, faster, and bigger (and earlier)". And the market is unmerciful... Peter Alfke ================================== > From: hmurray@suespammers.org (Hal Murray) > Newsgroups: comp.arch.fpga > Date: Tue, 20 Jul 2004 12:08:48 -0500 > Subject: Re: Spartan 3 termination question (DCI) > >> Modern high-performance sub-150 nm conventional CMOS technology has leakage >> currents that make that goal unattainable (by a long shot). >> Such a requirement is not mainstream... > > A million to one may not be mainstream, but there is a lot of > interest in low leakage parts where modest performance is > adaquate. > > Think of all those battery operated gizmos. > > An AA cell is roughly 2800 mA hours. Suppose you use half the energy > in idle current and the other half for real work, and want the system > to run for a year on a battery. That's an idle current of 0.16 mA, > for the whole system. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 71508
Hal, My wife has a talking pedometer. Neat. Keeps track of distance walked or run, calories, steps, time of day. Runs on hearing aid coin cells. Batteries last about 6 months. Whoops! Bad design. Should have skipped talking feature -- too much power added to the budget. I have a hand held radio. OK, standby current is 200 mA. Wow. Way too high. I like radios that need to be recharged less often than once a day. While transmitting, power can be as much as 2 amperes, but how much do you talk? Better design would have been an ultra low power receive mode, and leave all of the power for when you push to talk. Again, bad design. My kids have music players. Neat. Plays music for a really long time, never worry about batteries. Good design. Then we have a remote control (actually four of them). OK. Probably gets dropped too many times before the batteries go out. Good design. And, of course, everyone has a cell phone. Great. In town, batteries last up to a week with occasional use. If in a rural area, the batteries drain much faster (need the RF power to get out). Good design and compromise. Most folks have a digital camera. Varies tremendously with when you bought it. If it was one of the old ones, it ate batteries. Bad design. If it is one of the new ones, you almost do not care about batteries. Carrying around a spare battery is all you ever need, even on a week-long vacation. Good design. All of the above devices use uPs, ASICs or ASSPs because a FPGA is not cost effective at all in these tasks (volume too large). Reprogrammability doesn't add any value to any of the products. All of these products use much older technology CMOS processes tweaked for low power (high Vt's). So, what market even exists that needs reprogramability (as in FPGAs), AND also needs extremely low power? It isn't that I do not believe that there are no low power applications out there, it is that I need to be told which ones they are if I am to help provide products for them. Austin Hal Murray wrote: >>Modern high-performance sub-150 nm conventional CMOS technology has leakage >>currents that make that goal unattainable (by a long shot). >>Such a requirement is not mainstream... > > > A million to one may not be mainstream, but there is a lot of > interest in low leakage parts where modest performance is > adaquate. > > Think of all those battery operated gizmos. > > An AA cell is roughly 2800 mA hours. Suppose you use half the energy > in idle current and the other half for real work, and want the system > to run for a year on a battery. That's an idle current of 0.16 mA, > for the whole system. >Article: 71509
"Martin Thompson" <martin.j.thompson@trw.com> wrote in message news:u3c3m28dk.fsf@trw.com... > johnp3+nospam@probo.com (John Providenza) writes: > > I've embedded the place and route time (year, month, day, hour) in the > bitstream in the past as the USERCODE 0xyymmddhh > Neat!!Article: 71510
Phil Tomson <ptkwt@aracnet.com> wrote: ,,, : That still won't help when it comes to programming devices. The Jungo : parallel port driver doesn't work under Wine. I had some success with http://www.nahitech.com/jtag-en/ running with wine. Nahitafu will hopefully enable programming of more devices.. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 71511
Peter Alfke wrote: >>> Modern high-performance sub-150 nm conventional CMOS technology has >>> leakage currents that make that goal unattainable (by a long shot). >>> Such a requirement is not mainstream... Austin Lesea wrote: > Hal, > > My wife has a talking pedometer. Neat. Keeps track of distance walked > or run, calories, steps, time of day. Runs on hearing aid coin cells. > Batteries last about 6 months. Whoops! Bad design. Should have > skipped talking feature -- too much power added to the budget. > > I have a hand held radio. OK, standby current is 200 mA. Wow. Way too > high. I like radios that need to be recharged less often than once a > day. While transmitting, power can be as much as 2 amperes, but how > much do you talk? Better design would have been an ultra low power > receive mode, and leave all of the power for when you push to talk. > Again, bad design. > > My kids have music players. Neat. Plays music for a really long time, > never worry about batteries. Good design. > > Then we have a remote control (actually four of them). OK. Probably > gets dropped too many times before the batteries go out. Good design. > > And, of course, everyone has a cell phone. Great. In town, batteries > last up to a week with occasional use. If in a rural area, the > batteries drain much faster (need the RF power to get out). Good design > and compromise. > > Most folks have a digital camera. Varies tremendously with when you > bought it. If it was one of the old ones, it ate batteries. Bad > design. If it is one of the new ones, you almost do not care about > batteries. Carrying around a spare battery is all you ever need, even > on a week-long vacation. Good design. > > All of the above devices use uPs, ASICs or ASSPs because a FPGA is not > cost effective at all in these tasks (volume too large). > Reprogrammability doesn't add any value to any of the products. All of > these products use much older technology CMOS processes tweaked for low > power (high Vt's). > > So, what market even exists that needs reprogramability (as in FPGAs), > AND also needs extremely low power? > > It isn't that I do not believe that there are no low power applications > out there, it is that I need to be told which ones they are if I am to > help provide products for them. > > Austin Austin, You have already given some good examples, and also undelined an important point * First generation designs only have to work, second generation designs need to work properly * Here is another example of that : http://www.cypress.com/aboutus/press_release.cfm?objectid=B02B0D86-03E0-4485-945E4304605236AE Seems low power matters to Cypress, and their customers. Some small detail of saving a plug pack ? There was another company offering a bin-selected low power device, as it seems they also have customers for whom low power matters. Who was it now ..... ah, yes, here it is ... http://www.xilinx.com/prs_rls/silicon_spart/0478s3lp.htm and it says "While defining 'low power' is challenging, preliminary iSuppli estimates indicate that as much as $3 billion of the approximately $20 billion ASIC market could potentially shift to FPGAs if power consumption was reduced sufficiently." Sounds plausible to me. Seems iSuppli reckons there is a $3B answer to your question above? However it would seem there are two fundamentals against FPGAs in the chase for ASIC business. a) To compete the FPGA must be a couple of generations ahead b) They must compete on price/speed and power. Solving a) means they have moved the wrong way in leakage, so you can compete on price, and on speed, but fall rather behind on power efficency. Sure, 90nm ASICs are very expensive, but to compete with a 90nm FPGA, you do not need a 90nm ASIC. Costs at the 'back end' of 150-180nm could even drop, as flows mature, and the cost-recovery models follow the leading edge. There are ways to balance this : eg multiple oxides are now appearing, plus a MASK variant can have many fewer transistors, and lower loading means you have spare speed to trade for power. Also, a design can use another 'true low power' device and deploy complete power removal from the FPGA in sleep : then the comparison is [all in an ASIC] vs [PowerFrugaluC + FPGA] This combination can make rational engineering sense, but might have problems with FPGA vendor's marketing depts, so do not expect to see it strongly promoted any time soon :) -jgArticle: 71512
There are several methods to reduce power by a factor of two, and there may be tricks to get if down an order of magnitude ( i.e. factor 10). But to satisfy the applications that Austin enumerated that's not enough... So something has to be sacrificed: speed, low cost, complexity, versatility, sales volume, profit (or all of the above?) Peter Alfke ==================== > From: Jim Granville <no.spam@designtools.co.nz> > Organization: TelstraClear > Newsgroups: comp.arch.fpga > Date: Wed, 21 Jul 2004 10:26:14 +1200 > Subject: Re: Low Power Applications - enumerate > > Peter Alfke wrote: >>>> Modern high-performance sub-150 nm conventional CMOS technology has >>>> leakage currents that make that goal unattainable (by a long shot). >>>> Such a requirement is not mainstream... > Austin Lesea wrote: >> Hal, >> >> My wife has a talking pedometer. Neat. Keeps track of distance walked >> or run, calories, steps, time of day. Runs on hearing aid coin cells. >> Batteries last about 6 months. Whoops! Bad design. Should have >> skipped talking feature -- too much power added to the budget. >> >> I have a hand held radio. OK, standby current is 200 mA. Wow. Way too >> high. I like radios that need to be recharged less often than once a >> day. While transmitting, power can be as much as 2 amperes, but how >> much do you talk? Better design would have been an ultra low power >> receive mode, and leave all of the power for when you push to talk. >> Again, bad design. >> >> My kids have music players. Neat. Plays music for a really long time, >> never worry about batteries. Good design. >> >> Then we have a remote control (actually four of them). OK. Probably >> gets dropped too many times before the batteries go out. Good design. >> >> And, of course, everyone has a cell phone. Great. In town, batteries >> last up to a week with occasional use. If in a rural area, the >> batteries drain much faster (need the RF power to get out). Good design >> and compromise. >> >> Most folks have a digital camera. Varies tremendously with when you >> bought it. If it was one of the old ones, it ate batteries. Bad >> design. If it is one of the new ones, you almost do not care about >> batteries. Carrying around a spare battery is all you ever need, even >> on a week-long vacation. Good design. >> >> All of the above devices use uPs, ASICs or ASSPs because a FPGA is not >> cost effective at all in these tasks (volume too large). >> Reprogrammability doesn't add any value to any of the products. All of >> these products use much older technology CMOS processes tweaked for low >> power (high Vt's). >> >> So, what market even exists that needs reprogramability (as in FPGAs), >> AND also needs extremely low power? >> >> It isn't that I do not believe that there are no low power applications >> out there, it is that I need to be told which ones they are if I am to >> help provide products for them. >> >> Austin > > Austin, > You have already given some good examples, and also undelined an > important point > * First generation designs only have to work, second generation designs > need to work properly * > > Here is another example of that : > > http://www.cypress.com/aboutus/press_release.cfm?objectid=B02B0D86-03E0-4485-9 > 45E4304605236AE > > Seems low power matters to Cypress, and their customers. Some small > detail of saving a plug pack ? > > There was another company offering a bin-selected low power device, as > it seems they also have customers for whom low power matters. > Who was it now ..... ah, yes, here it is ... > > http://www.xilinx.com/prs_rls/silicon_spart/0478s3lp.htm > > and it says > > "While defining 'low power' is challenging, preliminary iSuppli > estimates indicate that as much as $3 billion of the approximately $20 > billion ASIC market could potentially shift to FPGAs if power > consumption was reduced sufficiently." > > Sounds plausible to me. Seems iSuppli reckons there is a $3B answer to > your question above? > > However it would seem there are two fundamentals against FPGAs in the > chase for ASIC business. > a) To compete the FPGA must be a couple of generations ahead > b) They must compete on price/speed and power. > Solving a) means they have moved the wrong way in leakage, so > you can compete on price, and on speed, but fall rather behind > on power efficency. > Sure, 90nm ASICs are very expensive, but to compete with a 90nm FPGA, > you do not need a 90nm ASIC. Costs at the 'back end' of 150-180nm could > even drop, as flows mature, and the cost-recovery models follow the > leading edge. > > There are ways to balance this : eg multiple oxides are now appearing, > plus a MASK variant can have many fewer transistors, and lower loading > means you have spare speed to trade for power. > > Also, a design can use another 'true low power' device and deploy > complete power removal from the FPGA in sleep : then the comparison is > [all in an ASIC] vs [PowerFrugaluC + FPGA] > > This combination can make rational engineering sense, but might have > problems with FPGA vendor's marketing depts, so do not expect to see > it strongly promoted any time soon :) > > -jg > >Article: 71513
Uwe Bonnes wrote: > Phil Tomson <ptkwt@aracnet.com> wrote: > ,,, > : That still won't help when it comes to programming devices. The Jungo > : parallel port driver doesn't work under Wine. > > I had some success with http://www.nahitech.com/jtag-en/ running with wine. > Nahitafu will hopefully enable programming of more devices.. > > Bye How about GtkJTAG from the same author? That runs on Linux, I have downloaded and compiled it. The downside is that in needs to run as root due to low level IO. But it should be possible to use the parport device driver. I am currently working on a modification to GtkJTAG (well, libjtag to be accurate) so that it uses the parport device driver. As my Spartan 3 kit hasn't arrived yet I haven't been able to test GtkJTAG. A seperate project aimed at Virtex: http://www.ddtc.dimes.tudelft.nl/~rene/xilinx-jtag.c As far as I can tell from XAPP188 this will also program Spartan2 devices and I can only guess that it may work for Spartan3. I can't find an XAPP for spartan3 configuration using JTAG. Regards AndrewArticle: 71514
Hi, Can anyone suggest how to assign a area constraint on a sub-module within my design? I dont care where the other sub-modules are as long as this particular sub-module is in the required area. I know we can assign a area constraint for the whole design. But, how to do it for a sub-module? Thanks in advance, RamtilakArticle: 71515
In article <KfiLc.322$YM6.78@newsfe4-gui.ntli.net>, Simon <news@gornall.net> wrote: >Phil Tomson wrote: > >> >> As a Linux software developer who has done a bit of consulting I've seen >> several environments that were primarily Windows development houses. The >> people in these groups might be very good developers, but they have no >> idea of what exists in the Linux world (or the open source world in >> general). They tend to view it as if it were a >> dangerous foreign country that they want to keep their distance from. So >> what happens is that Linux developers have a hard time communicating with >> Windows developers (and vice-versa). Right now in Xilinx, I would bet >> that you've got a primarily Windows development culture. Sure they've >> made steps toward Linux-land, but they're very cautious steps. With time >> they'll discover that the Linux waters aren't shark-infested and they'll >> become more adventurous ;-) > >Mmm, not sure I agree with that. Without wishing to be an apologist for >Xilinx (because basically I wish they'd get their act together and >support Linux as a tier-1 platform!), I don't think it's a 'unix/linux >is bad' attitude. They do support Suns, after all. Yes, but I suspect that their Solaris port is in the same shape as their Linux port. Also, I suspect that you can't program parts using Impact on Solaris either. My point was that they seem to be doing all of their initial development on Windows and then porting over to Linux (or Solaris) using MainWin and this, of course, shows. > >FWIW, I think it's a cost/reward thing. There's a large proportion of >people for whom the platform on which you code VHDL or verilog is >irrelevant. These people are more concerned with the end-product of >their design than the method of getting there, as all good designers >ought to be. Perhaps, but these days most designers coming to FPGAs from the ASIC world are used to running Linux (or perhaps Solaris) so they're not used to dealing with all of the virus problems that come with running Windows and they would prefer to not bother with them. Also, they may not want to have to take the time it takes to make their Windows box feel like 'home' (installing cygwin, scripting languages, etc.) > >The issue comes when you have to change OS to do XYZ for a while rather >than ABC. With the right environment, it's pretty hard to find any >situation where it's impossible to do something on Windows that it is >possible to do on Linux: all the 'really useful' things about Unix have >been ported to Windows to fill the gaps. What then is the reason to >still want a native Linux port ? As stated above: the 'really useful' part of Linux/Unix that has not been ported to Windows yet is stability (and security). Freedom from viruses/worms etc. That's a big reason why people are not wanting to run Windows now and are looking at Linux. > >Well, for me (and it's a personal view), it's a matter of 'Linux is my >work environment', and 'although there are workarounds (mingw, Wine, >etc) none of them really cut the mustard. To whit, I've just had to go >and buy Windows XP (and PC world, the only "nearby" computer shop, only >had the 'professional' version!) So I'm already £270 ($400 or so for our >US friends) down. Now I have to reboot into XP to do any experimenting: > > >Now, I have an idea that I think could be worth some money. What I'm >going to do over the next few months is evaluate whether it'll work, and >if so, purchase Foundation, because for me, the $2500 (=£1800 after >import, probably) will be worth it just for the time spent not switching >OS all the time, oh yeah, and it allows me to access the larger chips >:-) The critical thing though is that it works under Linux, and I'm >willing to put that much money into a bet that I can get a return (hey, >I'm only an amateur at this, for you professionals, it obviously makes >sense to get Foundation :-) > You're very committed to the hobby! I can't afford such commitment at this time. However, I think it' also important to note that there are companies out there running Linux and doing ASIC development on Linux and as they look more and more at FPGAs they want tools that will run well on Linux. >I guess the take-home message of what I'm trying to say, is that >although for some (perhaps a lot of) people the platform we work with is >agnostic. However I'd be willing to guess that most of those people are >already Windows users, and therefore 'agnostic' because it doesn't >affect their existing choice. My PC (until recently) didn't have Windows >on it. For me, the platform is an issue, to the point that I'm willing >to spend serious cash to stop it from being such. > >Xilinx, please take note: I'm using your devices despite your policy, >not because I love it. I suspect that there are more like me, and I >further suspect the number is growing. Please at least think about >supporting the Linux platform more. > Amen. PhilArticle: 71516
John Carter wrote: > Does anyone know of a supplier of FPGA's in compact flash format? > > (Yes, I know of FPGA development boards that have slots for compact > flash storage devices.) Compaq labs (now HP I suppose) created a device called BackPaq, for the Itsy/iPaq research they were doing a few years ago. It's an iPaq sleeve that has an FPGA in it, and connectors to other devices etc. Very cool, but your chances of getting hold of one would be very slim. stop press - blow me down with a feather, the first google hit for backpaq turns up a directory with full schematics for the thing! Not quite off-the-shelf, but interesting and useful regardless. http://lorien.handhelds.org/backpaq/ I'm off to have a closer look! JohnArticle: 71517
In article <40fd9deb_1@127.0.0.1>, Andrew Rogers <andrew@_NO_SPAM_rogerstech.co.uk> wrote: >Uwe Bonnes wrote: >> Phil Tomson <ptkwt@aracnet.com> wrote: >> ,,, >> : That still won't help when it comes to programming devices. The Jungo >> : parallel port driver doesn't work under Wine. >> >> I had some success with http://www.nahitech.com/jtag-en/ running with wine. >> Nahitafu will hopefully enable programming of more devices.. >> >> Bye > >How about GtkJTAG from the same author? That runs on Linux, I have >downloaded and compiled it. The downside is that in needs to run as root >due to low level IO. But it should be possible to use the parport device >driver. I am currently working on a modification to GtkJTAG (well, >libjtag to be accurate) so that it uses the parport device driver. There is a libjtag? > >As my Spartan 3 kit hasn't arrived yet I haven't been able to test GtkJTAG. > >A seperate project aimed at Virtex: > >http://www.ddtc.dimes.tudelft.nl/~rene/xilinx-jtag.c > >As far as I can tell from XAPP188 this will also program Spartan2 >devices and I can only guess that it may work for Spartan3. I can't find >an XAPP for spartan3 configuration using JTAG. > Thanks for the links. PhilArticle: 71518
Phil Tomson wrote: > > As a Linux software developer who has done a bit of consulting I've seen > several environments that were primarily Windows development houses. The > people in these groups might be very good developers, but they have no > idea of what exists in the Linux world (or the open source world in > general). They tend to view it as if it were a > dangerous foreign country that they want to keep their distance from. So > what happens is that Linux developers have a hard time communicating with > Windows developers (and vice-versa). Right now in Xilinx, I would bet > that you've got a primarily Windows development culture. Sure they've > made steps toward Linux-land, but they're very cautious steps. With time > they'll discover that the Linux waters aren't shark-infested and they'll > become more adventurous ;-) Mmm, not sure I agree with that. Without wishing to be an apologist for Xilinx (because basically I wish they'd get their act together and support Linux as a tier-1 platform!), I don't think it's a 'unix/linux is bad' attitude. They do support Suns, after all. FWIW, I think it's a cost/reward thing. There's a large proportion of people for whom the platform on which you code VHDL or verilog is irrelevant. These people are more concerned with the end-product of their design than the method of getting there, as all good designers ought to be. The issue comes when you have to change OS to do XYZ for a while rather than ABC. With the right environment, it's pretty hard to find any situation where it's impossible to do something on Windows that it is possible to do on Linux: all the 'really useful' things about Unix have been ported to Windows to fill the gaps. What then is the reason to still want a native Linux port ? Well, for me (and it's a personal view), it's a matter of 'Linux is my work environment', and 'although there are workarounds (mingw, Wine, etc) none of them really cut the mustard. To whit, I've just had to go and buy Windows XP (and PC world, the only "nearby" computer shop, only had the 'professional' version!) So I'm already £270 ($400 or so for our US friends) down. Now I have to reboot into XP to do any experimenting: o Hey! what if I use a blockram for the register file, and the high bit on the 6-bit register part of the opcode to select the 'switchable' 32 bank of registers. I can have 16 banks, 64 registers in total with the lower 32 at all times and 15x32 switchable). Use as thread-local or subroutine accelerators. Worth a try! o Hey! What if I use the parity entries of the blockram to implement a 'this i-or-d-cache value is valid' flag. The CPU can increment it's current tag-is-valid 'count' on cache-reset, and only actually clear the cache (and hence introduce delay) when 'count' cycles around to 0. That's a 16x win :-) o Hey! You get the idea. If it takes 15 mins to shut down all the programs I'm usually and normally running under Linux (since that's my work environment), and reboot into XP and try something, I'm far less likely to do it. Now, I have an idea that I think could be worth some money. What I'm going to do over the next few months is evaluate whether it'll work, and if so, purchase Foundation, because for me, the $2500 (=£1800 after import, probably) will be worth it just for the time spent not switching OS all the time, oh yeah, and it allows me to access the larger chips :-) The critical thing though is that it works under Linux, and I'm willing to put that much money into a bet that I can get a return (hey, I'm only an amateur at this, for you professionals, it obviously makes sense to get Foundation :-) I guess the take-home message of what I'm trying to say, is that although for some (perhaps a lot of) people the platform we work with is agnostic. However I'd be willing to guess that most of those people are already Windows users, and therefore 'agnostic' because it doesn't affect their existing choice. My PC (until recently) didn't have Windows on it. For me, the platform is an issue, to the point that I'm willing to spend serious cash to stop it from being such. Xilinx, please take note: I'm using your devices despite your policy, not because I love it. I suspect that there are more like me, and I further suspect the number is growing. Please at least think about supporting the Linux platform more. [grin: no, not really a Xilinx apologist :-)] SimonArticle: 71519
Phil Tomson wrote: > In article <KfiLc.322$YM6.78@newsfe4-gui.ntli.net>, > Simon <news@gornall.net> wrote: >> >>Mmm, not sure I agree with that. Without wishing to be an apologist for >>Xilinx (because basically I wish they'd get their act together and >>support Linux as a tier-1 platform!), I don't think it's a 'unix/linux >>is bad' attitude. They do support Suns, after all. > > > Yes, but I suspect that their Solaris port is in the same shape as their > Linux port. Also, I suspect that you can't program parts using Impact on > Solaris either. My point was that they seem to be doing all of their > initial development on Windows and then porting over to Linux (or > Solaris) using MainWin and this, of course, shows. > The "conventional wisdom" for some time has been that the command line tools, which are the things that do the actual work, were written on Unix platforms. After all, I seem to remember a time (my memory could be faulty here) when the tools were only available on Unix. In those days (not really so long ago), the GUIs were also written in X (probably Motif, which is what most vendors were using at the time). It looks to me like the command line tools are still either developed on Unix, or on Windows/Unix pretty much simultaneously. Only the gui has become a Windows thingy. I mainly think this because it is clear that the command line tool interface really has not changed much since "the old days", and they remain separate from the gui even now. The gui remains just a button clicking front end to those tools. I have not used Solaris in awhile, so I have no idea how that GUI performs these days. -- My real email is akamail.com@dclark (or something like that).Article: 71520
Hi, Does anyone have any experience in programming Altera FPGA's? In particular a FLEX8000. What development environment do you use and how much does it cost? Do any free development environments exist for it (VHDL or Verilog)? Also, is the programming hardware expensive? Thanks for any info,Article: 71521
Ramtilak wrote: > Hi, > > Can anyone suggest how to assign a area constraint on a sub-module > within my design? I dont care where the other sub-modules are as long > as this particular sub-module is in the required area. I know we can > assign a area constraint for the whole design. But, how to do it for a > sub-module? For Xilinx FPGA and tools, add something like below to the ucf file: INST “hierarchy/path/to/submodule” AREA_GROUP = "your_area_group_name"; AREA_GROUP “your_area_group_name” RANGE = range; HTH, Jim (jimwu88NOOOSPAM@yahoo.com remve NOOOSPAM) http://www.geocities.com/jimwu88/chipsArticle: 71522
"ernie" <ernielin@gmail.com> wrote in message news:d7fe9825.0407191638.58b29e0c@posting.google.com... > Hi, > > Can anyone recommend any good (and cheap) 32-channel analyzers? By > cheap I mean less than or approximately $1000. It would be nice if > the software supported complex triggering and the analyzer had > decently fast sampling rates. Sample depth is not really a critical > issue but more is obviously better. > > Thank you! You might be better off buying a second hand logic analyzer (non PC based) from eBay. Any PC based logic analyzer is going to be limited, especially with 32 channels. A lot of logic analyzers have RS232 or Network connectors so you can transfer the data to a PC.Article: 71523
remember to check the KEEP_HIERARCHY in the XST Options, and put AREA_GROUP “your_area_group_name” PLACE = CLOSED; AREA_GROUP “your_area_group_name” GROUP = CLOSED; Kelvin "Jim Wu" <NOSPAM@NOSPAM.COM> wrote in message news:fujLc.30825$F8.15097@nwrdny02.gnilink.net... > > > Ramtilak wrote: > > Hi, > > > > Can anyone suggest how to assign a area constraint on a sub-module > > within my design? I dont care where the other sub-modules are as long > > as this particular sub-module is in the required area. I know we can > > assign a area constraint for the whole design. But, how to do it for a > > sub-module? > > For Xilinx FPGA and tools, add something like below to the ucf file: > > INST “hierarchy/path/to/submodule” AREA_GROUP = "your_area_group_name"; > AREA_GROUP “your_area_group_name” RANGE = range; > > HTH, > Jim (jimwu88NOOOSPAM@yahoo.com remve NOOOSPAM) > http://www.geocities.com/jimwu88/chipsArticle: 71524
Austin Lesea wrote: (snip of many low power applications) > All of the above devices use uPs, ASICs or ASSPs because a FPGA is not > cost effective at all in these tasks (volume too large). > Reprogrammability doesn't add any value to any of the products. All of > these products use much older technology CMOS processes tweaked for low > power (high Vt's). > So, what market even exists that needs reprogramability (as in FPGAs), > AND also needs extremely low power? > It isn't that I do not believe that there are no low power applications > out there, it is that I need to be told which ones they are if I am to > help provide products for them. If the logic isn't there, the applications won't be developed. I remember being surprised some years ago when EPROMs started to be used in production devices. With the right price and convenience, they win out over masked ROMs. FPGA's have a similar advantage when the price and convenience are right. They will be slower and smaller than the state of the art devices, but the applications will come. -- glen
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z