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Hello, I have to work with legacy devices (Lattice Isp1032-60 and Isp1032E-70), and I'm looking for Synario 3.0 because I must update some projects that were made with that program version. I need Synario 3.0 also because newer versione of this software do not support those old CPLD. Can someone help me? -- Per rispondermi via email sostituisci il risultato dell'operazione (in lettere) dall'indirizzo -*- To reply via email write the correct sum (in letters) in the email addressArticle: 69476
Stijn Goris wrote: > I want to use a RTL8019 chip and want to interface it with a SPI bus > (datasheet: ftp://210.51.181.211/cn/nic/rtl8019as/spec-8019as.zip). I 'm > having trouble finding a good way to make the SPI communication. Someone > stated that an FPGA could do the conversion. Maybee you have a better idea? If this is the only task, a CPLD would be a better fit. IIRC a 8019 is an Ethernet (parallel memory mapped) controller, so you need SPI <-> Adr.Data.RD_WR_Strobes. First steps are to do a pin budget, then define transaction size ( 8/16/24 bits etc ), then how you will map the bus action/direction onto bits inside that frame. Smarter designs can include what amounts to SPI_DMA, where the CPLD can stream data at close to full SPI bandwidth, after being carefully initialised. If it's a 3V system, Xilinx Coolrunner2 devices will draw << 1mA @ 10MHz, if it is 5V, look at Atmel ATF150xASL devices. -jgArticle: 69477
> > > > Well Magma & Synplicity seem to have got enough information to be able > > to make physical synthesis tools. > > Does Magma make tools for FPGA? I thought they were just asic oriented. > Anyone who used it for FPGA care to comment? They have a physical synthesis tool: http://www.magma-da.com/c/@0GKYl0BeTX2k./Pages/PALACE.html Cheers, JonBArticle: 69478
Hi all, bitgen program in ISE can generate configuration bitstream that downloaded to the FPGA. In contrast, configuration bitstream, the currrent state of the registers in FPGA can also be readback. Create readback bitstream file by command line bitgen -w -l -m -g readback -g persist:X8... from application note XAPP176. So *.rbb and *.msk can be generated. My question is, how to generate readback ASCII file? .rba Thank you in advance. fhleungArticle: 69479
10Mb/s is a small cup of tea... Kelvin "Stijn Goris" <mepisto@hotmail.com> wrote in message news:qC6oc.102796$0s2.6160413@phobos.telenet-ops.be... > Hello Ray, > > Can you advice a FPGA that can deliver me the 10 Mbit/s? > > thanks > Stijn > > "Ray Andraka" <ray@andraka.com> wrote in message > news:40A0CD8A.EF088741@andraka.com... > > I don't think there are any FPGAs that have a hardwired SPI interface, if > they > > did it would be for programming. That said, any FPGA can be programmed > with > > an SPI interface. The interface is fairly simple to implement, and 10 > Mbit/s > > is easy to achieve. If you mean to use the SPI as a programming interface > to > > the FPGA, you'll have to use an external device to convert the SPI to one > of > > the programming formats recognized by the FPGA. A CPLD is sufficient for > that > > task. > > > > Stijn Goris wrote: > > > > > hi all, > > > > > > I m looking for a FPGA with a SPI interface. The SPI interface needs to > be > > > able to send data at a high rate (10 Mbit/s). > > > > > > regards > > > Stijn > > > > -- > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759 > > > > > >Article: 69480
>The key thing is that we both agree that be it an ASIC, >FPGA, or CPLD, code arithmetic resources (counters) >separately from the statemachines. There is one case where that might not hold. Consider a ROM based state machine. If you have lots of unused states maybe you don't need a counter. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 69481
Hi, I have my design files in Verilog,but want to have my testbenches in VHDL.I think this is possible. Can anybody suggest some pointers to this. I am using ModelSim 5.7g and Xilinx Project Navigator 6.2. --rajArticle: 69482
Hello I'm looking at interfacing my compact flash card with my Cyclone FPGA. What I want is some help/advice on how to start. Is there a website that has details on this? Thanks in advance RegardsArticle: 69483
jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0405110618.2b68ef83@posting.google.com>... > Siddharth Rele <siddharth.rele@xilinx.com> wrote in message news:<40A01D4E.3040203@xilinx.com>... > > Hi Dave: > > > > Have you tried using the -lc -lm -lc instead of -lm ? If this does not > > fix your problem, could you send the entire error log instead of just a > > snippet. > > > > Usually the first error is of most interest. > > Cheers, > JonB That's the only error or warning message. However, scrutinizing the build output I think what's happening is adding a float operation (just f = 1.0/f) pulls in all sorts of libs and is overflowing the available instruction space, which is set to 2048 (bytes? words?). Thanks to all who tried to help. -DaveArticle: 69484
Brian Drummond <brian@shapes.demon.co.uk> wrote: >Jim Lewis <Jim@SynthWorks.com wrote: >>Xilinx has taken the enviromentally sound practice >>of taking parts that would have otherwise gone to the >>dump, making them into something useful, and selling >>them. > >I don't believe they have, as I understand it, I don't believe the >EasyPath parts have actually failed production test. > >As I recall, it was the full testing itself that was expensive, rather >than the device failures. To take it to extremes, if you can churn out >wafers full of good devices, but you have to leave each chip sitting on >the tester for eight hours to prove it, then test costs would be a >killer. I once was a semiconductor test engineer, and when I was in that business decades ago, test time cost around US$0.25 per second per device. I'm sure it's rather more now. Eight hours would be rather pricy, say well over US$7,000 each! I've looked into testing FPGAs, and to get reasonable fault coverage requires hundreds of downloads. Look at the fastest loading method, multiply it by an assumed test time cost and that would give you a very minimum estimate of test cost. Test cost is a significant fraction of total cost for many semiconductor devices. For testing only what is used, this would allow a very major reduction in test time and cost. There is also a gain from the increased yield. The gain from each is going to depend on the defect density. If the yield is already high, as it would be with a smaller part on a mature process, the gain would be mostly from reduction in test cost. If the yield is low, as it would be on a large part or on a new process, then the gain would be from both improved yield and reduced test time. Don't forget that a part that fails still needs to be tested to the point that it fails. The test problem isn't the CLBs or the FFs, it is the interconnect. It is hard to get 5% of the interconnect used on a design, and the parts are more than half interconnect. >That would give a LOT of scope for testing exactly what a customer >wants, and no more, and passing on the reduced cost of test time. The >difference is, the rest of the chip is POSSIBLY fully functional, but >Xilinx haven't spent the money to prove it. Even if there was a defect on the rest of the chip, a different download would have a small chance (a few percent at most) of hitting it. If the change was as limited as possible, changing only a few interconnects or limited to the contents of LUTs, the odds of hitting a defect would be fairly near zero. It would be a good idea to have a test plan to determine if the new load is fully functional in each system in any case. >>To me this reflects engineering brillance. > >Either way... It is a great idea for the right end users. -- Phil Hays Phil_hays at posting domain should work for emailArticle: 69485
I picked up an EE Tools TopMax universal device programmer at the flea market recently. It appears to be in fine shape, but it fails the hardware test in the Windows software. Some functions seem to work OK (e.g. the 74xx logic test/identifier), but I haven't been able to successfully program a 27C256 EPROM, so I suppose it really is faulty. I opened it up and there's no obvious damage inside, and the +5/+12 power supply voltages are OK. The PC boards inside have a 1998 copyright date on them, BTW. Does anyone have any schematics and/or service information for this programmer? These guys cost about $1K new, so I hate to throw it away with out at least trying to fix it. Thanks, Bob ArmstrongArticle: 69486
fhleung wrote:
> Hi all,
>
> bitgen program in ISE can generate configuration bitstream that downloaded to
> the FPGA.
>
> In contrast, configuration bitstream, the currrent state of the registers in
> FPGA can also be readback.
>
> Create readback bitstream file by command line
> bitgen -w -l -m -g readback -g persist:X8... from application note XAPP176. So
> *.rbb and *.msk can be generated.
>
> My question is, how to generate readback ASCII file? .rba
>
> Thank you in advance.
In "Project Navigator" in the "Generate Bitstream"-process options, you
have to activate the options "Create ASCII Configuration File" ("General
Options" tab) and "Create Readback Data Files" ("Readback Options" tab),
only then the .RBA is generated.
If you call bitgen from the command line, you have to add these options:
-b -g Readback
The documentation is wrong there (at least the doc for ISE5.2), as it
states that it is enough to use the "-g Readback" option to generate the
file.
cu,
Sean
Article: 69487SneakerNet wrote: > Hello > > I'm looking at interfacing my compact flash card with my Cyclone FPGA. What > I want is some help/advice on how to start. Is there a website that has > details on this? Yes, have a look at the datasheet/application notes at Sandisk. Not necessarily for an FPGA, rather for CPU interfaces. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 69488
On 11 May 2004 15:25:59 -0700, jon@beniston.com (Jon Beniston) wrote: >> > >> > Well Magma & Synplicity seem to have got enough information to be able >> > to make physical synthesis tools. >> >> Does Magma make tools for FPGA? I thought they were just asic oriented. >> Anyone who used it for FPGA care to comment? > >They have a physical synthesis tool: > >http://www.magma-da.com/c/@0GKYl0BeTX2k./Pages/PALACE.html In this context physical synthesis still means technology dependent placement and it doesn't require much more internal knowledge than wiring information on the fpga (in addition to lookup table programming and placement configuration which is somewhat exposed in data sheets already). The result is yet another partially placed netlist which still requires placement finalization and detailed routing (and of course bit file generation). These last two steps do really expose what's going on in the chip and I don't think any FPGA company is going to let anyone write such tools.Article: 69489
jon@beniston.com (Jon Beniston) writes: > (My biggest pet-peeve is > > FPGA synthesis. FPGAs have had dual-port RAMs for ~7 years now, yet > > we still can't infer dual-port block RAM from HDL. Arggh!) > > Yes you can. > With two clocks and two write ports!? Which tool does this and what is the template HDL one has to use? > > What can we do to improve open-source EDA? > > Nothing, hopefully. Some of us would still like to be able to earn a > decent living from writing software, you know? ;) > Open-source doesn't *have* to mean no-cost... and neither does free-software. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 69490
On 11 May 2004 18:43:17 -0700, rajarsheeb@yahoo.com (raj) wrote: >Hi, > >I have my design files in Verilog,but want to have my >testbenches in VHDL.I think this is possible. >Can anybody suggest some pointers to this. >I am using ModelSim 5.7g and Xilinx Project Navigator 6.2. No problem, as long as you have the (expensive) Modelsim license that allows co-simulation. Check your license. Regards, Allan.Article: 69491
Hi all, I'm looking for a CF FPGA prototyping card. Do you know of such a beast? The closest I could find so far is the Wildcard, combined with a CF to PCMCIA adapter. http://www.annapmicro.com/wildcard2.html http://www.elandigitalsystems.com/accessories/cf2pce.php Kind regards, IwoArticle: 69492
> so how do I automate the process of finding where place and > route has put my BRAM? you need a .bmm file (Block RAM Memory Map) ... it contains the names of the blockrams... If you put this file in the project tree (asigned to the toplevel) then place&route will create a second .bmm file with the location of the blockrams ... I'm sorry - I don't know how to create these files manually ... In my case they are created by the EDK (platgen I think) bye, MichaelArticle: 69493
Austin, so what you are saying is that you can build a chip to potentially suit any design you like, but in fact customers are more interested in getting their own design to work and don't really care about the other possibilites. Does that mean that in the future, if everyone adopts this strategy, we will be back to having to swap chips at every upgrade? I thought one of the (many) wonderful advantages of FPGAs is their prolonged lifetime due to upgrade potential..... Effectively, if everyone does go down that route, Xilinx, Altera and Co. will become ASIC producers!! Very good ones, don't get me wrong, with time and money savings for everyone, but..... Maybe I'm just getting a bit nostalgic...... On Mon, 10 May 2004 07:58:30 -0700, Austin Lesea <austin@xilinx.com> wrote: >ACM, > >Oh, that was really mature. > >Did you know that we need to start new wafers to supply Easypath? (can >not rely on having enough die with one or two memory cells that are at >fault to satisfy demand). > >Did you know that the cost savings are mostly from testing the chip for >what the customer uses it for, rather than for testing it for what >everyone of our 250 thousand seats of software might design it to do? > >Oh, and what about all those laser trimmed redundant chips out there, >are those also scrap? After all, every one of those has a proven >hardware faults! > >(PS: thanks for bringing this up again, and giving me the opportunity >to reply -- it is so much fun to see the subject line of your posting >promoted by someone else besides me) > >Austin > >acm wrote: >> Easypath = EasyScrap... >> >> Hey, buy our excess scrapped inventory!!!! >>Article: 69494
BrakePiston wrote: > Austin, > > so what you are saying is that you can build a chip to potentially > suit any design you like, but in fact customers are more interested in > getting their own design to work and don't really care about the other > possibilites. > > Does that mean that in the future, if everyone adopts this strategy, > we will be back to having to swap chips at every upgrade? I thought > one of the (many) wonderful advantages of FPGAs is their prolonged > lifetime due to upgrade potential..... > > Effectively, if everyone does go down that route, Xilinx, Altera and > Co. will become ASIC producers!! Very good ones, don't get me wrong, > with time and money savings for everyone, but..... > > Maybe I'm just getting a bit nostalgic...... There are users for both types. A good parallel here is to look at the uC market: For a while, flash was seen as the ultimate, and some companies chose do only flash devices - but MASK ROM is actually not going away, and recent releases from some big suppliers have both FLASH and MASK models. FLASH covers development, and products needing design turns, but MASK has much lower FAB costs, lower testing times, and also has zero risk of unexpected field erasure, as well as wider Vcc operation, and zero programming costs. If your product is stable, and in high volume, it would be imprudent to not consider mask. If the FLASH variant is available, then product changes can always be covered, and are only needed for the ROM pipeline delay. I have not seen the die photos of these new devices, but I presume they use identical mask sets where possible, and skip the extra flash steps. ie the MASK die may not actually be smaller, and there are arguments to not do that (even tho you can), to keep identical EMC operation. The FPGA flows mimic this : Full testing coverage gives devices for development and many design turn products, but once it is stable, why not take the cost savings ? - a key aspect is the electrical operation is identical and thus timing and EMC approvals do not change. Why the NRE costs are so high is another story :) -jgArticle: 69495
http://www.xilinx.com/bvdocs/publications/ds080.pdf Kelvin "Rene Tschaggelar" <none@none.net> wrote in message news:40a1d5ce$0$713$5402220f@news.sunrise.ch... > SneakerNet wrote: > > Hello > > > > I'm looking at interfacing my compact flash card with my Cyclone FPGA. What > > I want is some help/advice on how to start. Is there a website that has > > details on this? > > Yes, have a look at the datasheet/application notes at Sandisk. > Not necessarily for an FPGA, rather for CPU interfaces. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.netArticle: 69496
Hi all, I would like to use a signal in the a testbench that is declared in one of the subblocks of the top. This question might obvious, but I cannot find any other way to use subblock signals from a top of a design ONLY for simulation purposses. What I usually do is to add those signals as ports in each entity beginning from the bottom of the design and continuing the hierarchy until I arrive to the top. In order not to consider them in the synthesis I add "synthesis translate off/on" comments. Here you are an example: Imagine that I want to instantiate the internal signal of the subblock1 from the top entity top is port( -- synthesis translate_off tb_out : out std_logic; -- synthesis translate_on ... ); end top; architecture arch of top is begin uut: subblock1 port map( -- synthesis translate_off internal => tb_out, -- synthesis translate_on ... ); end; Then I instantiate the top in the same way from the testbench. I know that in verilog there is another way to refer to a signal that is declared in subblock, just with something like this: "top.subblock1.internal" Any suggestion? Thanks in advance, Arkaitz.Article: 69497
Dave wrote: > That's the only error or warning message. However, scrutinizing the > build output I think what's happening is adding a float operation > (just f = 1.0/f) pulls in all sorts of libs and is overflowing the > available instruction space, which is set to 2048 (bytes? words?). Then just make it bigger. :) You probably have some sort of BRAM-controller in your design... attached to the PLB, OPB, or OCM-controller. Usually the smallest size available is 8kB, which is too little in most cases, especially when you need a bunch of extra libs. To get more instruction-side memory, all you have to to is change the address range of the BRAM-controller, EDK takes care of the rest. The size has to be a power of 2 though (8kb, 16kb, 32kb, 64kb...), and you have to make sure you don't use more BRAMs than you have available in your FPGA.. For example, in an xc2vp7 there are 44 BRAMs of 2kb each, so the biggest memory size for your PPC is 64kb. For example: a base address of 0xFFFF0000 and a high address of 0xFFFFFFFF for your BRAM-controller wuld give you 64kb of memory for your program. Note that 0xFFFFFFFC must always be included in the address space, since that is the address the PPC starts program execution from. cu, SeanArticle: 69498
Any chance Peter or Austin could post some non-proprietary information on the typical number of tests and average test time for a "generic" FPGA versus one for the EasyPath with a known FPGA bit pattern? As the devices get more complex, does test time go up linearly? What does test time cost per second? How expensive are the testers? Any other tidbits to enlighten/amuse us? Device testing is something a lot of people are never exposed to, so this could be an interesting education. EasyPath sounds like a cute idea - I hope it works well for Xilinx. John ProvidenzaArticle: 69499
On 05/12/2004 02:44 PM, arkaitz wrote: > Hi all, > > I would like to use a signal in the a testbench that is declared in > one of the subblocks of the top. > > This question might obvious, but I cannot find any other way to > use subblock signals from a top of a design ONLY for simulation > purposses. > > What I usually do is to add those signals as ports in each entity > beginning from the bottom of the design and continuing the hierarchy > until I arrive to the top. In order not to consider them in the > synthesis I add "synthesis translate off/on" comments. > See the following links. They show you simulator dependent and independent solutions. <http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#monitor> <http://tinyurl.com/2gyo2> <http://tinyurl.com/3h83e> And please post further VHDL questions to comp.lang.vhdl. I hope this solves your problem :-) Tschoe, Steff
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