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Hi all, I am trying to connect the SDRAM on-board the Nios Development Board to the FPGA Stratix EP1S40F780C5. It was not included among the library components in the Megawizard plugin and I was directed to download it. After that is done, I installed it according to instructions. However, when I re-visited the Wizard, it did not appear. The funny thing is its available in the SOPC builder. Did anyone experience the same problem? How should I resolve this issue since I do not want to involve the NIOs in my design. EdwardArticle: 70326
General Schvantzkoph wrote: > On Fri, 11 Jun 2004 11:31:18 -0700, Stephen Williams wrote: > > >>Does anybody know if the Xilinx Paralel cable IV cable can >>be made to work under Linux w/ ISE 6.1i.03? And to make it >>even more interesting, my Linux is AMD64, will the driver work >>at all on this system? > > The driver is tied to the kernel in Redhat 8.0 (I think it's 2.4.17). They > don't have a patch for a modern kernel. > The driver source is available, so it is *not* tied to RedHat 8. There is an APP note that covers this. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 70327
We think we can give you a good sized advantage on both area and timing. Our area advantage tends to be even bigger than our timing advantage which could get you into a smaller part. We also have some good analysis tools that can help you figure out how to improve your RTL - a good clean design always helps. - Ken McElvain CTO, Synplicity, Inc Jason Berringer wrote: > Hello all, > > I'm curious to know the benefits of using third party synthesis tools. For > example how much better are synthesis tools like Synplicity or Synplify, etc > over just using the vendor tools ISE Webpack. Do you only experience some > significant gains with large designs or does it not really matter. I've been > using the Xilins synthesis tools for quite a while and have never had a > problem. I will be the first to admit that my largest designs have only > taken up about 60% of a XC2S150 so I'm not dealing with mosterous designs. > > Anyn commetns are appreciated. > > Jason > > jberringer@remove.sympatico.remove.ca > > remove the removes to reply to me personally. > >Article: 70328
"Frank Benoit" <nospam@xyz.com> wrote in message news:pan.2004.06.12.00.33.17.424256@xyz.com... > Hi > > Can anyone please give me an rough overview about prices of IPs for the > Xilinx Virtex II Pro? i.e. > 10/100 Ethernet is free on opencores > CAN-Controller is free on opencores > LIN - Local Interconnect Network Bus Controller (iLIN) LIN is basically simple UART protocol can be handled with UART + SW or even software only > Do I have to pay for each sold piece or one time or one time per project? beware the "free" is not completly free as it often not complete lacks documenation and or support > Frank Antti http://www.openchip.orgArticle: 70329
I am using RAM in a processor design and I am having trouble understanding exactly how best to use these functions for my design. I will be using them to implement stacks, program memory and data memory. Ideally the write function will look like an addressable register where the address, data and enables are setup prior to the clock and the write happens on the clock edge. The read should be async so that I can provide an address and get data after a delay. The Altera part is an EP1K50 where the EAB read can be async. The write however is only shown as either fully async or fully registered. I recall that I was warned when reading and writing the same address the data out has a longer delay. But I can't seem to find a reference to that. I am also unclear if I can use the write the way I want or if it requires input registers. The Xilinx part is an XC3S400 with dual port block rams. It seems like the read path must be registered as well as the write path. I think I could live with that if I could read the data that is being written (top of stack) in the same clock cycle. But I belive the docs say that the other port can either read the old data or is invalid. But then I may be able to use a single port ram for a stack. The address would always be pointing to the current TOS and as soon as a new value were pushed, the next clock edge would read the new data as it is written to the new address. I don't want to pipeline anything in this design to keep it very simple. Right now the design is pretty clean and the delay paths are pretty short. Can anyone clarify how these rams work without pipelining? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70330
Frank Benoit wrote: > Hi > > Can anyone please give me an rough overview about prices of IPs for the > Xilinx Virtex II Pro? i.e. > 10/100 Ethernet > CAN-Controller > LIN - Local Interconnect Network Bus Controller (iLIN) > Do I have to pay for each sold piece or one time or one time per project? The non public IP cores are targetted at high volume stuff. So unless you're there, forget them. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 70331
the ethernet ip from opencore is for wishbone. is it possible to connect it to a powerpc core?Article: 70332
hmurray@suespammers.org (Hal Murray) wrote in message news:<z8OdnaZ9j5PaGFfd4p2dnA@megapath.net>... > [DRAM refresh not needed if you read/write often enough] > > >I've never seen anybody take advantage of that though. > > We built a delay line using DRAM. The idea was to simulate > a 10,000 km 155 megabit link in order to test software. > > No refresh needed. Just assign the RAS/CAS bits such that > you use each row often enough. On the other hand, you can > save power if you don't touch rows more often than necessary. Curious, I am planning on making my cpu DDR interface run as hot as possible (not that I like heat) but I am running no sram data cache since the ld/st address for 16 threads will be more random than a small cache could handle. The DDR specs I have from Micron are vague on power dissipation or I haven't found it yet for the case I am interested in. In order to allow so many threads I also need to thow them around to different banks, if they all hog 1 bank, perf would be impacted. So how much power can a typ 256M DDR DRAM dissipate when running Ras/Cas cycles as often as possible at say 250MHz and on random banks 1 or 2 simultaneous? regards johnjakson_usa_comArticle: 70333
>The DDR specs I have from Micron are vague on power dissipation or I >haven't found it yet for the case I am interested in. There is probably a section on current used under various conditions. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 70334
Thanks for your help. I will try to modify this lab to match my needs. Thanks again. Eric Crabill <eric.crabill@xilinx.com> wrote in message news:<40C9FC1C.AD31EB14@xilinx.com>... > Hi, > > Go to http://www.engr.sjsu.edu/crabill and download Lab #1. > > Eric > > Yang-Tzu wrote: > > > > Hello everybody, > > > > I am trying to use Xilinx's tool, ISE4.1i, to generate the > > bitstream file from my VHDL designs. > > > > If I have three designs named A, B, C. Designs B and C are the > > components of A. When I using Xst to synthesize C, it could be done. > > But if I synthesize A, B, and C, errors occured. Therefore, I could > > have no choice but stop. > > > > Could anyone tell me how to using the xilinx command line from > > synthesize VHDL files to generate bitstream file (or SVF file)? Any > > Documents about this? I am reading the documents of "Development > > System Reference Guide" of xilinx, but no good answers. > > Could anyone tell me the correct design flow or give me an example > > using command line to synthesize, PAR and generate configuration > > files? > > The chip I am using is xc2s100-5pq208. > > Thanks for any answers. > > > > Yang-TzuArticle: 70335
STA - static timing analysis, what's so "static" about it that people could it "static" as if there is such thing as "dynamic" timing analysis which I haven't hear of. Please enlight. Thanks, CharlesArticle: 70336
Hi,
Is anyone has the experience of converting bitstream file format to
svf file format?
It seems that iMPACT can't create svf file but bitstream file.
(Any document about this? The help of iMPACT have no solution. :(
)
Is anyone has the answer?
thanks.
Yang-Tzu
Article: 70337"charles" <czheng@ieee.org> wrote in message news:<XOOyc.21509$0g3.7700622@news4.srv.hcvlny.cv.net>... > STA - static timing analysis, what's so "static" about it that people could > it "static" as if there is such thing as "dynamic" timing analysis which I > haven't hear of. Please enlight. "dynamic" timing analysis is timing anaylsis performed by running a gate-level simulation annotated with timing information. The problem with this, is that only logic changes that occur in the simulation have their timing verified. With STA, all paths/state changes are covered, without the need to test-vectors. Cheers, JonBArticle: 70338
Thanks for the tip. Yes, I forgot to add that I have the Stratix Nios
Development Kit (Professional). I have another problem though. I can
add symbols in the .bdf files i.e. lpm_add, lpm_mult etc. However,
these basic components are not avialable in the MegaWizard Plugin. I
tried adding new IP blocks (SDRAM controller) to the wizard and this
does not show in the Wizard like the guide said it would. That's after
re-installation of the Quartus 2 (v4), service pack 1 and the Nios CD
(Installation did not produce any errors). I tried editing the
wizard.lst file and yes, it did show up on the Wizard interface but
the component is still not available. An exhaustive search of manuals
and online documentation didn't reveal anything. Any suggestions?
kempaj@yahoo.com (Jesse Kempa) wrote in message news:<95776079.0406111015.23670bca@posting.google.com>...
> ang_edward@hotmail.com (Edward) wrote in message news:<21076d77.0406110229.55163e02@posting.google.com>...
> > Hello All,
> >
> > I am trying to interface the on-board SRAM (IDT71V416 256Kx16) to the
> > FPGA on the Stratix. It is not installed among the library components
> > in the SOPC builder so I cannot instantiate it automatically.
> >
> > I have the datasheet for the SRAM but I need to know where the
> > address, data pins etc. are connected to the FPGA. The pin-out table
> > doesn't seem to specify that in the Stratix handbook.
> >
> > Can anybody tell me where to look for information or an alternative
> > methodology? That would be really helpful.
> >
> > Thanks a mil!
> > Ed
>
> Hi Ed,
>
> Hmm, sounds awfully like you have the Nios dev kit ('pro' edition).
>
> The easy way to get your SRAM going is to locate your Nios kit
> installation CD and make sure your install is up-to-date. That SRAM
> chip *should* be included with SOPC Builder if you have Nios properly
> installed. It will be listed under the components for the Nios 1S40
> dev board.
>
> For pin-outs, the various Nios/Nios II example designs (standard or
> standard_32) will have this SRAM instantiated and will have all the
> pins wired up and ready-to-go. This should save some time over
> manually assigning the pins! (a human-error-prone process I have never
> been fond of regardless of the tool).... so the ultra-easy way do use
> this SRAM would be to simply copy one of these Nios exampled designs
> off to a separate location, modify at-will to get the
> peripherals/system choices you need, and keep the SRAM/pinouts/Avalon
> connections the same.
>
> Regards,
>
> Jesse Kempa
> Altera Corp.
> jkempa at altera dot com
Article: 70339But my understanding is that you will always need stimulus or test vectors to simulate your design to see if they are functionally correct. So I guess what you mean by STA not needing test vectors is that the static timing analyzer will check all the paths in the design to find the paths with longest delay to determine the maximum operating frequency. It will even go thru the paths/logics that are not covered by the test vectors. So I guess the sole purpose of STA is to determine longest delay paths, so as to give the designer ideas where and what to constraint to improve the clock frequency. And I guess, during this interative constraint/synthesis/STA cycles, some constraints might be incoherent, thus causing the situation where the constraint is met but functionally broken. So is it fair to say that: "dynamic" timing analysis: 1. It's part of gate-level simulation. 2. If the gate-level simulation (with all the delays,i.e., logic plus routing, accounted for) passes the functional test with all the available test vectors, we can say that we have archieve timing closure; 3. Timing closure is only as good as your test vectors. If you don't have 100% coverage of your logic/states, you always run a risk of timing failure in untest circuit. Static Timing Analysis: 4. Examine all paths and states to find the longest delay path to calculate the maximum frequency. Designer uses this information to specify the constraint to improve the frequency, or use techniques such as register rebalancing or insert an extra FF. 5. It is done without any testvectors, so it is done by the tool automatically in both post map and post place&route. It does not concern itself with the functionality of circuit. 6. It seems that you have to functionally understand the circuit before someone can specify some coherent constraints. So I guess constraints are usually specified by the RTL designers themselves. So what does the back-end process usually invovles with then? Please comment, and thanks so much for your time! Charles "Jon Beniston" <jon@beniston.com> wrote in message news:e87b9ce8.0406130220.206bcaaf@posting.google.com...Article: 70340
Arturo You really need an older processor core ? have you a lot of software running into this processors ? If not, you have more economic solutions using FPGA optimized cores as PicoBlaze in 8 bits or MicroBlaze in 32 bits. and PicoBlaze is FREE . Walter. "Arturo Rios" <arturios75@yahoo.com.br> a écrit dans le message de news:9cb21c00.0406101239.28aa41e@posting.google.com... > Hi, > I'm a new user of fpga, actually i'm learning about it and i need > help. > I want to know how import cpu's cores (8051 or z80) into a xilinx fpga > device ( Spartan IIe ). If someone can send me a tutorial where i can > learn about that i thanks a lot.Article: 70341
Yang-Tzu, Imact is able to create a SVF file from a bit file. Details can be found in the iMPACT documentation: http://toolbox.xilinx.com/docsan/xilinx6/help/impact/impact.htm Shalin- Yang-Tzu wrote: > Hi, > Is anyone has the experience of converting bitstream file format to > svf file format? > > It seems that iMPACT can't create svf file but bitstream file. > (Any document about this? The help of iMPACT have no solution. :( > ) > > Is anyone has the answer? > > thanks. > Yang-TzuArticle: 70342
Hi, Do the following in impact to get the .svf file Go to Edit - Preferences - check the box on " Keep intermediate SVF file ". Ram PS: I am not sure is this what you are looking for, if not please rephrase your question. m9107904@knight.fcu.edu.tw (Yang-Tzu) wrote in message news:<46e53203.0406122305.1c463cad@posting.google.com>... > Hi, > Is anyone has the experience of converting bitstream file format to > svf file format? > > It seems that iMPACT can't create svf file but bitstream file. > (Any document about this? The help of iMPACT have no solution. :( > ) > > Is anyone has the answer? > > thanks. > Yang-TzuArticle: 70343
"Frank Benoit" <nospam@xyz.com> wrote in message news:pan.2004.06.12.23.17.36.161401@xyz.com... > the ethernet ip from opencore is for wishbone. is it possible to connect > it to a powerpc core? hm, we have succesfully connected several wishbone peripheral cores to OPB bus (used in Virtex2Pro PowerPC systems). I havent checked if the ehternet core requires busmastering or not. Without bus mastering the OPB to wishbone adaption is fairly simple. antti xilinx.openchip.orgArticle: 70344
Andrea, If you are looking for ways on how to pass variables to assembly instructions in MicroBlaze, check out the very last passage in the following solution record: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18561 Hope this helps, Matt Andrea Sabatini wrote: > Hi all. > > I have to write a code for the MicroBlaze soft processor (Xilinx Platform > Studio 6.1.03i) and I am facing the following problem: both my assembly code > and my c code have to access some shared (global!) variables but I do not > know how to do it. I downloaded all the MicroBlaze documentation from the > Xilinx web site (or at least I am convinced I did) but I did not find any > clue. Does someone of you out there know how to do it? > > Regards, > > Andrea Sabatini > >Article: 70345
Hi, there: I am asking a question about Design Compiler for ASIC. My ASIC lib can operate from 2.2V~3.0V, but the other library user gave me a derating library derating_lib.db, which he claims it can enable operations to 2.0V... In the derating_lib.lib, it only shows a new operating condition called "worst_derated" which has a voltage of 2.0V, same worst case temperature and nothing more than that. How do I make use of this library? Setting the operation_condition to "worst_derated" and use the worst.db for synthesis? But how does DC work if there is no derating factor? Best Regards, KelvinArticle: 70346
It's simple, the pioneer Synopsys defined that term...I guess that's intended to differentiate itself from gate-level simulation... When you are the pioneer in a field, you can define funny terms too... Kelvin "charles" <czheng@ieee.org> wrote in message news:3sZyc.374$uh1.993184@news4.srv.hcvlny.cv.net... > But my understanding is that you will always need stimulus or test vectors > to simulate your design to see if they are functionally correct. So I guess > what you mean by STA not needing test vectors is that the static timing > analyzer will check all the paths in the design to find the paths with > longest delay to determine the maximum operating frequency. It will even go > thru the paths/logics that are not covered by the test vectors. So I guess > the sole purpose of STA is to determine longest delay paths, so as to give > the designer ideas where and what to constraint to improve the clock > frequency. And I guess, during this interative constraint/synthesis/STA > cycles, some constraints might be incoherent, thus causing the situation > where the constraint is met but functionally broken. > > So is it fair to say that: > "dynamic" timing analysis: > 1. It's part of gate-level simulation. > 2. If the gate-level simulation (with all the delays,i.e., logic plus > routing, accounted for) passes the functional test with all the available > test vectors, we can say that we have archieve timing closure; > 3. Timing closure is only as good as your test vectors. If you don't have > 100% coverage of your logic/states, you always run a risk of timing failure > in untest circuit. > > Static Timing Analysis: > 4. Examine all paths and states to find the longest delay path to calculate > the maximum frequency. Designer uses this information to specify the > constraint to improve the frequency, or use techniques such as register > rebalancing or insert an extra FF. > 5. It is done without any testvectors, so it is done by the tool > automatically in both post map and post place&route. It does not concern > itself with the functionality of circuit. > 6. It seems that you have to functionally understand the circuit before > someone can specify some coherent constraints. So I guess constraints are > usually specified by the RTL designers themselves. So what does the > back-end process usually invovles with then? > > Please comment, and thanks so much for your time! > > Charles > "Jon Beniston" <jon@beniston.com> wrote in message > news:e87b9ce8.0406130220.206bcaaf@posting.google.com... > >Article: 70347
charles wrote: > But my understanding is that you will always need stimulus or test vectors > to simulate your design to see if they are functionally correct. Yes, consider writing an hdl testbench to provide the stimulus for your functional verification. > So I > guess what you mean by STA not needing test vectors is that the static > timing analyzer will check all the paths in the design to find the paths > with longest delay to determine the maximum operating frequency. It will > even go thru the paths/logics that are not covered by the test vectors. It has nothing to do with test vectors. It's an automated test of the maximum delay from Q to D between each register. > > So I guess the sole purpose of STA is to determine longest delay paths, > so as to give the designer ideas where and what to constraint to improve > the clock frequency. It is to prove that the design will run without timing problems at the required frequency. This assumes a 100% synchronous design. > And I guess, during this interactive constraint/synthesis/STA > cycles, some constraints might be incoherent, thus causing the situation > where the constraint is met but functionally broken. Consider using simulation code coverage to make sure the functional sim is complete. > 2. If the gate-level simulation (with all the delays,i.e., logic plus > routing, accounted for) passes the functional test with all the available > test vectors, we can say that we have achieve timing closure; No. You have done an incomplete and perhaps unnecessary double check on the static timing analysis. Timing closure means doing whatever is necessary to meet the fmax you need in static timing. > 3. Timing closure is only as good as your test vectors. No. A functional test is only as good as your code coverage. -- Mike TreselerArticle: 70348
When simulating .sdf in Modelsim, I can see the registered signal names of my VHDL description apart from many other gate level names. Should I not be able to see the "original" registered names? Thank you. Kind regardsArticle: 70349
Tommy Thorn <TommyAtNumba-Tu.Com--not@yahoo.com> writes: > RANGA REDDY wrote: > > is it true that Micron SDRAM does not require any refresh cycles if we > > are reading the SDRAM rows once in 20 ms atleast? if i dont give any > > refresh cycles what will be the condition of the SDRAM? > > AFAIK, *no* SDRAM requires refresh cycles if all the rows you care > about are touched (read or written) sufficiently often. I think once > every 64ms is enough. > > I've never seen anybody take advantage of that though. > Our video-processing app doesn't bother with refresh for the display frame buffer. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt
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