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"Antti Lukats" <antti@case2000.com> writes: > LIN is basically simple UART protocol can be handled with UART + SW or even > software only > Erm, not if you want to master the sync break right... 13 consecutive low bits doesn't come out of the UARTs I've used. I've seen it work with SW only, but it's not spec compliant... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 70351
Matt, Thank you for your reply. I am now facing another problem. I would like to call C routines from my assemble code but I did not found a place where there is written how to do it. I am able to do it with routines that do not need input parameters and do not return any value but I need to know how to do it in a general case (presence of ins and outs). Thanks in advance, Andrea "Matthew Ouellette" <matt.ouellette@xilinx.comNOSPAM> wrote in message news:cai9bm$jn31@xco-news.xilinx.com... > Andrea, > > If you are looking for ways on how to pass variables to assembly > instructions in MicroBlaze, check out the very last passage in the > following solution record: > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= 1&getPagePath=18561 > > Hope this helps, > > Matt > > Andrea Sabatini wrote: > > > Hi all. > > > > I have to write a code for the MicroBlaze soft processor (Xilinx Platform > > Studio 6.1.03i) and I am facing the following problem: both my assembly code > > and my c code have to access some shared (global!) variables but I do not > > know how to do it. I downloaded all the MicroBlaze documentation from the > > Xilinx web site (or at least I am convinced I did) but I did not find any > > clue. Does someone of you out there know how to do it? > > > > Regards, > > > > Andrea Sabatini > > > >Article: 70352
Hi, I'm doing a work for my studies which consists who programming an FPGA (Spartan 2, xc2s200). We have three plattform with it: -A BurchED Board -Two selfmade PCB with all other components (RAM, PROM, Clock Generator, UART modul), one was soldered by the previous work, the other by me. We want to boot the FPGA in Master Serial Mode. It works OK on the BurchED Board, so controlled the configuration pins on both boards, which are correct (M2, M1 too ground; M0 is not important in that case, but also to ground.) I actually never got the FPGA booting from Flash (xc18v02). I can program both flash. The second problem is that I can't configure the board i soldered myself through JTAG. When I choose init cable in impact, the FPGA is correctly recogninanize as xc2s200, but when I choose programm, the programm says "incorrect idcode". I looked at it, sice are zeros at one in it, it can't be a stuck-at fault. Useful infos: The pullups are down one the old board with 4.7 KOhm, on the newer with 5.6 kOhm (there weren't any 4.7 left) Can anybody help me ? I have read the newsgroup and found no solution.Article: 70353
At first thanks for Mike's answer. But my exact question was how to extract so many many internal signals which are listed during the timing simulation. For example, _inbuf, _ibuf, _gst, etc. How can I know which signal represents my original input signal or output signal? mike_treseler@comcast.net (Mike Treseler) wrote in message news:<865ab498.0406110925.5aef46c9@posting.google.com>... > c.chen@gmx.de (Chao) wrote in message news:<8228a344.0406101346.30f8ace2@posting.google.com>... > > > I am dealing with the back-annotated SDF timing simulation. The > > timing_vhdl file is generated by the Xilinx ISE tool and I applied it > > to the Modelsim simulator. But how can I obtain my original > > input/output signal? > > Maybe you are using a component instance, > and need a configuration. > Here's an example: > ____________________________________________ > -- vital entity by place+route > -- vho = /usr0/tres/vhdl/xszero/synth/work > configuration vital of test_xszero is > for sim > for dut:socket > use entity vho.xszero(\ep1k50fc256-1\); > end for; > end for; > end configuration vital; > ______________________________________________ > > Or maybe you haven't written a vhdl testbench yet. > It is signals from the testbench architecture. > that drive your design instance. > > -- Mike TreselerArticle: 70354
hmurray@suespammers.org (Hal Murray) wrote in message news:<P5WdnZUv-YS0iFTdRVn-sA@megapath.net>...
> >Although the main power supplies on the board are OK, they actually
> >make good connectivity to a random number of power pads on the FPGA.
> >Each board has a different set of 'good' connections between the
> >power supply and the FPGA.
>
> Ugh. That's probably the worst sort of problem to have to track down.
>
> Any hints on how you found it? (just in case any of us are unlucky
> enough to encounter the same problem)
It took a lot of effort to find the problem. As it turns out,
the problem stumped our local FAE as well, and he's a pretty
sharp guy. Since the boards were flakey, almost any experiment
we performed was later invalidated by conflicting results from
another experiment. However...
1) I turned on the 'debug' flag in bitgen so that the data
output pin would wiggle during configuration. From this
it was clear that the download would fail at random points
in the download process.
2) I looked at signal quality of the clock and data input pin
to the target FPGA. As part of this, I re-clocked the
data being sent to the target back into my master so I could
verify that the proper data was being sent. Here was one of
the areas that snookered me. As part of these experiments,
I played around with slew rates on the pins being driven by the
master FPGA, sometimes things would get better, sometimes they'd
get worse. This led us down a signal integrity rat-hole.
3) I finally decided to re-verify suppy voltages at a couple of spots.
Luckily, I found unexpected voltages on a couple of bypass caps
pretty quickly. I then checked other boards and found different
voltage problems on other pins. This was the 'aha' moment.
During the process, I was trying to focus on:
a) bitstream correctness
b) signal integrity
c) supply voltage integrity.
Little did I suspect that the problem was random connectivity between
the supplies and the FPGA pins.
In all my years of design, I've never seen board problems like this. Odds
are most designers will never see boards that deteriorate over time like
this.
Article: 70355
A read on a row in SDRAM accomplishes a refresh, so if you read all used
rows within the refresh period, you do not need an explicit refresh. I've
used that in video applications on several occasions.
Tommy Thorn wrote:
> RANGA REDDY wrote:
> > is it true that Micron SDRAM does not require any refresh cycles if we
> > are reading the SDRAM rows once in 20 ms atleast? if i dont give any
> > refresh cycles what will be the condition of the SDRAM?
>
> AFAIK, *no* SDRAM requires refresh cycles if all the rows you care about
> are touched (read or written) sufficiently often. I think once every
> 64ms is enough.
>
> I've never seen anybody take advantage of that though.
>
> Tommy
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 70356In article <40C9D4DC.8060900@yahoo.com>, TommyAtNumba-Tu.Com-- not@yahoo.com says... > RANGA REDDY wrote: > > is it true that Micron SDRAM does not require any refresh cycles if we > > are reading the SDRAM rows once in 20 ms atleast? if i dont give any > > refresh cycles what will be the condition of the SDRAM? > > AFAIK, *no* SDRAM requires refresh cycles if all the rows you care about > are touched (read or written) sufficiently often. I think once every > 64ms is enough. > > I've never seen anybody take advantage of that though. The original IBM PC had one of the DMA channels set up to do periodic reads from contiguous locations to the DRAM refresh. -- KeithArticle: 70357
Apologies to those who don't like ads but this free and has no strings attached. It is biased to MicroBlaze and PicoBlaze on the basis of that is what we do most. If you are in our locality please let us know if you would like to attend. Link is http://www.enterpoint.co.uk/seminar/microblaze_intro.html John Adair Enterpoint Ltd. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted.Article: 70358
Chao wrote: > At first thanks for Mike's answer. But my exact question was how to > extract so many many internal signals which are listed during the > timing simulation. For example, _inbuf, _ibuf, _gst, etc. How can I > know which signal represents my original input signal or output > signal? The job of synthesis is to create a netlist of primitives (like dffe, inbuf etc. ) that sims the same as your code. You can view the netlist on tools like leonardo. I don't know of any way to relate primitives to your source code. Normally synthesis "just works". When it doesn't consider the following. 1. Double check the static timing report and synthesis warnings. 2. Eliminate asynchronous processes and multiple clocks. 3. Double check all inputs for synchronization. 4. Break the design into pieces zoom in on the problem. Good luck, -- Mike TreselerArticle: 70359
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Article: 70360iMPACT can convert a bitstream file to an SVF file automatically using the File Generation mode (Create SVF/XSVF Files Operation) Please check the on-line help for details. Yang-Tzu wrote: > Hi, > Is anyone has the experience of converting bitstream file format to > svf file format? > > It seems that iMPACT can't create svf file but bitstream file. > (Any document about this? The help of iMPACT have no solution. :( > ) > > Is anyone has the answer? > > thanks. > Yang-TzuArticle: 70361
We have a board with 2 Virtex II 6000 devices. They are programmed from independent bank of serial eeproms in Master serial mode. One of the FPGA's (slave fpga) is not being programmed consistently. On power up it sometimes programs and at times fails. If after powerup we manually start a programming cycle by pulling program pin low, it programs properly. Observed INIT pin going low before DONE goes high on slave FPGA, indicating CRC error. Also observed that slave FPGA initiates the program cycle earlier and has higher serial clock frequency than master.(using the lowest frequency 4 MHz) Hooked up logic analyzer and counted the clock cycles in the programming cycle. The slave FPGA clock count varies, both when it fails and when it programs(manual program intiation). When it fails it is lower than the required count but varies from one try to another. When it succeeds it is higher than required and also vaires from one try to another. Master FPGA clock count is always the same. Any suggestions on what could be causing this problem? Thanks BrijeshArticle: 70362
Markus Meng wrote: > Hi Thierry, > > difficult to say, what the problem could be, however it might be > worthwhile to always check "support.xilin.com" and simple type in > - as an example - "impact incorrect idcode" and read through the > database hits. It should give you a hint or an idea howto look closer > to your problem ... > > Concerning JTAG programming I think you need to disable one or the > other option - can't remember anymore - and the problem might disappear ... The guys who designed the hardware hardwired M2 and M1 to ground, it's nearly not possible to change them. I have read all on Xilinx Support, but nothing helped me. Also what I read if I understan it correct, JTAG has always priority over other programming.Article: 70363
rickman <spamgoeshere4@yahoo.com> wrote in message news:<40CB4C4A.9FB9CD47@yahoo.com>... > I am using RAM in a processor design and I am having trouble > understanding exactly how best to use these functions for my design. I Rick, I wish I had something more constructive to offer... I have a Stratix design and I use read latency of 2 cycles everywhere (one for address in, one for data out.) While one can eliminate the data output register it adds enough ns that it's just not worth it. I can't help noticing the (huge?) disparity between the 1K50 and the 3S400, and am surprised that you're still using the ACEX parts. In that vein, I'm carrying around the notion that _all_ newer FPGAs are or will require registered ports... so why not bite the bullet and go synchronous ? <snip> > I don't want to pipeline anything in this design to keep it very > simple. Right now the design is pretty clean and the delay paths are > pretty short. I'm also not sure from your post whether "pipelined" is synonymous with "registered", ie you're trying to do something like one instruction per clock cycle and/or you can't tolerate the 2 ticks latency. Also, what's you're desired clock speed ? Regards, -rajeev-Article: 70364
It seems to me that the Master tries to start programming too early after power-up. Peter Alfke ============= > From: Brijesh <brijesh_xyz@cfrsi_xyz.com> > Organization: Virginia Tech, Blacksburg, Virginia, USA > Newsgroups: comp.arch.fpga > Date: Mon, 14 Jun 2004 16:50:38 -0400 > Subject: FPGA serial programming troubles. (Virtex II) > > We have a board with 2 Virtex II 6000 devices. They are programmed from > independent bank of serial eeproms in Master serial mode. > > One of the FPGA's (slave fpga) is not being programmed consistently. On > power up it sometimes programs and at times fails. If after powerup we > manually start a programming cycle by pulling program pin low, it > programs properly. Observed INIT pin going low before DONE goes high on > slave FPGA, indicating CRC error. > > Also observed that slave FPGA initiates the program cycle earlier and > has higher serial clock frequency than master.(using the lowest > frequency 4 MHz) > > Hooked up logic analyzer and counted the clock cycles in the programming > cycle. The slave FPGA clock count varies, both when it fails and when > it programs(manual program intiation). When it fails it is lower than > the required count but varies from one try to another. When it succeeds > it is higher than required and also vaires from one try to another. > > Master FPGA clock count is always the same. > > Any suggestions on what could be causing this problem? > > Thanks > BrijeshArticle: 70365
Stephen Williams wrote: > Neil Glenn Jacobson wrote: > >> Sorry - typo - >> >> There is NO information that allows for customized cable use. >> >> The cable is for use only with Xilinx-supplied applications > > > And the Xilinx applications with ISE 6.1i cannot use it under > Linux. Correct? > > No. Applications like iMPACT and ChipScope should be able to use the cables under LinuxArticle: 70366
"rickman" <spamgoeshere4@yahoo.com> escribió en el mensaje news:40CB4C4A.9FB9CD47@yahoo.com... > I am using RAM in a processor design and I am having trouble > understanding exactly how best to use these functions for my design. I > will be using them to implement stacks, program memory and data memory. > Ideally the write function will look like an addressable register where > the address, data and enables are setup prior to the clock and the write > happens on the clock edge. The read should be async so that I can > provide an address and get data after a delay. > > The Altera part is an EP1K50 where the EAB read can be async. The write > however is only shown as either fully async or fully registered. I > recall that I was warned when reading and writing the same address the > data out has a longer delay. But I can't seem to find a reference to > that. I am also unclear if I can use the write the way I want or if it > requires input registers. > > The Xilinx part is an XC3S400 with dual port block rams. It seems like > the read path must be registered as well as the write path. I think I > could live with that if I could read the data that is being written (top > of stack) in the same clock cycle. But I belive the docs say that the > other port can either read the old data or is invalid. But then I may > be able to use a single port ram for a stack. The address would always > be pointing to the current TOS and as soon as a new value were pushed, > the next clock edge would read the new data as it is written to the new > address. > i dont know exactly how the spartan3 is related to the spartan2, but it might help you, check this out http://toolbox.xilinx.com/docsan/xilinx4/data/docs/lib/dsgnelpr5.html it says that when you write data, one of the ports reads what you're writting. From Coregen options i'd guess that you can also set it up as read-after-write (this one) or write-after-read (which would read the previous contents, and then write) > I don't want to pipeline anything in this design to keep it very > simple. Right now the design is pretty clean and the delay paths are > pretty short. > > Can anyone clarify how these rams work without pipelining? > Coregen ask you about that too, but the link i gave you dont mention anything. Though, if i recall correctly, i also read (somewhere in xilinx site) that the latency is dependant on the size of the RAM, bigger gets 2 cycles latency, but smaller can get 1 cycle i think. (sorry i dont have a link)Article: 70367
"Andrea Sabatini" <andrea@dapdesign.com> escribió en el mensaje news:40cd7bb7$0$6795$e4fe514c@news.xs4all.nl... > Matt, > > Thank you for your reply. I am now facing another problem. I would like to > call C routines from my assemble code but I did not found a place where > there is written how to do it. I am able to do it with routines that do not > need input parameters and do not return any value but I need to know how to > do it in a general case (presence of ins and outs). > check out the C calling convention > Thanks in advance, > > Andrea > > > "Matthew Ouellette" <matt.ouellette@xilinx.comNOSPAM> wrote in message > news:cai9bm$jn31@xco-news.xilinx.com... > > Andrea, > > > > If you are looking for ways on how to pass variables to assembly > > instructions in MicroBlaze, check out the very last passage in the > > following solution record: > > > > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= > 1&getPagePath=18561 > > > > Hope this helps, > > > > Matt > > > > Andrea Sabatini wrote: > > > > > Hi all. > > > > > > I have to write a code for the MicroBlaze soft processor (Xilinx > Platform > > > Studio 6.1.03i) and I am facing the following problem: both my assembly > code > > > and my c code have to access some shared (global!) variables but I do > not > > > know how to do it. I downloaded all the MicroBlaze documentation from > the > > > Xilinx web site (or at least I am convinced I did) but I did not find > any > > > clue. Does someone of you out there know how to do it? > > > > > > Regards, > > > > > > Andrea Sabatini > > > > > > > >Article: 70368
Xilinx (Virtex2 or Spartan3) BlockRAM reading while writing: Any write operation also performs a read, and outputs it on the Do output. The user can choose: write before read (= output the data that is being witten), or read before write (=output the previous content that is now being overwritten) or "no change"( keep the old data on the Do lines. Peter Alfke >Article: 70369
Hi Rick, I can offer my experiences with Xilinx blockram. You're correct that both the read and write are synchronous. There are three write options, WRITE_FIRST, READ_FIRST and NO_CHANGE. Carefully (!) read about these in the data sheet. I use WRITE_FIRST almost exclusively, where the "same clock edge that writes the data input (DI) into the memory also transfers DI into the output registers DO". When I did my processor design, I also used one as a stack. Like your design I didn't use pipelining. This was to keep the design small and simple. On the BlockRAM I used one port for PUSHING/POPPING registers, and the other for CALL/RETURN subroutine addresses. The catch with these blockrams is that, if you read from one port whilst you're writing to the *same* address on the other port, the read data is indeterminate. This makes sense if you think about what the BlockRAM is doing. Check out 'Conflict Resolution' in the user guide (I'm looking at ug012 for V2PRO). This means for me that I can't do a POP instruction immediately after doing a CALL subroutine, and I can't do a RETURN immediately after doing a PUSH. No problem to avoid this in the code, of course. It's a wierd thing to do anyway. The ModelSIM simulator also warns if conflicts occur and, of course, simulates the RAM accurately. Good luck! Cheers, Syms.Article: 70370
Here is the official Xilinx text (I just rewrote this for the new User
Guide).
Conflict Avoidance.
Virtex-2 BlockRAM is a true dual-port RAM where both ports can access any
memory location at any time. When accessing the SAME MEMORY LOCATION from
both ports, the user must, however, observe certain restrictions, specified
by the clock-to-clock set-up time window.See the following:
There are two fundamentally different situations:
The two ports either have a common clock ("Synchronous Clocking"), or the
clock frequency or phase is different for the two ports ("Asynchronous
Clocking").
Asynchronous Clocking is the more general case, where the active edges of
both clocks do not occur simultaneously:
There are no timing constraints when both ports perform a read operation on
the same location.
When one port performs a write operation, the other port must not read- or
write-access the same memory location by using a clock edge that falls
within the specified forbidden clock-to-clock set-up time window. (If this
restriction is ignored, a read operation might read unreliable data, perhaps
a mixture of old and new data in this location; a write operation might
result in wrong data stored in this location. There is, however, no risk of
physical damage to the device.)
Synchronous Clocking is the special case, where the active edges of both
port clocks occur simultaneously:
There are no timing constraints when both ports perform a read operation.
When one port performs a write operation, the other port must not write into
the same location, unless both ports write identical data.
When one port performs a write operation, the other port can reliably read
data from the same location if the write port is in READ_FIRST mode.
DATA_OUT will then reflect the previously stored data.
If the write port is in either WRITE_FIRST or in NO_CHANGE mode, then the
DATA-OUT on the read port would become invalid (unreliable). Obviously, the
read-port's mode setting does not affect this.
June 2004 Peter Alfke ( this text has not yet been posted on xilinx.com)
>
Article: 70371"rickman" <spamgoeshere4@yahoo.com> escribió en el mensaje news:40CB4C4A.9FB9CD47@yahoo.com... > I am using RAM in a processor design and I am having trouble > understanding exactly how best to use these functions for my design. I > will be using them to implement stacks, program memory and data memory. > Ideally the write function will look like an addressable register where > the address, data and enables are setup prior to the clock and the write > happens on the clock edge. The read should be async so that I can > provide an address and get data after a delay. > > The Altera part is an EP1K50 where the EAB read can be async. The write > however is only shown as either fully async or fully registered. I > recall that I was warned when reading and writing the same address the > data out has a longer delay. But I can't seem to find a reference to > that. I am also unclear if I can use the write the way I want or if it > requires input registers. > > The Xilinx part is an XC3S400 with dual port block rams. It seems like > the read path must be registered as well as the write path. I think I > could live with that if I could read the data that is being written (top > of stack) in the same clock cycle. But I belive the docs say that the > other port can either read the old data or is invalid. But then I may > be able to use a single port ram for a stack. The address would always > be pointing to the current TOS and as soon as a new value were pushed, > the next clock edge would read the new data as it is written to the new > address. > i dont know exactly how the spartan3 is related to the spartan2, but it might help you, check this out http://toolbox.xilinx.com/docsan/xilinx4/data/docs/lib/dsgnelpr5.html it says that when you write data, one of the ports reads what you're writting. From Coregen options i'd guess that you can also set it up as read-after-write (this one) or write-after-read (which would read the previous contents, and then write) > I don't want to pipeline anything in this design to keep it very > simple. Right now the design is pretty clean and the delay paths are > pretty short. > > Can anyone clarify how these rams work without pipelining? > Coregen ask you about that too, but the link i gave you dont mention anything. Though, if i recall correctly, i also read (somewhere in xilinx site) that the latency is dependant on the size of the RAM, bigger gets 2 cycles latency, but smaller can get 1 cycle i think. (sorry i dont have a link)Article: 70372
Quoting Peter's text from below, "When one port performs a write operation,
the other port must not write into the same location, unless both ports
write identical data."
For a one-port dedicated read and one-port dedicated write configuration
that I *believe* rickman is pursuing, a little trick could be used: feed
the data to *both* write ports and enable the write to the nomally read-only
port when a RdAddr==WrAddr compare is valid. This increases the effective
address setup time but gives the desired WRITE_FIRST functionality without
increasing the Clk-to-out time.
"Peter Alfke" <peter@xilinx.com> wrote in message
news:BCF3748F.69FD%peter@xilinx.com...
> Here is the official Xilinx text (I just rewrote this for the new User
> Guide).
> Conflict Avoidance.
> Virtex-2 BlockRAM is a true dual-port RAM where both ports can access any
> memory location at any time. When accessing the SAME MEMORY LOCATION from
> both ports, the user must, however, observe certain restrictions,
specified
> by the clock-to-clock set-up time window.See the following:
>
> There are two fundamentally different situations:
> The two ports either have a common clock ("Synchronous Clocking"), or the
> clock frequency or phase is different for the two ports ("Asynchronous
> Clocking").
>
> Asynchronous Clocking is the more general case, where the active edges of
> both clocks do not occur simultaneously:
> There are no timing constraints when both ports perform a read operation
on
> the same location.
> When one port performs a write operation, the other port must not read- or
> write-access the same memory location by using a clock edge that falls
> within the specified forbidden clock-to-clock set-up time window. (If this
> restriction is ignored, a read operation might read unreliable data,
perhaps
> a mixture of old and new data in this location; a write operation might
> result in wrong data stored in this location. There is, however, no risk
of
> physical damage to the device.)
>
> Synchronous Clocking is the special case, where the active edges of both
> port clocks occur simultaneously:
> There are no timing constraints when both ports perform a read operation.
> When one port performs a write operation, the other port must not write
into
> the same location, unless both ports write identical data.
> When one port performs a write operation, the other port can reliably read
> data from the same location if the write port is in READ_FIRST mode.
> DATA_OUT will then reflect the previously stored data.
>
> If the write port is in either WRITE_FIRST or in NO_CHANGE mode, then the
> DATA-OUT on the read port would become invalid (unreliable). Obviously,
the
> read-port's mode setting does not affect this.
>
> June 2004 Peter Alfke ( this text has not yet been posted on xilinx.com)
>
> >
>
Article: 70373I'm trying to increase the speed of my Stratix design and would like to change which FFs are turned on within a DSP block. The Stratix handbook shows the DSP path something like this: [ FF ] [ X ] [ FF ] [ + ] [ FF ] where [X] is the multiplier block, [+] is an accumulate block and all registers are optional. I don't use any of the accumulators, and I use pipeline_delay=2 going through the multiplier. What I find is (a) Quartus always invokes the first and 2nd FFs, viz [ FF ] [ X ] [ FF ] [ --> ] [ --> ] (b) There's > 1ns interconnect delay getting out from the 2nd FF. What I'd really like is to try [ FF ] [ X ] [ --> ] [ --> ] [ FF ] in the hope that this will give me faster overall operation. But I can't find any way to do this. I've looked at the multiplier tdf and it doesn't appear that the choice of which FFs to implement is brought out to HDL. What I'd like to learn is : (i) is the path I've diagrammed above possible in the Stratix hardware ? (ii) how can I make the software implement this ? Thanks for any help, -rajeev-Article: 70374
Neil Glenn Jacobson wrote: > > > Stephen Williams wrote: > >> Neil Glenn Jacobson wrote: >> >>> Sorry - typo - >>> >>> There is NO information that allows for customized cable use. >>> >>> The cable is for use only with Xilinx-supplied applications >> >> >> >> And the Xilinx applications with ISE 6.1i cannot use it under >> Linux. Correct? >> >> > > No. Applications like iMPACT and ChipScope should be able to use the > cables under Linux Even if this is iMPACT bundled with ISE *6.1i*? I was under the impression (based on APP notes and the like) that under Linux, iMPACT starts supporing the PCIV cable at ISE 6.2. Certainly, when I start impact, the radio button for Parallel Cable IV is grayed out. Are you saying that when the cable arrives, I'll be able to plug it in, install the Linux driver, and un-gray the selection? -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
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