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All, The 1.5 is important, but so is the origianl input frequency. There is a jitter calculator used to calculate the jitter for any M, D and input frequency. For M=3, D=2, and F=100 MHz, the jitter (worst case noisy system)is 630 ps peak to peak (9.5% of a UI) for V2 Pro DCM. Thus your timing slack for this clock domain has to be comfortably better than 1/2 of 630 ps (to allow for the shortest possible period). Austin Symon wrote: > I agree to 100ppm is irrelevant. But according to > http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm the factor does > matter. > I think you have to use the CLKFX output to multiply by 1.5, and the factor > is important. Or am I making a mistake, Peter? > Cheers, Syms. > "Peter Alfke" <peter@xilinx.com> wrote in message > news:40C74FC4.1ECD01C4@xilinx.com... > >>The 100 ppm is irrelevant, it describes a constant frequency error. >>The factor 1.5 is also irrelevant. >>The output jitter will equal the input jitter plus about 50 ps coming >>from the trim-tap uncertainty of the DCM. >>Peter Alfke > > >Article: 70226
Hi Austin, So, it's OK to assume the jitter is centred about the nominal ideal edge position? I.e. Does the positive peak jitter equal the negative peak jitter? Thanks, Syms. "Austin Lesea" <austin@xilinx.com> wrote in message news:ca7mpr$mov1@cliff.xsj.xilinx.com... > Thus your timing slack for this clock domain has to be comfortably > better than 1/2 of 630 ps (to allow for the shortest possible period).Article: 70227
"Steven K. Knapp" wrote: > > Being an engineer myself, I've never much liked the difference between LUTs > and logic cells. > > However, the story goes beyond just MUXFs. The Xilinx LUT delivers a few > other unique capabilities ... > > * 16x1 distributed RAM, either single-ported or with separate read/write and > read-only ports > - Roughly equivalent to 16 'D' flip-flops, two 16:1 output select MUXs, > and 16 4-input decode gates > > * 16-bit serial-in, serial-out shift register with tap select output > - Roughly equivalent to 16 'D' flip-flops, and 16:1 output select MUX > > Add that into the mix, I believe it comes out well ahead of the 12% fudge > factor. It is admittedly a fudge factor because not every design (okay, > except for Ray Andraka ;) will use every LUT as distributed RAM or shift > registers. That may well be, but I think most engineers that are using your parts understand the advantages of the Xilinx CLB design. How about if you limit the numbers in your data sheets to just the LUT count and drop marketing terms like "Logic Cells" which have no meaning in a data sheet since they are an *interpretation* and will vary according to the design. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70228
I stand corrected, very badly so. Sigh! Peter Alfke Peter Alfke wrote: > > The 100 ppm is irrelevant, it describes a constant frequency error. > The factor 1.5 is also irrelevant. > The output jitter will equal the input jitter plus about 50 ps coming > from the trim-tap uncertainty of the DCM. > Peter Alfke > > David Joseph Bonnici wrote: > > > > Consider you have 100ppm crystal oscillator, 80ps jitter driving a DCM > > that is configured to output x1.5 the input frequency. What will > > happen to the jitter? Will it increase or decrease? And by what > > factor?Article: 70229
Yes, the TDO has to be working as I am able to program and scan the other devices on the chain. "Neil Glenn Jacobson" <n.e.i.l.j.a.c.o.b.s.o.n@x.i.l.i.n.x.c.o.m.> wrote in message news:ca7egf$mou1@cliff.xsj.xilinx.com... > Do you have an external pull-up on TDO of the 2v2000? You need one. > > > Clark Pope wrote: > > I am able to program and scan Altera devices on my scan chain but when I go > > to load the Virtex2 I get an IR_Capture failure because the LSB on the > > Virtex is not being set. I am using a serial prom on that chip so I'm > > worried that it is trying to load at power up and messing up the JTAG in the > > chip. Anyone ever seen a problem like this? > > > > > >>>INFO:iMPACT:1206 - Instruction Capture = > > > > '0101010101000000010101000101000101010101010000000110101101' > > > >>>INFO:iMPACT:1207 - Expected Capture = > > > > '0101010101XXXX01XXXXXXXXXXXXXX010101010101XXXXXX01XXXXXX01' > > > > '0101010101XXXX01XXXXXXXXXXXXXX010101010101XXXXXX01XXXXXX01' > > > >>I generated the third line by reading the .bsdl > >>files for what the INSTRUCTION_CAPTURE value should be. So everything > >>matches except that the XC2V2000 is not setting the LSB to one. It must be > >>kept in reset or something... > >> > >>attribute INSTRUCTION_CAPTURE of XC2V2000_FG676 : > >>entity is > >>-- Bit 5 is 1 when DONE is released (part of startup > >>sequence) > >>-- Bit 4 is 1 if house-cleaning is complete > >>-- Bit 3 is ISC_Enabled > >>-- Bit 2 is ISC_Done > >> "XXXX01"; > > > > > >Article: 70230
Symon, Yes, it is. In addition, its histogram is gaussian in shape (from the CLKFX) output. Some folks have been really suprised that the jitter histogram is gaussian in shape, but does not have the same RMS to peak to peak ratio that is commonly assumed from a PLL (14 to 1), and yet it is still random....(power spectral density has no peaks). One can think of the output of the DCM as being multiple input clock jitter histograms (which are usually very gaussian from crystal oscillators), offset by a tap or two (at random + and -). Thus the peak to peak vs RMS is closer to 4:1 or 6:1. Austin Symon wrote: > Hi Austin, > So, it's OK to assume the jitter is centred about the nominal ideal edge > position? I.e. Does the positive peak jitter equal the negative peak jitter? > Thanks, Syms. > "Austin Lesea" <austin@xilinx.com> wrote in message > news:ca7mpr$mov1@cliff.xsj.xilinx.com... > >>Thus your timing slack for this clock domain has to be comfortably >>better than 1/2 of 630 ps (to allow for the shortest possible period). > > >Article: 70231
Altera engineering has been working with Spyros on this issue outside of the news group, but wanted to share the results in case anyone else is running into similar issues. The main problem was that a module used a different global net in the top-level then it did in the lower-level. Spyros solved this problem by locking down this pin in both the lower and higher level designs. Once that was done, the higher level project was forced to use the same global as the low level, and the routing constraints could be obeyed. Other tidbits that may be useful: 1. LogicLock regions automatically become floating when imported. The regions can be restored to a locked state using the TCL command "set_logiclock -region $region_name -floating false". 2. Virtual I/O's can be used when a lower-level IO is not meant to be an I/O at the top-level. This can help ensure routing constraints are legal. 3. Logiclock_export -routing does nothing unless routing has already been back-annotated. We will put a warning for this in future versions of the Quartus II software. It was a pleasure to work with Spyros on this issue. Stephen Brown, Altera Corp. lyberis@isd.gr (Spyros Lyberis) wrote in message news:<ebe66d13.0405110647.c7a33a@posting.google.com>... > Hi everyone, > > I'm near the completion of the final TCL flow for a Quartus II > hierarchical design (based on a previous comp.arch.fpga discussion > with the same subject). > > I ran into a problem while finalizing the TOP script, which is > supposed to import the locked, back-annotated BOTTOM regions and > simply connect them on a top level. > > The BOTTOM blocks, after they are fitted, are back-annotated and > exported along with their routing information. This is desirable, > because if the routing was not exported the final top-level > performance would not be guaranteed. However, there is a conflict > with the global clock networks. > > Specifically, when each BOTTOM block is compiled it automatically > promotes its high fanout nets onto global clocks. This, again, is > desirable. But if this process is done automatically by Quartus and > independently for each BOTTOM entity, when the BOTTOM blocks are > assembled by the TOP script the routing on the global clock networks > makes the fit impossible: Quartus has used the same global > resources for different top-level nets. > > Is there any way that I can assign a _specific_ global clock network > to a design node? Note that while a BOTTOM entity is compiled, the > source of this global clock is not yet known: in my case, this > global clock network will be driven by a different BOTTOM entity > which is the reset controller (or a PLL with many output clocks). > > Does Quartus support this? The assignments "global signal" and > "auto global clock" simply declare that a signal will be promoted > to a global clock network, but do not specify _which_ of the > available global clock networks will be used. Does anybody know > something on this? > > Thanks in advance, > SpyrosArticle: 70232
Peter, Your answer is correct for the DLL outputs, CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X_b, and CLKDV. For example, if they had said "divided by 1.5" you are correct. But not for CLKFX, and CLKFX_b. 7 out of 9 is not all that bad...... Also the 100ppm doesn't have anything at all to do with it. I also forgot to add the square root of the sum of the squares (sqr ((630^2)+(80^2)) ~ 635 ps ) to get the total jitter out (clock + DCM). Austin Peter Alfke wrote: > I stand corrected, very badly so. Sigh! > Peter Alfke > > Peter Alfke wrote: > >>The 100 ppm is irrelevant, it describes a constant frequency error. >>The factor 1.5 is also irrelevant. >>The output jitter will equal the input jitter plus about 50 ps coming >>from the trim-tap uncertainty of the DCM. >>Peter Alfke >> >>David Joseph Bonnici wrote: >> >>>Consider you have 100ppm crystal oscillator, 80ps jitter driving a DCM >>>that is configured to output x1.5 the input frequency. What will >>>happen to the jitter? Will it increase or decrease? And by what >>>factor?Article: 70233
How about a 32 macrocell....x I mean LUT device. With an on board flash memory you'd find a market. If Xilinx had it's own packaging house, like Microchip, such a device might prove to be juicy, so to speak. Hul Steven K. Knapp <steve.knappNO#SPAM@xilinx.com> wrote: > Being an engineer myself, I've never much liked the difference between LUTs > and logic cells. > > However, the story goes beyond just MUXFs. The Xilinx LUT delivers a few > other unique capabilities ... > > * 16x1 distributed RAM, either single-ported or with separate read/write and > read-only ports > - Roughly equivalent to 16 'D' flip-flops, two 16:1 output select MUXs, > and 16 4-input decode gates > > * 16-bit serial-in, serial-out shift register with tap select output > - Roughly equivalent to 16 'D' flip-flops, and 16:1 output select MUX > > Add that into the mix, I believe it comes out well ahead of the 12% fudge > factor. It is admittedly a fudge factor because not every design (okay, > except for Ray Andraka ;) will use every LUT as distributed RAM or shift > registers. > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/II/IIE FPGAs > http://www.xilinx.com/spartan3 > --------------------------------- > Spartan-3: Make it Your ASIC > > "Marc Randolph" <mrand@my-deja.com> wrote in message > news:c9mdnbfiOc81YVvdRVn-uA@comcast.com... >> rickman wrote: >> > Jan Gray wrote: >> > >> >>I wrote "Up to 200 kLUTs", but to be precise, the Xilinx press release >> >>states "With up to 200,000 logic cells...". >> >> >> >>Not the same thing, LUTs and logic cells. Sorry about that. >> > >> > >> > Are you talking about the 12% inflation factor, or are logic cells >> > actually something different than a LUT plus a FF? Anyone know what a >> > logic cell is? >> >> Xilinx's definition is: >> >> "Logic cell = One 4-input Look Up Table (LUT) + Flip Flop + Carry Logic" >> >> If I recall, they are not including the MUXFx's that are after the LUTs. >> As you correctly surmised, Xilinx feels those are worth an additional >> 12% (so there are ~12% more logic cells than there are LUTs). >> >> Are they right? The high speed (311 MHz, therefore heavily pipelined) >> design I'm working on right now uses >> >> 457 MUXF's plus >> 6170 LUTs >> >> So they're only off by 50% or so. A slower design that isn't nearly as >> well pipelined uses: >> >> 2618 MUXF's plus >> 22832 LUTs >> >> Which is noticeably less than 12%, but closer to their marketing number. >> >> Marc > >Article: 70234
I am implementing a SERDES transceiver using the LPM_SHIFTREG as serializer. In simulations, the register loads new parallel word only when the load signal is active during the time when clock is '0'. The help states that it should be active on the +ve clock edge. I can't find any reasonable documentation about this megafunction, so wonder if anyone know what might be the problem ? (The target is Stratix device. The reason I am not using the Megafunction SERDES transceiver is because it can be used only above 300Mbps) VadimArticle: 70235
petersommerfeld@hotmail.com (Peter Sommerfeld) wrote in message news:<5c4d983.0406090721.24479ad@posting.google.com>... > Hi Rick, > > Yes I've taken the route of developing my own. The opencores one > didn't cut it - 2000 LEs and 64 MHz fmax, which is much too big and > slow for me (mind you, it lets you change SDRAM timing parameters on > the fly via registers, but that's a feature I don't need). > > Like you say, after poring over some Micron datasheets and drawing up > a state machine it didn't seem too difficult. My first compile has > fmax 135 Mhz without setting a target fmax in Quartus, and 780 LEs > (could be less with register packing option turned on). I also added > something I think might be useful, which is piling up refresh events > so that they are done only at the end of a long bursts, instead of > interrupting them. Hopefully this will help reach theoretical max > bandwidth in the case of long bursts within open rows followed by a > bit of idle time (exactly the model of my video app). > > Now comes the task of testbenching and debugging. I was hoping I > didn't have to reinvent the wheel, but I think I'll have exactly what > I want when I'm done. > > -- Pete > > Both X & A have loads of appnotes on these controllers and esp they get into board and signal, timing issue. By the time I read the Micron and Xilinx and PLD notes, I felt the same way (reading the same thing over & over), doing your own will get you a direct interface that will maybe be smaller than the general designs. regards johnjakson_usa-comArticle: 70236
Philip Freidin wrote: > Note that the parallel versions [of CRCs] can not > be made to work with data streams that are not an integer multiple > of bits of the width you choose for the parallel version. Allan Herriman wrote: > This is not true in general. There's a number of ways of getting wide > parallel CRC calculators to work with frames of any length. > > I call these the "ragged start word" and "ragged end word" problems if > the packet does not start or end on a word boundary. I had to do this for USB CRC-5 on a processor with an instruction to do an 8-bit-at-a-time CRC with a polynomial of up to 32 bits (Ubicom IP3023). Preloading the CRC register with a suitable value caused the CRC to be the all-ones initialization value *after* the extra zero bits at the high end of the data were computed into the CRC. I wrote a simple C program to do a brute-force search for the correct values, but a more clever approach might be possible by running the CRC backward.Article: 70237
Thanks for the tips, these are the little things you don't find in the manuals. Jason "John_H" <johnhandwork@mail.com> wrote in message news:HgGxc.3$eB5.231@news-west.eli.net... > "Jason Berringer" <look_at_bottom_of@email.com> wrote in message > news:n4txc.32812$sS2.988493@news20.bellglobal.com... > > My recent task had me interacting with XST and altering the settings to > > highest effort to achieve the timing constraint that I had. I eventually > had > > to use the reentrant route feature to finally make the constraint. I would > > imagine that using some floorplanning might have helped me out, but as I > > have yet to get into the basics of floorplanning yet I felt to try and > just > > push the tools more. Since I brought it up, do you use floorplanning when > > doing a desing, and if so, where is the best place to start. Is the idea > to > > get things as close as possible keeping the routing as short as possible, > or > > just to focus on specific areas that might use faster clocks, and require > > short delays? > > If you need to resort to placing your logic, I'd suggest you first consider > RPMs - relationally placed macros - to deal with critical paths. If you > have a 25MHz clock that has one flop that always goves you troubles, the > paths that drive that flop may be more routing than logic. A good rule of > thumb for "decent" routing is 50% routing, 50% logic as reported by the > timing analyzer. If you're at 60% logic and you're still having troubles > meeting timing, look seriously at ways to redo the logic. If you're at 70% > routing, RPMs can place critical components within that path closer together > without tying them down to an absolute slice. I'll use explicit LOC > location constraints on signals that interact with the I/O cells that have > been LOC'ed for my PCB pinout but for logic-to-logic paths I typically use > the RLOC relative placement constraints. > > As far as using the floorplanner tool, I haven't because of early bugs when > the tool was first coming out. The user constraints file can include > everything you need; you can often put the constraints in your source code > if you find that a better place to document your placement constraints. > > In general, you will get better results if related logic is confined to a > specific area of the chip using the AREA_GROUP constraint on a module; > several wildcard-selected signals can also be kept in a small range to help > meet timing on particular paths without resorting to RLOCs. > > There are many ways to skin the cat. Sometimes it's the place & route > that's giving you troubles. Sometimes it's the synthesizer that's throwing > in 7 levels of logic onto a critical signal that could have been included in > the last level of logic. It's times like that that it's better to recode to > coax your synthesizer or seriously look at a new synthesizer that will know > better in the first place. > > Timing is often the most annoying part of high performance design but the > results from attention to detail can get you into a lower speed grade device > or a higher margin design. > >Article: 70238
<pop> escribió en el mensaje news:ee86f56.-1@webx.sUN8CHnE...
>Hi
>
>I have inherited a design containing both asyncrous and syncronous FF. I
started to rewrite the code but started to doubt the strategy. Does >anybody
know which is better. The FPGA is very large.
hi,
i'd also like to know if there are design guidelines about reset as there
are for clocks. Like i know that you shouldnt put any logic on the clocks as
it messes with the clock tree generation, but is there design rules about
reset for ASIC and FPGA?
is it good or bad practice to put something like
process(clk, reset, reset2)
begin
if reset = '0' or reset2 = '1' then
reset stuff;
elsif clk'event and clk = '1' then
sync stuff;
end if;
end process;
instead of:
process(clk, reset)
begin
if reset = '0' then
reset stuff;
elsif clk'event and clk = '1' then
if reset2 = '1' then
reset stuff;
else
sync stuff;
end if;
end if;
end process;
because the second approach will use muxes, while the first one will use
only gates in the reset path to the DFFs
i started reading about resets, but i think i still havent read anything
about not putting logic in the reset path
Article: 70239geoffrey brown <geoffrey.DeLeTebrown@acm.orgDeLeTe> wrote in message news:<jjixc.16271$4S5.13174@attbi_s52>... > Has anybody actually received updates to their Quartus and Nios toolkits > to support Nios II ? > > Geoffrey Hi Geoffrey, The Nios II development kits for Cyclone and Stratix begin shipping next week (week of June 14). Updates to Nios subscribers ship the following week. If you have an urgent need to get the update sooner, please email me. Best Regards, Bob Bob Garrett Altera Product Marketing Manager, NiosArticle: 70240
Wednesday June 9, 10:04 pm ET SAN JOSE, Calif., June 9 /PRNewswire-FirstCall/ -- Xilinx, Inc. (Nasdaq: XLNX - News) today sadly announced the passing of Bernard (Bernie) V. Vonderschmitt, Xilinx co-founder, Chairman Emeritus and former Chairman of the Board. Vonderschmitt died earlier today in his hometown of Jasper, Indiana. http://biz.yahoo.com/prnews/040609/sfw097_1.html -- Phil Hays Phil_hays at posting domain should work for emailArticle: 70241
San San wrote:
> I wonder who is using lancelot daughter board for altera bios dev board?
> Can we exchange email for discussion?I have many problem about this. I am
> green to FPGA system design.
Most certainly. H. Peter Anvin started a mailing list for the Lancelot
+ Altera Nios Dev boards (see below) that you should join. Framebuffer
graphics is pretty easy (mine is about a page). Sounds is interesting,
but HPAs Sigma-delta converter is on the Lancelot page. PS/2 kbd and
mouse is mostly a software issue, but HPAs ABC80 supports keyboard.
Tommy
Here the call from participation:
Hi all,
I have no idea how big this community is, but I've been trying to set
up a mailing list for people who hack the Altera NIOS kits
(APEX/Cyclone/Stratix) and especially using the Lancelot boards from
www.fpga.nl.
This may sound rather restrictive, but the hope is that there will be
enough of a group that we can trade designs around.
The subscription/archives page is at:
http://www.zytor.com/mailman/listinfo/lancelot
I hope we can get some people together, at least.
-hpa
Article: 70242Bob Garrett wrote: > The Nios II development kits for Cyclone and Stratix begin shipping > next week (week of June 14). Updates to Nios subscribers ship the > following week. If you have an urgent need to get the update sooner, > please email me. > > Bob Garrett > Altera > Product Marketing Manager, Nios Any news on when a Stratix-II Dev kit will be available? TommyArticle: 70243
In other words, are there any chances to meet with Spartan-4 (or kind of that) family in the future? It looks like Virtex-4 SX is successor for Virtex-II and Virtex-4 FX - for Virtex-II Pro. ValeriArticle: 70244
But seriously, has anyone had any experience (good or bad) programming
xilinx devices over JTAG with third party devices in the chain.
I'm using impact under linux, from the command line. And impact is
having real trouble with an Atmel BSDL file.
I've tried programming a chain with just xilinx devices and it works
fine. As soon as impact has to read a third party BSDL it has a fit and
stops working.
Here's the error
ERROR:iMPACT:1353 - ACD entry PROGRAM_PROGRESS_COUNT not found for device
family ATMEGA128.
EXCEPTION:iMPACT:ConstraintsManager.c:394:1.34.2.1 - Data not found.
I've tried using the Xilinx generic BSDL file and it gives the same error.
INFO:
ISE 6.2 (Services Pack 2)
JTAG chain: Atmel AVR -> Xilinx Spartan IIE
Impact batch file:
setMode -bs
setCable -port lpt1
#assignFile -p 1 -file "atmega128.bsd"
addDevice -p 1 -part "atmega128.bsd" # BSD file for AVR
addDevice -p 2 -file "xmemtest.bit" # Bit File for Spartan
program -p 1
quit
If anyone can throw some light on this problem it would be a _REAL_ help.
Many thanks
Andy
--
Andrew Greensted Department of Electronics
Bio-Inspired Engineering University of York, UK
Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk
Fax: +44(0)1904 433224 Web: www.bioinspired.com
Article: 70245hi, i just noticed that the clock on the submodules of my top module is delayed (about 1,3ns) with respect to the clock on the top module. im new to xilinx FPGA's and ISE so i might be forgetting something?? maybe DCM??, i use only VHDL entry so i havent instantiated any, should i? im using xc2v4000 and ISE 5.2i i think thanksArticle: 70246
Hi, If anyone from Xilinx is listening, would they consider changing TSMCCCS (hold time of CS_b from CCLK rising in SelectMAP mode) to -0.5ns or so? TSMCCCS is currently 0.0ns in V2P and +1.0ns in older parts. This change would enable CS_b and CCLK to be tied together on the board, which simplifies certain applications which involve the FPGA being configured from a CPU, with CS_b and CCLK both coming from the same output of a chip select decoder. CS_b and CCLK aren't close on the package, and 0.5ns would be sufficient to allow for delays on the PCB between the two pins. (Perhaps CS_b and CCLK could be moved closer together? This would also help signal integrity.) I recently saw a design using a SpartanIIE (which requires +1.0ns of hold time) that had an RC network on the board to provide the delay. Thanks, Allan.Article: 70247
Hopefully this information might save someone else some time. If you're using ISE6.2 under Linux, and want to use an old programming cable, such as the Parallel Cable III (DLC5). you need to compile your own Linux drivers. This Answers Database record has the info: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18612 Here's a few pointers. Make sure that the version of kernel you are running, matches the kernel source you have installed. The xilinx makefile uses uname -r to find this out. So do uname -r at a command line, and check that the kernel files in /usr/src match this and the files in /lib/modules match too. If they don't, try doing an update of your system, updating both kernel and kernel source (I'm a SuSE user, and in this case use the online update). Then REBOOT, this makes sure that the version uname returns matches that installed. Hope this helps Andy -- Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, UK Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 433224 Web: www.bioinspired.comArticle: 70248
Think I jumped for the newsgroup too soon there. Spot the deliberate mistake in the batch file, was trying to program the wrong device. Sorry Andrew Greensted wrote: > But seriously, has anyone had any experience (good or bad) programming > xilinx devices over JTAG with third party devices in the chain. > > I'm using impact under linux, from the command line. And impact is > having real trouble with an Atmel BSDL file. > > I've tried programming a chain with just xilinx devices and it works > fine. As soon as impact has to read a third party BSDL it has a fit and > stops working. > > Here's the error > > ERROR:iMPACT:1353 - ACD entry PROGRAM_PROGRESS_COUNT not found for device > family ATMEGA128. > EXCEPTION:iMPACT:ConstraintsManager.c:394:1.34.2.1 - Data not found. > > I've tried using the Xilinx generic BSDL file and it gives the same error. > > INFO: > ISE 6.2 (Services Pack 2) > JTAG chain: Atmel AVR -> Xilinx Spartan IIE > Impact batch file: > > setMode -bs > setCable -port lpt1 > #assignFile -p 1 -file "atmega128.bsd" > addDevice -p 1 -part "atmega128.bsd" # BSD file for AVR > addDevice -p 2 -file "xmemtest.bit" # Bit File for Spartan > program -p 1 > quit > > If anyone can throw some light on this problem it would be a _REAL_ help. > > Many thanks > Andy > -- Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, UK Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 433224 Web: www.bioinspired.comArticle: 70249
Hello, I use quartus II 4.00 and SOPC builder 4.00 to build a NIOS system on a Stratix II board. I enabled the support for external interruptions, add a user defined IP connected via the provided avalon ahb bridge. Everything is ok. Then I try to use the interruption of the bridge, everything on the wire is ok until the data_master_irq gets high. The iq number is ok, NIOS makes a couple of instructions more and then stops on a strange adress (totallly out of the memory map). but it doesn't fetch the ISR code indeed. The soft uses nr-installusr and is exactly the same as the examples provided. I tried whithout any soft isr and initialisation to see if i get the famous message ... but nothing. How can I be sure of what is done by the compiler, is there any restriction that I don't respect ? thanks for all your help and experience about those interrupts on NIOS systems. Sincerely Julien Chevalier
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