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>problem. The only thing I can see is that maybe the Ethernet/PHY chip >they use defaults to 10 Mbps, even though it says it auto detects to >100 or 10. Plug both lines into a switch/hub and look at the lights to find out what speed the link is running at. Put a scope on the wire... (or one of the wires going to the PHY chip) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 70401
Semantic confusion: It seems that your board fails in slave mode. In slave mode the FPGA is not in charge of generating CCLK, it is at the mercy of a foreign master who generates the clock. My thought is that this foreign master is too impatient and starts the clocking too early, before the FPGA is ready. Just a thought... Peter Alfke ========== > From: Brijesh <brijesh_xyz@cfrsi_xyz.com> > Organization: Virginia Tech, Blacksburg, Virginia, USA > Newsgroups: comp.arch.fpga > Date: Tue, 15 Jun 2004 09:58:36 -0400 > Subject: Re: FPGA serial programming troubles. (Virtex II) > > Hello Peter, > > Did you mean the slave FPGA? Thats the one that is giving trouble and > starts programming 1ms earlier than master. > > What factors can cause this on a FPGA? > Both master and slave share the ground and power planes. > Is the poweron voltage ramp causing the issue? Since they both share > power planes it should affect both the same way. So poweron voltage ramp > is probably not the issue. > > Thanks for taking time out to respond. > Brijesh > > > > > Peter Alfke wrote: >> It seems to me that the Master tries to start programming too early after >> power-up. >> >> Peter Alfke >> ============= >> >>> From: Brijesh <brijesh_xyz@cfrsi_xyz.com> >>> Organization: Virginia Tech, Blacksburg, Virginia, USA >>> Newsgroups: comp.arch.fpga >>> Date: Mon, 14 Jun 2004 16:50:38 -0400 >>> Subject: FPGA serial programming troubles. (Virtex II) >>> >>> We have a board with 2 Virtex II 6000 devices. They are programmed from >>> independent bank of serial eeproms in Master serial mode. >>> >>> One of the FPGA's (slave fpga) is not being programmed consistently. On >>> power up it sometimes programs and at times fails. If after powerup we >>> manually start a programming cycle by pulling program pin low, it >>> programs properly. Observed INIT pin going low before DONE goes high on >>> slave FPGA, indicating CRC error. >>> >>> Also observed that slave FPGA initiates the program cycle earlier and >>> has higher serial clock frequency than master.(using the lowest >>> frequency 4 MHz) >>> >>> Hooked up logic analyzer and counted the clock cycles in the programming >>> cycle. The slave FPGA clock count varies, both when it fails and when >>> it programs(manual program intiation). When it fails it is lower than >>> the required count but varies from one try to another. When it succeeds >>> it is higher than required and also vaires from one try to another. >>> >>> Master FPGA clock count is always the same. >>> >>> Any suggestions on what could be causing this problem? >>> >>> Thanks >>> Brijesh >> >>Article: 70402
> Instead of you spending time creating the code, I have attached some > modules. Goran, thanks a lot for such an interesting example of VHDL power. I couldn't care less for a baudrate generator, but I liked a lot the way it's handled. Very clever. BTW, with default stated generics it compiles with XST (6.1SP3) in 3 slices in a Spartan III. I had to comment out the "library opbxxxx" lines, tough. Thanks again! Have you some other more ? ;-))Article: 70403
Hi, Glad that you liked the code. I think it's showing the power of a programming language like VHDL. Yes, I have more code but that is MicroBlaze and I can't send out that. ;-) Göran Bilski Antonio Pasini wrote: >>Instead of you spending time creating the code, I have attached some >>modules. >> >> > >Goran, > >thanks a lot for such an interesting example of VHDL power. >I couldn't care less for a baudrate generator, but I liked a lot the way >it's handled. Very clever. > >BTW, with default stated generics it compiles with XST (6.1SP3) in 3 slices >in a Spartan III. > >I had to comment out the "library opbxxxx" lines, tough. > >Thanks again! > >Have you some other more ? ;-)) > > > > >Article: 70404
Yes, this path is possible to implement in the hardware. Using the altmult_add Megafunction you can control explicitly which registers are used in the DSP Block, while the lpm_mult Megafunction only gives you an option to specify the number of pipeline stages. Using the altmult_add MegaWizard, create an altmult_add instantiation with 1 multiplier, which ensures only the multiplier portion will be used (the adder portion will not be used). Within this MegaWizard, you can explicitly specify which registers to use. To achieve what you want, you should use the input registers and extra ouput register, but disable the multiplier output register. Hope this helps. Subroto Datta Altera Corp.Article: 70405
Hey Goran, How about posting the code direct. Not all of us have news hosts that can pass on attachments! Ta, Syms.Article: 70406
Thanks Mike and Jim for the replies, I will go off and digest this and see what happens. This is also the first time I have used the groups, thank you very much for the replies. Paul Mike Harrison <mike@whitewing.co.uk> wrote in message news:<t7ftc0l7fj5fqu89qpgpri2btgfntnciis@4ax.com>... > On 14 Jun 2004 18:38:54 -0700, accrg@accrepairs.com (Paul K) wrote: > > >I am very new to PAL programming. I have created a few to decode > >addresses. I have been using the ATMEL 16V8 PAL and WINCUPL. > > > >I now need to latch data appearing on 3 inputs when a certain > >condition is met on 3 other inputs. > > > >I need to latch the data on a cpu data buss D0, D1, & D2 when the > >signal write (WR\) is low, and the signal chip enable (CE\) is low and > >the signal output enable (OE\)is high, then latch the data on D0-D3. > > > >I currently have the circuit working with a 74LS02 (NOR)with the > >inputs tied to WR\ and OE\, the output of the NOR goes to a 74LS08 > >(AND)the other input is tied to OE\. The output of the AND gate feeds > >a 73LS273 latch. I will be latching on the falling edge of WR\ > > > >I don't have room for the 3 TTL chips so I am trying to move it to the > >16V8. > > > >I am not sure how to approach the latch, any help or push in the right > >direction would be greatly appreciated. I have had a hard time > >finding examples using the latching feature. > > > >Thanks, Paul > > My CUPL is a little rusty so excuse any punctuation errors... > > pin[2..5] = [d0..3]; > pin[12..15] = [q0..3]; > pin[6,7,8] = [!ce,!oe,!wr]; > > field din=[d0..3]; > field dout=[q0..3]; > > enable = !CE & OE & !WR; > > dout = !enable & dout /* hold latch contents by feeding output back to input */ > # enable & din;Article: 70407
In 2003, Xilinx was saying higher static power was an inevitable price of progress, and that speed was king, and nothing was on the Horizon to solve this..... It is interesting to read this latest press release http://www.xilinx.com/prs_rls/silicon_vir/0470umc_tripleoxide.htm "By using three different thicknesses of the insulating gate oxide layers, the companies were able to break the traditional tradeoff between power consumption and performance, and expect to lower static and dynamic power consumption by 50 percent from previous generation devices with the Virtex-4 platform FPGA family." Some real numbers would be nice : Just where are we now (V4 samples), on the static power spectrum ? '50 percent' is not great, but is much better than another step in the wrong direction :) and also this, which is more on the horizon @ 65nm: http://www.eet.com/semi/news/showArticle.jhtml;jsessionid=GJVUXDA2224GYQSNDBCCKHQ?articleId=21800471 seems the foundries/R&D are very aware of the importance of static Icc in many applications, and they are working to tune the process to allow designer selection. Cutting edge silcon EDA tools now talk about 'power closure', in the same way timing closure was the hot button a couple of years ago. -jgArticle: 70408
Stephen Williams wrote: > Neil Glenn Jacobson wrote: > >> >> >> Stephen Williams wrote: >> >>> Neil Glenn Jacobson wrote: >>> >>>> Sorry - typo - >>>> >>>> There is NO information that allows for customized cable use. >>>> >>>> The cable is for use only with Xilinx-supplied applications >>> >>> >>> >>> >>> And the Xilinx applications with ISE 6.1i cannot use it under >>> Linux. Correct? >>> >>> >> >> No. Applications like iMPACT and ChipScope should be able to use the >> cables under Linux > > > Even if this is iMPACT bundled with ISE *6.1i*? I was under the > impression (based on APP notes and the like) that under Linux, > iMPACT starts supporing the PCIV cable at ISE 6.2. Certainly, when > I start impact, the radio button for Parallel Cable IV is grayed > out. Are you saying that when the cable arrives, I'll be able to > plug it in, install the Linux driver, and un-gray the selection? You know sometimes I wonder just how awake I am... Yes, Linux usage of the parallel cable was first supported in 6.2i thus all statements about Xilinx application support refer to release 6.2i and later. This means that if you are unable to upgrade to 6.2i or later and need to use the parallel cable and Linux then you are stuck. The (slower) MultiLINX cable is your only download option on Linux previous to 6.2i Sorry for all the confusion but I think we have it straightened out now. > >Article: 70409
Symon wrote: > Hey Goran, > How about posting the code direct. Not all of us have news hosts that can > pass on attachments! > Ta, Syms. ..or maybe a couple of links into a Xilinx.com\comp.arch.fpga.Date.ID.YGTI.. one link could be vanilla text, and one html syntax highlighted (many editors now have a save-as html option), and you can also copy/paste from a web browser into a text editor, and keep just the code. This also allows bookmarking, and avoids anyone bleating about bandwidth usage... I presume everyone can web-link from their news readers OK ? -jgArticle: 70410
hey all, Anybody know about limitations on the length of a parallel cable attached to the xilinx P IV cable? I have the cable attached to my PC via two 10' parallel extension cables and it does not work at all. thanks MattArticle: 70411
How about digital logic design engineer? What kind of math required other than basic arithmetic? And don't they need a lot less math than say an RF engineer? HendraArticle: 70412
nevermind, my mistake i got it working with the 2 10' extensions. Matt On Tue, 15 Jun 2004, Matthew E Rosenthal wrote: > hey all, > Anybody know about limitations on the length of a parallel cable attached > to the xilinx P IV cable? > I have the cable attached to my PC via two 10' parallel extension cables > and it does not work at all. > > thanks > > Matt >Article: 70413
On Tue, 15 Jun 2004 15:21:50 -0700, "Symon" <symon_brewer@hotmail.com> wrote: >Hey Goran, >How about posting the code direct. Not all of us have news hosts that can >pass on attachments! >Ta, Syms. Or, just wait till the end of the month when it will turn up in the archive at www.fpga-faq.com Philip =================== Philip Freidin philip.freidin@fpga-faq.com Host for WWW.FPGA-FAQ.COMArticle: 70414
Thanks Mike. I kindly of understand it now. But what is the best way to handle clock domain crossing where you need to synchronize between the two domains. And I guess the clock domain part circuit really needs to be tested with gate level simulation with the sdf back annotation, right? I mean that is not part of synchronous design. Thanks again! "Mike Treseler" <mike_treseler@comcast.net> wrote in message news:nt6dnfiFBpToq1DdRVn-hQ@comcast.com...Article: 70415
I am trying to importing a design from maxplus2 to quartus, and having trouble for whole day. I imported the .acf file without too much trouble, and compiled it in quartus. Well, I got this weird error saying that LPM_DECODE's PIPELINE value has to be great 0 if clock is used. But PIPELINE parameter value does have a value of 1. So I don't know why it is doing that. So I updated the symbol, and somehow it was fixed. But for some strange reason, the .sof target to a flex10k10a part just won't work. The same design compiled under the maxplus2 works fine. Am I missing anything here. Thank you very much! CharlesArticle: 70416
Hello Guys,
I am using the SOPC builder to design a simple system that integrates
a couple of UARTS, a soft processor and a VHDL blackbox (Connected
internally in user design logic). I export a 8-bit wide signal which
are connected to LEDs on-board from the blackbox. I am using the Nios
Development Board Pro Edition. My VHDL code is as follows:
Libraries blah blah...
entity count is
port(
clk: in std_logic;
write_con: in std_logic;
chipsel: in std_logic;
write_data: in std_logic_vector(1 downto 0);
export
dataout: out std_logic_vector(7 downto 0));
end count;
architecture RTL of count is
signal counter: std_logic_vector(7 downto 0);
signal write_data_d: std_logic_vector(1 downto 0);
signal resetn_d: std_logic;
signal control: std_logic;
begin
control<= write_con and chipsel;
count_proc: process(clk, control, counter, write_data)
begin
if clk'event and clk='1' then
if ((write_data="00") and control='1') then
counter<=(OTHERS=>'1');
elsif ((write_data="01") and control='1') then
counter<=counter+1;
elsif ((write_data="10") and control='1') then
counter<="00001111";
else
counter<= "01010000";
end if;
end if;
end process count_proc;
dataout<= counter;
end RTL;
////////////////////////////////////////////////////////////////////////////
My C code in the src directory is as follows:
#define point1 *((int *)(na_user_logic_altera_avalon_pwm_0_base))
void main()
{
while(1)
{
point1=1;
}
}
I am assuming that I am writing directly to the write_data port (In
VHDL) so I should be expecting a dim LED for the MSB and a bright one
at the LSB. However, all I get is 2 bright LEDs (else condition). I
checked the manuals but there wasn't any explicit instructions on how
to use the header files for user design logic. Any direct help will be
greatly appreaciated. Any reference to material will also be welcomed
too. Cheerio!
Ted
Article: 70417Hi Charles, Can you try using Quartus II v 4.0? Either way please send me a zip of the Max+Plus II project at sdatta@altera.com and we will definitely analyze the problem regarding the PIPELINE parameter. Subroto Datta Altera Corp. "charles" <czheng@ieee.org> wrote in message news:nwNzc.28428$Hg2.10568@attbi_s04... > I am trying to importing a design from maxplus2 to quartus, and having > trouble for whole day. I imported the .acf file without too much trouble, > and compiled it in quartus. Well, I got this weird error saying that > LPM_DECODE's PIPELINE value has to be great 0 if clock is used. But > PIPELINE parameter value does have a value of 1. So I don't know why it is > doing that. So I updated the symbol, and somehow it was fixed. But for > some strange reason, the .sof target to a flex10k10a part just won't work. > The same design compiled under the maxplus2 works fine. Am I missing > anything here. > > Thank you very much! > > Charles > >Article: 70418
Ok,
Here is the two files inlined.
Göran
-------------------------------------------------------------------------------
-- $Id: divide_part.vhd,v 1.2 2003/02/13 16:13:28 goran Exp $
-------------------------------------------------------------------------------
-- divide_part.vhd - Entity and architecture
--
--
***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights
reserved. **
--
** **
-- ** This text contains proprietary,
confidential **
-- ** information of Xilinx, Inc. , is distributed
by **
-- ** under license from Xilinx, Inc., and may be
used, **
-- ** copied and/or disclosed only pursuant to the
terms **
-- ** of a valid license agreement with Xilinx,
Inc. **
--
** **
-- ** Unmodified source code is guaranteed to place and
route, **
-- ** function and run at speed according to the
datasheet **
-- ** specification. Source code is provided "as-is", with
no **
-- ** obligation on the part of Xilinx to provide
support. **
--
** **
-- ** Xilinx Hotline support of source code IP shall only
include **
-- ** standard level Xilinx Hotline support, and will only
address **
-- ** issues and questions related to the standard released
Netlist **
-- ** version of the core (and thus indirectly, the original core
source). **
--
** **
-- ** The Xilinx Support Hotline does not have access to
source **
-- ** code and therefore cannot answer specific questions
related **
-- ** to source HDL. The Xilinx Support Hotline will only be
able **
-- ** to confirm the problem in the Netlist version of the
core. **
--
** **
-- ** This copyright and support notice must be retained as
part **
-- ** of this text at all
times. **
--
***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: divide_part.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- divide_part.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2003/02/13 16:13:28 $
--
-- History:
-- goran 2003-02-13 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with
Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity Divide_part is
generic (
Ratio : natural;
First : boolean := true
);
port (
Clk : in std_logic;
Clk_En : in std_logic;
Clk_En_Out : out std_logic
);
end entity Divide_part;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture VHDL_RTL of Divide_part is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000");
-- pragma translate_on
port (
Q : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
Clk : in std_logic;
D : in std_logic
);
end component SRL16E;
component SRLC16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000");
-- pragma translate_on
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
Clk : in std_logic;
D : in std_logic
);
end component SRLC16E;
signal loop_Bit : std_logic;
attribute INIT : string;
constant Nr_Of_SRL16 : natural := 1 +
((Ratio-1)/16);
constant Last_SRL16_Ratio : natural := ((Ratio-1)
mod 16);
constant A : std_logic_vector(3 downto 0) :=
std_logic_vector(to_unsigned(Last_SRL16_Ratio, 4));
signal shifts : std_logic_vector(0 to Nr_Of_SRL16);
signal Emptys : std_logic_vector(0 to Nr_Of_SRL16);
begin -- architecture VHDL_RTL
One_SRL16 : if (Nr_Of_SRL16 = 1) generate
attribute INIT of SRL16E_I : label is "0001";
begin
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => X"0001") -- [bit_vector]
-- pragma translate_on
port map (
CE => Clk_En, -- [in std_logic]
D => loop_Bit, -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => A(0), -- [in std_logic]
A1 => A(1), -- [in std_logic]
A2 => A(2), -- [in std_logic]
A3 => A(3), -- [in std_logic]
Q => loop_Bit); -- [out std_logic]
end generate One_SRL16;
Two_SRL16 : if (Nr_Of_SRL16 = 2) generate
attribute INIT of SRLC16E_1 : label is "0001";
attribute INIT of SRL16E_2 : label is "0000";
begin
-- The first SRLC16E
SRLC16E_1 : SRLC16E
-- pragma translate_off
generic map (
INIT => X"0001") -- [bit_vector]
-- pragma translate_on
port map (
CE => Clk_En, -- [in std_logic]
D => loop_Bit, -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => '1', -- [in std_logic]
A1 => '1', -- [in std_logic]
A2 => '1', -- [in std_logic]
A3 => '1', -- [in std_logic]
Q15 => shifts(1), -- [out std_logic]
Q => Emptys(1)); -- [out std_logic]
SRL16E_2 : SRL16E
-- pragma translate_off
generic map (
INIT => X"0000") -- [bit_vector]
-- pragma translate_on
port map (
CE => Clk_En, -- [in std_logic]
D => shifts(1), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => A(0), -- [in std_logic]
A1 => A(1), -- [in std_logic]
A2 => A(2), -- [in std_logic]
A3 => A(3), -- [in std_logic]
Q => loop_Bit); -- [out std_logic]
end generate Two_SRL16;
More_Than_Two : if (Nr_Of_SRL16 > 2) generate
attribute INIT of SRLC16E_1 : label is "0001";
attribute INIT of SRL16E_n : label is "0000";
begin
-- The first SRLC16E
SRLC16E_1 : SRLC16E
-- pragma translate_off
generic map (
INIT => X"0001") -- [bit_vector]
-- pragma translate_on
port map (
CE => Clk_En, -- [in std_logic]
D => loop_Bit, -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => '1', -- [in std_logic]
A1 => '1', -- [in std_logic]
A2 => '1', -- [in std_logic]
A3 => '1', -- [in std_logic]
Q15 => shifts(1), -- [out std_logic]
Q => Emptys(1)); -- [out std_logic]
The_Rest : for I in 2 to Nr_Of_SRL16-2 generate
attribute INIT of SRLC16E_I : label is "0000";
begin
SRLC16E_I : SRLC16E
-- pragma translate_off
generic map (
INIT => X"0000") -- [bit_vector]
-- pragma translate_on
port map (
CE => Clk_En, -- [in std_logic]
D => shifts(I-1), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => '1', -- [in std_logic]
A1 => '1', -- [in std_logic]
A2 => '1', -- [in std_logic]
A3 => '1', -- [in std_logic]
Q15 => shifts(I), -- [out std_logic]
Q => Emptys(I)); -- [out std_logic]
end generate The_Rest;
-- The last SRL16
SRL16E_n : SRL16E
-- pragma translate_off
generic map (
INIT => X"0000") -- [bit_vector]
-- pragma translate_on
port map (
CE => Clk_En, -- [in std_logic]
D => shifts(Nr_Of_SRL16-2), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => A(0), -- [in std_logic]
A1 => A(1), -- [in std_logic]
A2 => A(2), -- [in std_logic]
A3 => A(3), -- [in std_logic]
Q => loop_Bit); -- [out std_logic]
end generate More_Than_Two;
-----------------------------------------------------------------------------
-- If the SRL16 is the first in a serie then the output is a clean single
-- clock pulse
-----------------------------------------------------------------------------
Is_First : if (First) generate
Clk_En_Out <= loop_Bit;
end generate Is_First;
-----------------------------------------------------------------------------
-- If not the first the output has to be masked so that it produce a
single
-- clock pulse
-----------------------------------------------------------------------------
not_First : if (not First) generate
signal Out1 : std_logic;
begin
Out1_DFF : process (Clk) is
begin -- process Out1_DFF
if Clk'event and Clk = '1' then -- rising clock edge
Out1 <= loop_Bit;
end if;
end process Out1_DFF;
Out2_DFF : process (Clk) is
begin -- process Out2_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Out1 = '1') then
Clk_En_Out <= Clk_En;
end if;
end if;
end process Out2_DFF;
end generate not_First;
end architecture VHDL_RTL;
-------------------------------------------------------------------------------
-- $Id: baudrate.vhd,v 1.2 2003/01/16 22:32:37 tise Exp $
-------------------------------------------------------------------------------
-- baudrate.vhd
-------------------------------------------------------------------------------
--
--
***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights
reserved. **
--
** **
-- ** This text contains proprietary,
confidential **
-- ** information of Xilinx, Inc. , is distributed
by **
-- ** under license from Xilinx, Inc., and may be
used, **
-- ** copied and/or disclosed only pursuant to the
terms **
-- ** of a valid license agreement with Xilinx,
Inc. **
--
** **
-- ** Unmodified source code is guaranteed to place and
route, **
-- ** function and run at speed according to the
datasheet **
-- ** specification. Source code is provided "as-is", with
no **
-- ** obligation on the part of Xilinx to provide
support. **
--
** **
-- ** Xilinx Hotline support of source code IP shall only
include **
-- ** standard level Xilinx Hotline support, and will only
address **
-- ** issues and questions related to the standard released
Netlist **
-- ** version of the core (and thus indirectly, the original core
source). **
--
** **
-- ** The Xilinx Support Hotline does not have access to
source **
-- ** code and therefore cannot answer specific questions
related **
-- ** to source HDL. The Xilinx Support Hotline will only be
able **
-- ** to confirm the problem in the Netlist version of the
core. **
--
** **
-- ** This copyright and support notice must be retained as
part **
-- ** of this text at all
times. **
--
***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: baudrate.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- baudrate.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2003/01/16 22:32:37 $
--
-- History:
-- goran 2001-06-12 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with
Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Baud_Rate is
generic (
C_USE_FIXED : integer := 1; -- Fixed baudrate
C_RATIO : integer := 814; -- The ratio between clk and the
asked
-- baudrate multiplied with 16
C_INACCURACY : integer := 15 -- The maximum inaccuracy of the clk
); -- division in per thousands
port (
Clk : in std_logic;
Div_Factor : in std_logic_vector(0 to 15);
EN_16x_Baud : out std_logic);
end entity Baud_Rate;
library unisim;
use unisim.all;
library opb_uartlite_v2_00_a;
use opb_uartlite_v2_00_a.Divide_Part;
architecture VHDL_RTL of Baud_Rate is
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component Divide_Part is
generic (
Ratio : natural;
First : boolean);
port (
Clk : in std_logic;
Clk_En : in std_logic;
Clk_En_Out : out std_logic);
end component Divide_Part;
-- log2 function returns the number of bits required to encode x choices
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
-----------------------------------------------------------------------------
-- Calculate the number of SRL16s needed for the Ratio R
-----------------------------------------------------------------------------
constant MAX_DIV_FACTOR : natural := 16;
subtype SRL16_DIV_TYPE is natural range 2 to MAX_DIV_FACTOR;
type FACTORS_LIST_TYPE is array (natural range 1 to 15) of
SRL16_DIV_TYPE;
type FACTORS_TYPE is
record
Good_Divide : boolean;
Nr_Of_Factors : natural;
Factor_List : FACTORS_LIST_TYPE;
end record FACTORS_TYPE;
-----------------------------------------------------------------------------
-- Trying to divide R into integer values of values 2-16 until the end
result
-- is between 2-16.
-----------------------------------------------------------------------------
function Get_Factors (R : natural) return FACTORS_TYPE is
variable N : natural := R;
variable Result : FACTORS_TYPE;
variable no : natural := 1;
variable Found : boolean;
begin -- function Get_Factors
if (N < 16) then
Result.FACTOR_LIST(1) := N;
Result.Nr_Of_Factors := 1;
Result.Good_Divide := true;
return Result;
end if;
while N /= 1 loop
Found := false;
for I in 16 downto 2 loop
if ((N mod I = 0)) then -- Found factor
Result.FACTOR_LIST(no) := I;
N := N / I;
no := no + 1;
Found := true;
exit;
end if;
end loop; -- I
if (not(Found)) then
Result.Good_Divide := false;
exit;
end if;
end loop;
if (found) then
Result.Good_Divide := true;
Result.Nr_Of_Factors := no-1;
end if;
return Result;
end function Get_Factors;
-----------------------------------------------------------------------------
-- Trying to find a ratio that is within 1.5% of the asked ratio and
that the
-- ratio can be implemented with SRL16.
-----------------------------------------------------------------------------
function Find_Best_Factors (R : natural) return FACTORS_TYPE is
constant Proc_Diff : natural := R*C_INACCURACY/1000; -- Calculate
the max difference
-- for the maximum inaccuracy
variable Result : FACTORS_TYPE;
begin -- function Find_Best_Factors
Result := Get_Factors(R);
if (Result.Good_Divide) then
return Result;
end if;
for I in 1 to Proc_Diff loop
Result := Get_Factors(R+I);
if (Result.Good_Divide) then
return Result;
end if;
Result := Get_Factors(R-I);
if (Result.Good_Divide) then
return Result;
end if;
end loop; -- I
Result.Good_Divide := false;
return Result;
end function Find_Best_Factors;
constant Divide_Factors : FACTORS_TYPE := Find_Best_Factors(C_RATIO);
signal Clk_En_I : std_logic_vector(0 to
Divide_Factors.Nr_Of_Factors);
signal Count : std_logic_vector(0 to 15);
begin -- architecture VHDL_RTL
Using_Fixed_Baudrate : if (C_USE_FIXED /= 0) generate
-----------------------------------------------------------------------------
-- A clean and good ratio was found that was within the 1.5% limit, so
-- implement the uartlite division using SRL16s
-----------------------------------------------------------------------------
Using_SRL16s : if (Divide_Factors.Good_Divide) generate
Clk_En_I(0) <= '1';
SRL16s : for I in 1 to Divide_Factors.Nr_Of_Factors generate
Divide_I : Divide_Part
generic map (
Ratio => Divide_Factors.FACTOR_LIST(I), -- [natural range 2
to 16]
First => (I = 1)) -- [boolean]
port map (
Clk => Clk, -- [in std_logic]
Clk_En => Clk_En_I(I-1), -- [in std_logic]
Clk_En_Out => Clk_En_I(I)); -- [out std_logic]
end generate SRL16s;
En_16x_Baud <= Clk_En_I(Divide_Factors.Nr_Of_Factors);
end generate Using_SRL16s;
-----------------------------------------------------------------------------
-- Couldn't find a good ratio within the 1.5% limit so implement the
uartlite
-- generation using a standard counter
-----------------------------------------------------------------------------
Using_Counter : if (not Divide_Factors.Good_Divide) generate
constant Nr_Of_Bits : natural :=
log2(C_RATIO-1);
constant New_Value : std_logic_vector(0 to Nr_Of_Bits-1) :=
std_logic_vector(to_unsigned(C_RATIO-1, Nr_Of_Bits));
signal Cnt : std_logic_vector(0 to Nr_Of_Bits-1);
signal New_Cnt : std_logic_vector(0 to Nr_Of_Bits-1);
signal Carry : std_logic_vector(0 to Nr_Of_Bits);
signal Count : std_logic_vector(0 to Nr_Of_Bits-1);
begin
Carry(0) <= '0'; -- Always subracting
All_Bits : for I in 0 to Nr_Of_Bits-1 generate
New_Cnt(I) <= not(Count(I)) when Carry(Nr_Of_Bits) = '0' else
New_Value(I);
MUXCY_L_I1 : MUXCY_L
port map (
DI => '0', -- [in std_logic]
CI => Carry(I), -- [in std_logic]
S => New_Cnt(I), -- [in std_logic]
LO => Carry(I+1)); -- [out std_logic]
XORCY_I1 : XORCY
port map (
LI => New_Cnt(I), -- [in std_logic]
CI => Carry(I), -- [in std_logic]
O => Cnt(I)); -- [out std_logic]
end generate All_Bits;
Counter : process (Clk) is
begin -- process Counter
if Clk'event and Clk = '1' then -- rising clock edge
Count <= Cnt;
end if;
end process Counter;
En_16x_Baud <= Carry(Nr_Of_Bits);
end generate Using_Counter;
end generate Using_Fixed_Baudrate;
Dynamic_Baudrate: if (C_USE_FIXED = 0) generate
Counter : process (Clk) is
begin -- process Counter
if Clk'event and Clk = '1' then -- rising clock edge
if (Count = "0000000000000000") then
Count <= Div_Factor;
EN_16x_Baud <= '1';
else
Count <= std_logic_vector(unsigned(Count) - 1);
EN_16x_Baud <= '0';
end if;
end if;
end process Counter;
end generate Dynamic_Baudrate;
end architecture VHDL_RTL;
Symon wrote:
>Hey Goran,
>How about posting the code direct. Not all of us have news hosts that can
>pass on attachments!
>Ta, Syms.
>
>
>
>
Article: 70419same as RF engineer .. ever seen what a 2 gig processor looks like :-)... infact anything over 500 MHz is RF Simon "Hendra Gunawan" <u1000393@email.sjsu.edu> wrote in message news:cao5ji$7epp0$1@hades.csu.net... > How about digital logic design engineer? What kind of math required other > than basic arithmetic? And don't they need a lot less math than say an RF > engineer? > > Hendra > >Article: 70420
Hi all, I am using Xilinx viretx 2 pro device (1152)package which has 8 MGT's. for each of the MGT there are 9 dedicated pins which are TXP, TXN, RXP, RXN, AVCCAUXTX, AVCCAUXRX, VTTX, VTRX, and GNDA. In my design i am not using any of the MGT's. The data sheet suggests that VTRX is the Input Receive termination supply for the RocketIO multi-gigabit transceiver (1.8V - 2.8V). Since i am not using the MGT's i wanted to know wether i should keep these pins open OR tie it to 2.5 V. Thanks in advance. Rgds, pravArticle: 70421
On 16 Jun 2004 02:06:37 -0700, praveenkn123@yahoo.com (prav) wrote: >Hi all, > >I am using Xilinx viretx 2 pro device (1152)package which has 8 MGT's. >for each of the MGT there are 9 dedicated pins which are TXP, TXN, >RXP, RXN, >AVCCAUXTX, AVCCAUXRX, VTTX, VTRX, and GNDA. > >In my design i am not using any of the MGT's. >The data sheet suggests that VTRX is the Input Receive termination >supply for the RocketIO multi-gigabit transceiver (1.8V - 2.8V). >Since i am not using the MGT's i wanted to know wether i should keep >these pins open OR tie it to 2.5 V. On a recent design, I tied VCCAUXTX, VCCAUXRX, VTRX to +2.5V and left the TxP, TxN, RxP, RxN pins open. The RocketIO™ Transceiver User Guide http://www.xilinx.com/bvdocs/userguides/ug024.pdf doesn't appear to say anything about the VTRX pins when the transceiver is unused. Note that the pinout of the BGA package is such that the VCCAUXTX, VCCAUXRX and VTRX are all in a row. It's easier to tie the VTRX pins to +2.5V than to leave them open. Regards, Allan.Article: 70422
sdatta@altera.com (Subroto Datta) wrote in message news:<ca4d800d.0406151420.270b95f5@posting.google.com>... > Yes, this path is possible to implement in the hardware. Using the > altmult_add Megafunction you can control explicitly which registers > are used in the DSP Block, while the lpm_mult Megafunction only gives > you an option to specify the number of pipeline stages. > > Using the altmult_add MegaWizard, create an altmult_add instantiation > with 1 multiplier, which ensures only the multiplier portion will be > used (the adder portion will not be used). Within this MegaWizard, > you can explicitly specify which registers to use. To achieve what > you want, you should use the input registers and extra ouput register, > but disable the multiplier output register. > > Hope this helps. > > Subroto Datta > Altera Corp. Subroto, Thanks a lot. I'll try this out. It looks like exactly what I wanted. In the meantime I've discovered that with some optimizations turned on, Quartus is aggressively moving the multiplier registers around -- I didn't know it was possible to separate the registers from the multiplier ! Not only that but it's cramming lots of auxiliary registers into the DSP block, even when all 4 (18-bit) multipliers are used. Wow! Regards, -rajeev-Article: 70423
Hello, I just installed Xilinx ISE 6.2i on a Linux box and it is sluggish as anything. Does anyone know why? I am running on a P4 1.7GHz w/ 1GB of RAM. On windows, it is much more zippy. Could it be the gui toolkit that Xilinx is using (it seems like JAVA.......slow as a slug....)? Thanks. SalmanArticle: 70424
Hello, does anyone have an example for a circuit using an AMBA bus on the excalibur epxa1? I built a circuit with the following components: a arm processor, a stripe_pld_master, a user interface ahb slave and a logic block in FPGA. But it does not work. I want to have an example to have a comparison and to see, where the problem in my circuit lies. Thanks! Diandian
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