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Peter Sommerfeld a écrit: > Hi folks, > > Can anyone recommend an SDRAM controller, free or otherwise, with the > following features: > - synthesizable to >100 MHz fmax on Stratix -7 (preferably 133 MHz) > - allows latent read bursts to maximum throughput > - burtsts efficiently (keeps bank rows open where possible) What about this one? http://www.plda.com/pdt_core_mem.htm -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 70176
Hi, I need a hardware implementation of the Xilinx CRC generator for the configuration process. I want to manipulate the configuration date before I download them to the SelectMap interface, but as the CRC checksum changes by manipulating the configuration bistream, I have to calculete the new CRC checksum in hardware and include this into the new configuration stream. In the App 151 and 138 they talk about a parallel implementation, because timing (clock cycles) is critical for me. Any suggestions how to implement the CRC checker or better, is there an existing hardware implentation that I can use? HeikoArticle: 70177
On 8 Jun 2004 00:50:31 -0700, heiko@thecoldies.de (Heiko) wrote:
>Hi,
>I need a hardware implementation of the Xilinx CRC generator for the
>configuration process. I want to manipulate the configuration date
>before I download them to the SelectMap interface, but as the CRC
>checksum changes by manipulating the configuration bistream, I have to
>calculete the new CRC checksum in hardware and include this into the
>new configuration stream. In the App 151 and 138 they talk about a
>parallel implementation, because timing (clock cycles) is critical for
>me.
>
>Any suggestions how to implement the CRC checker or better, is there
>an existing hardware implentation that I can use?
>Heiko
The following website will create Verilog or VHDL for any CRC
polynomial from 1 to 33 bits, and can parallelize the implementation
from 1 (basically serial) to 511 bits.
http://www.easics.be/webtools/crctool
It has a few preset CRC generator polynomials, you need the second
one in the list : "CRC-16 / USB".
Select it, click "set to", select the level of parallelism for the
data bus, for example, 32, click apply, and then generate.
There are lots of ways to screw up CRC: load from the wrong end,
shift in the wrong direction, forget to initialize the CRC register,
reverse the results bits, forget to invert the result at the end,
and many more. Not all CRC standards require all these steps, but
some do. The best procedure is to implement a 1 bit at a time
version, the N bit at a time version, and the C code in XAPP151.
Run some test data through all of them, then fix things until they
all give the same answer. Note that the parallel versions can not
be made to work with data streams that are not an integer multiple
of bits of the width you choose for the parallel version.
If you must do this, then a possible solution is to process as much
as possible in the parallel section, then transfer the result to
the CRC register of a 1 bit at a time CRC generator, and then finish
of the remaining bits there.
Have fun,
Philip
Philip Freidin
Fliptronics
Article: 70178
Hello,
Im' using Quartus 4 and SOPC Builder 4.
I'm preparing a nios design, but i've got a trouble with software build.
The point is that the only way I have to generate the soft is to
regenerate the whole system (both soft and hard).
I obviously tried to use the command line tools, in vain.
I tried to use the c macro offered in the generated modelsim do file ...
but it's still not working ...
Here is the error i have in the SOPC SDK SHELL when try to build
montest.c code :
[SOPC Builder]$ nios-build montest.c
Can't use string ("-1") as a HASH ref while "strict refs" in use at -
line 478.
And attached is the log of the modelsim shell.
If anybody has an idea from where it comes from, please let me know.
Thanks for your attention.
Julien Chevalier
translate knight to french and add a j att voila dot fr
Article: 70179On Tue, 08 Jun 2004 08:55:29 GMT, Philip Freidin <philip@fliptronics.com> wrote: >Note that the parallel versions [of CRCs] can not >be made to work with data streams that are not an integer multiple >of bits of the width you choose for the parallel version. This is not true in general. There's a number of ways of getting wide parallel CRC calculators to work with frames of any length. I call these the "ragged start word" and "ragged end word" problems if the packet does not start or end on a word boundary. Some methods described here: http://groups.google.com/groups?threadm=434d10fb.0302160949.75d1736f%40posting.google.com Regards, Allan.Article: 70180
Talk to your FAE. They have been trained in Virtex-4. Failing that they have access contacts for more information on jitter. Sorry I can't say more but until it is public NDAs apply. John Adair Enterpoint Ltd. - Home of Broaddown2 http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:f5fac0pro7joakuat33uvonetm4to1kv8k@4ax.com... > Hi, > Does anyone know if the (just announced) Virtex-4 FX transceivers will > have jitter characteristics suituable for SONET work at 10Gb/s? > > The current (V2PX) transceivers aren't able to meet the jitter specs, > forcing the use of external SERDES devices. > > There's not much real information on the web page yet. > http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Virtex-4 > > TIA, > Allan.Article: 70181
Peter, Thanks for your answer GaRYArticle: 70182
Julien Chevalier <translate_to_french_the_word_knight_and_add_a_j@voila.fr> writes:
> Here is the error i have in the SOPC SDK SHELL when try to build
> montest.c code :
>
> [SOPC Builder]$ nios-build montest.c
> Can't use string ("-1") as a HASH ref while "strict refs" in use at
I seem to recall that I got this message when I used the wrong perl
installation. You have to make sure that you use the included cygwin
and perl distriutions.
Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Article: 70183Now that the Virtex-4 has been announced: http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Virtex-4 The obvious question is when and how much? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 70184
Petter Gustad <newsmailcomp5@gustad.com> wrote: : Now that the Virtex-4 has been announced: : http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Virtex-4 : The obvious question is when and how much? Probaly, when you install Ise 6.3, you will read in one of those background pictures : "Virtex-4, delivering since June 2004" like you read with Ise 6.2 "Spartan-3, delivering since March 2003" :-( Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 70185
I am able to program and scan Altera devices on my scan chain but when I go to load the Virtex2 I get an IR_Capture failure because the LSB on the Virtex is not being set. I am using a serial prom on that chip so I'm worried that it is trying to load at power up and messing up the JTAG in the chip. Anyone ever seen a problem like this? > > INFO:iMPACT:1206 - Instruction Capture = '0101010101000000010101000101000101010101010000000110101101' > > INFO:iMPACT:1207 - Expected Capture = '0101010101XXXX01XXXXXXXXXXXXXX010101010101XXXXXX01XXXXXX01' > '0101010101XXXX01XXXXXXXXXXXXXX010101010101XXXXXX01XXXXXX01' > > I generated the third line by reading the .bsdl > files for what the INSTRUCTION_CAPTURE value should be. So everything > matches except that the XC2V2000 is not setting the LSB to one. It must be > kept in reset or something... > > attribute INSTRUCTION_CAPTURE of XC2V2000_FG676 : > entity is > -- Bit 5 is 1 when DONE is released (part of startup > sequence) > -- Bit 4 is 1 if house-cleaning is complete > -- Bit 3 is ISC_Enabled > -- Bit 2 is ISC_Done > "XXXX01";Article: 70186
Has anybody actually received updates to their Quartus and Nios toolkits to support Nios II ? GeoffreyArticle: 70187
I was experimenting a coregen generated FFT module. How come the slice utilization jump 6 fold from the synthesis report to map report? XST does not just synthesis the logic into generic logics, it synthesize the logic to target resources, right? What I am saying is that if I change the target device, the # of slice used would change if the architecture of the slice is different between these two devices. So why there is such a big change in the # of slice used (and other resource for that matter) between MAP report and synthesis report. I am definitely a newbie, so please bear with me. Thanks, CharlesArticle: 70188
Hi Nocolas, Dave, Thanks for pointers. I will look into both controllers. > > What about this one? > http://www.plda.com/pdt_core_mem.htmArticle: 70189
Yes I emailed yesterday morning ... waiting on reply. -- Pete > > Why not ask the authors? > > /RogerLArticle: 70190
Hi, "John Retta" <jretta@rtc-inc.com> wrote: > The previously mentioned article was an interesting read. I have always > been a strong > advocate of synchronous design, and this includes the application of resets. > My rule of thumb is use synchronous resets in all areas, unless > exceptional > conditions arise. There are at least two good exceptions : > [1] Block of logic may have a clock which after power-up disappears, example > clock derived from a DDS which might be reset operationally. In order to > restore outputs > to inactive states in absence of clock, asynchronous reset needs to be used. > [2] Sequential logic drives tristate enable control - During powerup or > during > in-circuit test mode, clock may not be present, and multiple drivers causing > contention > can cause device failure. I think you forgot logic that drives external cirquits (which might be true for most designs). Normaly you start your fpga while powerup of the pcb. There exists cirquits that wil be destroyed if the fpga drives its outputs in a state which generates unacceptable currents or voltages on external parts over a longer periode (beside tristate busses). I prefer a asynchronous reset and an internal logic, that will recover out of every failure mode. In some cases it might be clever to use a synchron deassert of the asynchronous reset. bye ThomasArticle: 70191
"Xilinx ... today unveiled details of its Virtex-4 (TM) Platform FPGAs..." Scant details -- sans data sheets, this event is closer to a second wave of ASMBL teaser PR than a product launch. Some interesting tidbits, though. Up to 200 kLUTs, enhanced DSP, PPC APU port, and apparently evolution, not revolution, with respect to CLB architecture (*). All good. EE Times reports 14 devices "in the works" (compare to ~11 V2 products and 10+2 follow-ons). Spread over three family variants, that could mean steeper than historic device capacity steps within some variants. We'll see. http://www.xilinx.com/company/press/kits/v4_arch/v4_finalwhitepaper4.pdf, first paragraph: "Xilinx had already established itself with numerous implementations of FPGA-based RISC processors and processor cores, with the earliest example being Philip Freidin's RISC4005/R16 FPGA processor implementation in 1991." Jan Gray Gray Research LLC ----- (*) Perhaps I read too much into the statements of "Up to 7 input functions/CLB" and "Full support for all Virtex-II Series features".Article: 70192
I wrote "Up to 200 kLUTs", but to be precise, the Xilinx press release states "With up to 200,000 logic cells...". Not the same thing, LUTs and logic cells. Sorry about that. Jan Gray Gray Research LLCArticle: 70193
It is a matter of packing. a slice is counted as used if only one of the two
LUTs is used. It is also used if the slice is used as a route-through. XST
counts LUTs. The placer may also be separating the LUTs from a carry chain or
carry chain from flip-flops due to poor mapping. Look at the design under FPGA
editor (preferably) or under floorplanner to see what it did to the design.
charles wrote:
> I was experimenting a coregen generated FFT module. How come the slice
> utilization jump 6 fold from the synthesis report to map report? XST does
> not just synthesis the logic into generic logics, it synthesize the logic to
> target resources, right? What I am saying is that if I change the target
> device, the # of slice used would change if the architecture of the slice is
> different between these two devices. So why there is such a big change in
> the # of slice used (and other resource for that matter) between MAP report
> and synthesis report.
> I am definitely a newbie, so please bear with me.
>
> Thanks,
> Charles
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 70194John Retta wrote: > My rule of thumb is use synchronous resets in all areas, > unless exceptional conditions arise. > There are at least two good exceptions : (snip of exceptions) (snip) To me, a global asynchronous reset driven from an external pin, or by the FPGA itself, is fine. The user of the system is then responsible for any required timing. (I believe most FPGA will do asynchronous reset on all FF at initialization time.) Otherwise, I would agree that asynchronous reset driven by other parts of the design results in an asynchronous design. -- glenArticle: 70195
David, The DUC is a free IP which can be downloaded from our website. As opposed to other IP, it has been implemented with our System Generator tool and can be downloaded as a source code for System Generator, or a netlist. Please take a look at the following page and let me know if you have any questions. http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DUC Sabine > ------------------------------------------------------------------------ > > > > Subject: Where is my Digital Up Convertor in Logicore ??!! :) > > Date: 6 Jun 2004 19:58:28 -0700 > > From: djb@global.net.mt (David Joseph Bonnici) > > Organization: http://groups.google.com > > Newsgroups: comp.arch.fpga > > > > I have been on the xilinx website and they say that they have included > > the Digital Up Convertor in ISE package. I have opened Coregen but I > > CANNOT FIND IT. Perhaps I am getting cross eyed. I tried a file search > > on the installation path C:\xilinx and there is not even the duc.pdf > > I know that I can build one myself from the other blocks, but I would > > like to use it. (to be less error prone, designs use less slices, less > > code, less time) > > Is there someone that has the same problems that I have? > > > > Apart from that: Can someone explain me what is "Bit convergent > > rounding" with a practical example of numbers? > > > > DavidArticle: 70196
On Tue, 08 Jun 2004 19:37:21 +1000, Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote: >On Tue, 08 Jun 2004 08:55:29 GMT, Philip Freidin ><philip@fliptronics.com> wrote: > >>Note that the parallel versions [of CRCs] can not >>be made to work with data streams that are not an integer multiple >>of bits of the width you choose for the parallel version. > >This is not true in general. There's a number of ways of getting wide >parallel CRC calculators to work with frames of any length. > >I call these the "ragged start word" and "ragged end word" problems if >the packet does not start or end on a word boundary. > >Some methods described here: >http://groups.google.com/groups?threadm=434d10fb.0302160949.75d1736f%40posting.google.com > >Regards, >Allan. Indeed. Although more like clues, rather than methods :-) While my previous article suggested using a 1 bit serial solution to finish of the "ragged end" as you name it, for a packet that is byte oriented, you could process it 32 bits at a time, and then finish off the last 1, 2, or 3 bytes with an 8 bit generator, or if cycle count was really critical, have a generator for 8, 16, and 24 bits that is only used for one cycle at the end of the packet. Thanks for the interesting addition algorithm behavior info, Philip Philip Freidin FliptronicsArticle: 70197
My recent task had me interacting with XST and altering the settings to highest effort to achieve the timing constraint that I had. I eventually had to use the reentrant route feature to finally make the constraint. I would imagine that using some floorplanning might have helped me out, but as I have yet to get into the basics of floorplanning yet I felt to try and just push the tools more. Since I brought it up, do you use floorplanning when doing a desing, and if so, where is the best place to start. Is the idea to get things as close as possible keeping the routing as short as possible, or just to focus on specific areas that might use faster clocks, and require short delays? "John_H" <johnhandwork@mail.com> wrote in message news:Jk0xc.1$eB5.82@news-west.eli.net... > I see you're not pushing density yet. Are you pushing speed? If your needs > are for slow clocks, low complexity, and low density, you shouldn't need > anything more than you have. Other third party tools can provide higher > speed performance through better optimizations that have sensitivity to > which paths are more critical than others. When it was first coming out, > XST (Xilinx Synthesis Technology) was heralded as a nice, technically > accurate compiler that will always have access to the latest silicon > features. Its purpose was not to provide spectacular performance results; > for the points where it does outdo third party tool vendors, kudos! > > I have a design now where I know where my worst delay will be and my coding > style is attempting to coax the critical signal into the last layer of > logic. My expectation is that the 3rd party synthesis will deliver good > results to begin with and only need a little tweaking to get the worst > behaving paths under control. I'd expect much more interaction with XST to > be able to achieve similar results, but this is a guess; I haven't USED the > tool, only listened to their FAEs. > > > "Jason Berringer" <look_at_bottom_of@email.com> wrote in message > news:rVrwc.55767$Hn.1478571@news20.bellglobal.com... > > Hello all, > > > > I'm curious to know the benefits of using third party synthesis tools. For > > example how much better are synthesis tools like Synplicity or Synplify, > etc > > over just using the vendor tools ISE Webpack. Do you only experience some > > significant gains with large designs or does it not really matter. I've > been > > using the Xilins synthesis tools for quite a while and have never had a > > problem. I will be the first to admit that my largest designs have only > > taken up about 60% of a XC2S150 so I'm not dealing with mosterous designs. > > > > Anyn commetns are appreciated. > > > > Jason > > > > jberringer@remove.sympatico.remove.ca > > > > remove the removes to reply to me personally. > > > > > >Article: 70198
Hi Philip, hi Allan, many thanks for your answers, I am sure this will help me. Regards HeikoArticle: 70199
hello, I want to build tcp/ip-Stack as an library file. The stack contains one tcp.hcc-file with the main-function and and some other macros and functions. The second file is a headerfile where all the variables are declared and the macro/functions-prototypes are in it. Its my first time building a library file at all. 1. I think I have to put the main-function in the file which should later include the library file (its not allowed to have a main-function in a library-file, or), is it right??? 2.I did that, I made a new project which includes the tcp.hcl the code of the project is only the tcp-mainfunction from the old tcp.hcc file 3. No there are a lot of errors, some var. are undeclared and some are redifined. can somebody help me,thanks, michael
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