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"Kelvin" <student@nowhere.com> wrote in message news:<40e501ca$1@news.starhub.net.sg>... > Terrible! How may I optimize it in RTL codes? > > assign tmp1 = en ? din_a_abs * din_b_abs : 16'b0; > assign dout = sign ? ~tmp1 + 1'b1 : tmp1; > > Best Regards, > Kelvin Well probably you have a timing constaint that forces tmp1 to be duplicated to meet it, 1 inst has its output made -ve.the other as is. You may have a switch to stop this replication. You could try putting the cond sgn negation in series with one of the 2 inputs or put it on the next pipeline or relax the timing, either way should give 1 mul. regards johnjakson_usa_comArticle: 70951
Just open the precision script (../Mgc_home/bin) and change line 26 from supported=0 to supported=1 :-) I had to do the same to get it to run on RH9. Regards, Hans. www.ht-lab.com "General Schvantzkoph" <schvantzkoph@yahoo.com> wrote in message news:pan.2004.06.27.21.31.40.155311@yahoo.com... > The latest version of Precision is checking for the distribution, is there > an environment variable that I can set to fake Precision into thinking > that it's running on Redhat 8? The older versions of Precision run fine on > Mandrake 10, unfortunately they added a test into Precision 2004a. >Article: 70952
It works fine for me. "Tom Seim" <soar2morrow@yahoo.com> wrote in message news:6c71b322.0407012012.2e2e92e5@posting.google.com... > Is it me, or do the rest of you have major frustratinos using Xilinx's web site? > > Just today they had a broken link TO THEIR OWN SITE!!! > > Believe me, I have talked to Xilinx managers who have admitted as much.Article: 70953
Hi,
I'm having problems getting nios-run -t to function correctly. The
development platform is Quartus 3 sp2, SOPC 3.02 on Linux, Apex board.
I'm using the standard_32 example provided with the Nios kit 3.2. This
builds (SDK and the hardware) without apparent problem, synthesises and
can be downloaded via the jtag interface.
executing nios-run -t results in the peripherals test menu being displayed
but no response to keyboard input occurs, except ^C which occasionally
requires repeating to get the program to quit. Running strace shows
repeated calls to query the keyboard via select(), but only the ^c is
picked up on.
Running minicom permits access to germs: and to the peripheral tests,
albeit with a 'staircase' problem on the output from the peripherals test,
but at least I have 2 way communication which implies that the problem
lies with nios-run.
Running nios-run -p with a download file results in it waiting
indefinitely for the board to respond, both with the factory default and
the jtag downloaded file.
Has anybody had similar problems? A search through the archives didn't
find anything, hence the post.
AFAIUS, I need to use nios-run to reprogram the onboard flash or is there
an alternative.
thanks in advance,
nigelg.
--
Nigel Gunton Office: +44/0 117 32 83167 /"\
CEMS, UWE, Bristol, BS16 1QY. \ /
X
ASCII Ribbon Campaign against HTML email & microsoft attachments / \
Article: 70954Get out of bed on the wrong side this morning Tom? ;-) I've usually found what I'm looking for on the website pretty easily. Cheers, Syms. "Tom Seim" <soar2morrow@yahoo.com> wrote in message news:6c71b322.0407012012.2e2e92e5@posting.google.com... > Is it me, or do the rest of you have major frustratinos using Xilinx's web site? > > Just today they had a broken link TO THEIR OWN SITE!!! > > Believe me, I have talked to Xilinx managers who have admitted as much.Article: 70955
In article <73n9e0dcp1d7dg4smj3d088g926ogv3bne@4ax.com>, Bob Perlman <bobsrefusebin@hotmail.com> wrote: >On Wed, 30 Jun 2004 16:53:28 +0100, "Leon Heller" ><leon_heller@hotmail.com> wrote: > >>Xilinx has a Spartan-3 kit selling for $99, via their web site. Price from >>Insight (UK) will be 70 GBP, but they don't know when they will be in stock. >> >>Leon > >I ordered one of these yesterday, received it today. All in all, it's >a nice little testing platform. > I'm wondering if you (or anyone else) might have tried the software that comes with the board under Win98? I know Win98 isn't an advertised supported platform, but sometimes that's just because the company doesn't want to have more platforms to test on. The software that comes with the board won't work with Wine under Linux apparently because Xilinx opted to use the dreaded Jungo parallel port driver (why they want to have to pay a royalty to Jungo, I don't know). This is likely the reason they won't have Linux support for this board anytime soon.... on the otherhand this could also mean it won't work under Win98. I run Linux and OSX and and thus have no use for Windows anymore, but I do have an old copy of Win98 laying around somewhere ;-) PhilArticle: 70956
Hi Richard,
Try the attached...
Thanks,
Mark
Richard Sloan wrote:
> Why does code that someone wrote and used on a Lattice part, not compile
> right with Xilinx webpack tools, various parts of the code it does not like.
>
> Is ABEL a standard? Seems the answer is already no.
>
> Can anyone help make the code Xilinx ready? Its not a lot of code 40 lines
> and most of its look fairly simple.
>
> I will attach it for you to see.
>
> Thanks!
>
>
==================================================================== filename="pci_pio2.abl"
MODULE PCI_PIO2
TITLE 'PCI PIO with only one chip of CPLD';
" CLK, RST# ____________________
" -------------->| |
" FRAME#, IRDY# | | XOUT[31:0]
" -------------->| |============>
" DEVSEL#, TRDY# | |
" <--------------| CPLD |
" C/BE[3:0]# | | XIN[31:0]
" ==============>| |<============
" AD[31:0] | |
" <=============>| |
" ~~~~~~~~~~~~~~~~~~~~
" This design can be fitted to ispLSI2128.
" PCI BUS
CLK, !RES pin;
!FRAME, !IRDY pin;
!DEVSEL, !TRDY pin istype 'reg,pos';
CB0..CB3 pin;
AD0..AD31 pin istype 'reg_l';
" External I/O ports
XOUT0..XOUT7 pin istype 'reg_g';
XIN0..XIN7 pin;
" Intrenal state counter
S0..S2 node istype 'reg';
" Constants and Symbols
"DEVADDR = ^b00000000000000001111001100000000;
" Device address
SC = [S2..S0];
CMD_IOR = ([FRAME,IRDY, [CB3..CB0], [AD31..AD0].pin] == [1,0, 0,0,1,0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0,1,1,0,0,0,0,0,0,0,0]);
CMD_IOW = ([FRAME,IRDY, [CB3..CB0], [AD31..AD0].pin] == [1,0, 0,0,1,1, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0,1,1,0,0,0,0,0,0,0,0]);
BUS_IDLE = ([FRAME,IRDY ] == [0,0 ]);
BUS_XFER = ([ IRDY,TRDY.pin] == [ 1,1]);
LAST_XFER = ([FRAME,IRDY,TRDY.pin] == [0,1,1]);
EQUATIONS
[DEVSEL, TRDY, SC, XOUT0..XOUT7].clk = CLK;
[AD7..AD0].d = [XIN7..XIN0];
[XOUT7..XOUT0].d = [AD7..AD0].pin;
STATE_DIAGRAM SC;
State 0:
if RES then 0;
else if BUS_IDLE then 4;
else 0;
State 4:
if RES then 0;
else if CMD_IOW then 2 with DEVSEL := 1; TRDY := 1;
else if CMD_IOR then 5;
else if BUS_IDLE then 4;
else 0;
State 2:
DEVSEL.oe = 1; TRDY.oe = 1;
[XOUT7..XOUT0].ce = BUS_XFER & !CB0;
" [XOUT15..XOUT8].ce = BUS_XFER & !CB1;
" [XOUT23..XOUT16].ce = BUS_XFER & !CB2;
" [XOUT31..XOUT24].ce = BUS_XFER & !CB3;
if RES then 0;
else if LAST_XFER then 3;
else 2 with DEVSEL := 1; TRDY := 1;
State 3:
DEVSEL.oe = 1; TRDY.oe = 1;
if RES then 0;
else if CMD_IOW then 2 with DEVSEL := 1; TRDY := 1;
else if CMD_IOR then 5;
else 4;
State 5:
if RES then 0;
else 6 with DEVSEL := 1; TRDY := 1;
State 6:
DEVSEL.oe = 1; TRDY.oe = 1; [AD7..AD0].oe = 1; [AD7..AD0].le = 1;
if RES then 0;
else if LAST_XFER then 7;
else 6 with DEVSEL := 1; TRDY := 1;
State 7:
DEVSEL.oe = 1; TRDY.oe = 1;
if RES then 0;
else 4;
State 1:
goto 0;
END
Article: 70957On 2 Jul 2004 16:44:56 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: >In article <73n9e0dcp1d7dg4smj3d088g926ogv3bne@4ax.com>, >Bob Perlman <bobsrefusebin@hotmail.com> wrote: >>On Wed, 30 Jun 2004 16:53:28 +0100, "Leon Heller" >><leon_heller@hotmail.com> wrote: >> >>>Xilinx has a Spartan-3 kit selling for $99, via their web site. Price from >>>Insight (UK) will be 70 GBP, but they don't know when they will be in stock. >>> >>>Leon >> >>I ordered one of these yesterday, received it today. All in all, it's >>a nice little testing platform. >> > >I'm wondering if you (or anyone else) might have tried the software that >comes with the board under Win98? I know Win98 isn't an advertised >supported platform, but sometimes that's just because the company doesn't >want to have more platforms to test on. I couldn't say. I'm running Windows 2000. Bob Perlman Cambrian Design WorksArticle: 70958
I am just wandering if any of you have take a look at the Lattice FPGAs. I do like the DSP functions. is out there any serious comparation against SpartanIII and Cyclone? regards, paulArticle: 70959
On 2 Jul 2004 16:44:56 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: >I'm wondering if you (or anyone else) might have tried the software that >comes with the board under Win98? I know Win98 isn't an advertised >supported platform, but sometimes that's just because the company doesn't >want to have more platforms to test on. The thread prompted me to drag out an old Spartan II dev kit that I never got around to playing...er...working with. Download the latest Webpack ISE from the Xilink site (6.2.03i, IIRC) and tried an install on the home Win98SE box. It seemed to install OK *except* that it knocked out the USB ports I was running on a 2.0 add-in card. A quick pass through some of the examples did seem to function, although I didn't try to actually load any of them. It also does not register itself with the Win98 uninstall list (at least, it didn't show up on my box's Add/Remove applette). If/when I get serious about it (been mostly using Cypress lately) I'll probably install it on an XP notebook and forgo the '98 issues... YMMV and it doesn't cost anything (except time) to download the app and try it. They DO have Linux (Redhat) releases, as well. Trying them out is on my One Of These Days list... -- Rich Webb Norfolk, VAArticle: 70960
In fact, the website just helped me out big time. I use Data2mem. I used it today, and it kept crashing with no proper error message. A little search on the Xilinx website and I found out very quickly that Data2mem goes haywire if you have bitstream compression turned on. (I turned it on the other day during that bitstream compression thread.) Problem solved. So, website pretty good, Data2mem software shite. cheers, Syms. "Symon" <symon_brewer@hotmail.com> wrote in message news:2klgdgF3tf7nU1@uni-berlin.de... > Get out of bed on the wrong side this morning Tom? ;-) I've usually found > what I'm looking for on the website pretty easily. > Cheers, Syms. > "Tom Seim" <soar2morrow@yahoo.com> wrote in message > news:6c71b322.0407012012.2e2e92e5@posting.google.com... > > Is it me, or do the rest of you have major frustratinos using Xilinx's web > site? > > > > Just today they had a broken link TO THEIR OWN SITE!!! > > > > Believe me, I have talked to Xilinx managers who have admitted as much. > >Article: 70961
salman sheikh <sheikh@pop500.gsfc.nasa.gov> wrote in message news:<capfj5$fa$1@skates.gsfc.nasa.gov>... > Hello, > > I just installed Xilinx ISE 6.2i on a Linux box and it is sluggish as > anything. Does anyone know why? I am running on a P4 1.7GHz w/ 1GB of > RAM. On windows, it is much more zippy. Could it be the gui toolkit > that Xilinx is using (it seems like JAVA.......slow as a slug....)? > > Thanks. > > > Salman Greetings, I am currently attempting to install Xilinx ISE 6.2i on a PC running SuSE Linux 9.1 Pro, and would appreciate any hints or instructions that you might share. I am not getting very far on my own. According to the installation instructions, I load the CD and run the setup script (as root) as shown below: pc-vhdl5:/media/dvdrecorder # ./setup The setup script fails after getting to the point of running xilsetup. The xilsetup error message is: /media/dvdrecorder/xilsetup: relocation error: /media/dvdrecorder/bin/lin/libwinsock44.so: symbol h_errno, version GLIBC_2.0 not defined in file libc.so.6 with link time reference ************ setup done! *************** I have confirmed that I do have libc.so.6 in the /lib directory (also in /lib/i686 and /lib/tls). However, I cannot verify if my libc.so.6 has a symbol h_errno exported. I am running glibc version 2.3.3-97, installed from the SuSE installation media, and with all current patches applied. Any help that you could provide would be appreciated. (I understand that Xilinx doesn't claim to support SuSE for ISE, so haven't called their support yet. Perhaps after the holiday weekend.) Thanks. Victor Atkinson Syracuse, NYArticle: 70962
I've had this exact problem. Here's how I solved it. I'm using version 6.2 of the Xilinx ISE and EDK. Make sure you are downloading the bootloop application to the PowerPC target during development. When you download a user application that enables interrupts and then try and connect to the PowerPC with XMD the PowerPC may have already wedged itself (especially if your code is incorrect). Once I initialized the target with a bootloop to execute and then later used XMD to download my interrupt supported code did the error go away. Zach Pfeffer http://ece.colorado.edu/~pfefferzArticle: 70963
In article <s0abe0t818200pi6qmjqg5g07gar325knh@4ax.com>, Rich Webb <bbew.ar@mapson.nozirev.ten> wrote: >On 2 Jul 2004 16:44:56 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: > >>I'm wondering if you (or anyone else) might have tried the software that >>comes with the board under Win98? I know Win98 isn't an advertised >>supported platform, but sometimes that's just because the company doesn't >>want to have more platforms to test on. > >The thread prompted me to drag out an old Spartan II dev kit that I >never got around to playing...er...working with. Download the latest >Webpack ISE from the Xilink site (6.2.03i, IIRC) and tried an install on >the home Win98SE box. > >It seemed to install OK *except* that it knocked out the USB ports I was >running on a 2.0 add-in card. A quick pass through some of the examples >did seem to function, although I didn't try to actually load any of >them. Were you able to use Impact to program the device? >It also does not register itself with the Win98 uninstall list (at >least, it didn't show up on my box's Add/Remove applette). If/when I get >serious about it (been mostly using Cypress lately) I'll probably >install it on an XP notebook and forgo the '98 issues... > >YMMV and it doesn't cost anything (except time) to download the app and >try it. Well, it would cost me $99 for the board to try it out with. > >They DO have Linux (Redhat) releases, as well. Trying them out is on my >One Of These Days list... But it didn't look like they had a Linux version for free download. Did I miss something? PhilArticle: 70964
Victor Atkinson wrote: > Greetings, > > I am currently attempting to install Xilinx ISE 6.2i on a PC running > SuSE Linux 9.1 Pro, and would appreciate any hints or instructions > that you might share. I am not getting very far on my own. According > to the installation instructions, I load the CD and run the setup > script (as root) as shown below: > > pc-vhdl5:/media/dvdrecorder # ./setup > > The setup script fails after getting to the point of running xilsetup. > The xilsetup error message is: > > /media/dvdrecorder/xilsetup: relocation error: > /media/dvdrecorder/bin/lin/libwinsock44.so: symbol h_errno, version > GLIBC_2.0 not defined in file libc.so.6 with link time reference > > ************ setup done! *************** Try setting the environment variable LD_ASSUME_KERNEL=2.4.1. This works for later versions of Red Hat but have not tried it on Suse. This is needed for the installer and the applications in order to work with the newer. Report back whether that does the trick or not. -- BrianArticle: 70965
As mentioned, you need your simulator set to ps resolution. Anything coarser can make the model not operate properly. Newer versions of the model warn against this but older ones did not. Also, if you reset the DCM, you must hold the reset for at least 3 full clock cycles. This is a hardware requirement and newer versions of the model again warn you of this. Also check to see if LOCK has gone high. It can take several ns before the DCM LOCKs and before that time, some runt pulses can be seen but after you have achieved LOCK, the DCM is supposed to be operating properly. Also, ensure you have all of the attributes properly set for the DCM as they have an obvious effect on the operation of the model. -- Brian jakab tanko wrote: > Do you have your modelsim resolution set to ps? > "wolfgang" <wolfgang.hofmann@arcs.ac.at> wrote in message > news:cc14ut$on9$1@newsreader1.utanet.at... > >>hey guys! >> >>i trie to simulate a dcm design with modelsim, but the dcm doesn't start. > > i > >>tried to reset the dcm after applying clkin, it seems, that the dcm is >>working, but clkfx is only a amount of spikes instead of a 50:50 clock but >>at the right frequency. clkin is a 60%:40% clock with 33 MHz. >> >>anyone out there with the same problem? >> >>thx >> >>wolfgang >> >> > > >Article: 70966
Tim wrote:
> Kelvin wrote:
>
>>I am compiling a partial design with XST. I can only use 24
>>multipliers in my portion of a V2-6000 chip...
>>However, the RTL has 35 multipliers...
>>Now I need to compile the other 11 multipliers with LUT, but I don't
>>want to modify the RTL codes...
>>How may I handle this situation?
>>
>>"-mult_style LUT" makes all multipliers with LUT...AUTO and BLOCK
>>makes all multipliers with
>>block multiplers...sigh...
>
>
> Tell the synth that you are compiling for a smaller chip?
>
>
Looks to me that MULT_STYLE is an attribute as well as a synthesis
option meaning you can either use it globally as it sounds you may have
done or attach it on certain modules or certain signals to specify how
to implement individual multipliers in your code. As a quick test, I
wrote the following code and got one multiplier built from LUTs and the
other using the MULT18X18S block:
`timescale 1ns/1ps
module mult_style_test (A, B, C, CLK, X, Y, Z);
input [10:0] A;
input [10:0] B;
output [21:0] C;
input CLK;
input [10:0] X;
input [10:0] Y;
output [21:0] Z;
reg [21:0] C; // synthesis attribute mult_style of C is lut;
reg [21:0] Z; // synthesis attribute mult_style of Z is block;
always @(posedge CLK)
Z <= X * Y;
always @(posedge CLK)
C <= A * B;
endmodule
-- Brian
Article: 70967Actually.. I believe they charge you a license fee if you move sites.. for their time and effort of course "mx" <mx@mx.com> wrote in message news:0V4Fc.84714$s25.47872@newssvr29.news.prodigy.com... > Rene Tschaggelar wrote: > > The whole is solved by a notebook being the work machine at > > the expense of reduced performance. > > UMMM *NO* the original-poster mentioned somewhere in his rant that > the license terms of Mentor, Cadence, and Synopsys > are *tied* to a physical site. Actually the software license is bound > to 3 specific items: > > a) authorized hardware (license node/server) > <AND> > b) physical site (company location, with defined 'distance radius') > <AND> > c) the party/persons/company named on the purchase-order > > That's *AND* (not OR.) Change any 1 of the above, and you have to > contact the vendor to renew/re-validate your license. (This doesn't > automatically mean you have to *repurchase* the software...) > > (b) Buying a laptop, taking it on the road, and using it to run the > EDA sofware falls under 'running the software outside of the > physical site.' All you've done with your laptop, is place > both the license-server and execution-machine in the same > machine (your laptop), instead of just taking the execution-machine > > The physical-site limitation is so restrictive, that technically > speaking, if a customer merely relocates its office more than a > few miles, their software-liense is invalidated. Obvioualy, > no EDA-vendor requires the customer to repurchase the software. They > merely update the license contract with the customer's new (street) > address. > > (c) If the customer is acquired (purchased) by another company, the > EDA-software is non-transferrable. Thankfully within industry, the > standard practice is for the vendor to permit the ownership transfer, as > long as the new owner continues to pay the maintenance/support contract > obligations. This is cheaper for the new owner, because they don't > have to 're-purchase' the licenses (large one-time non-recurring > expense), rather merely pay the quarterly/yearly support-fee (smaller > recurring expense.) >Article: 70968
On 2 Jul 2004 20:22:40 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: >But it didn't look like they had a Linux version for free download. Did I >miss something? As others have noted, the Xilinx site is not as transparent as it could possibly be. There's this note on the WebPack ISE main download page: "Please note - For the 6.2 release the only supported platforms are Windows XP and Windows 2000 with Service Pack 2 or greater." But if one enters via the support tab and look for updates one would find: "Installation instructions for Linux Users 1. Download "6_2_03i_lin.tar.gz" from: http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp 2. Untar the downloaded file into an empty "staging" directory." So only Windows is supported but there is a Linux update that's the same generation as the latest 6.2 Windows update. And there doesn't seem to be any base 6.2 system for Linux to which the service pack can be applied. Makes perfect sense to me... arrggggg -- Rich Webb Norfolk, VAArticle: 70969
Hi, all
Here are two processes: One is temporary buffer to acquire transient /
real-time input data; the other is another buffer to store every 11 samples;
when 11 samples are filled in ChipBuffer_temp, BufferReady is asserted in
the first process.
My problem is : expcept the clock signal ChEst_Clk1x, the BufferReady is
also treated as Global Clock in Xilinx Constraints Editer, which is not
desired. To my understanding, the signal with rising or falling event will
be regarded as Clock...., but here I don't know why BufferReady is put in
the Global list , and how can I avoid this ?
Many thanks.
ChipInput: process(ChEst_Reset,ChEst_Clk1x)
begin
if ChEst_Reset = '1' then
ChipBuffer_temp <= (others => (others => '0'));
ChipCount <= 0;
BufferReady <= '0';
elsif ChEst_Clk1x'event and ChEst_Clk1x = '1' then
if ChEst_FEPhCtrl = "01"
-- BitSync is acquired
ChipBuffer_temp(ChipCount) <= ChEst_ChipIn_I;
if ChipCount < 10 then
ChipCount <= ChipCount + 1;
BufferReady <= '0';
else
ChipCount <= 0;
BufferReady <= '1';
end if;
end if;
end if;
end process;
DataAcquistion: process(ChEst_Reset,ChEst_Clk1x)
begin
if ChEst_Reset = '1' then
ChipBuffer_I <= (others => (others => '0'));
BitCount <= 0;
elsif ChEst_Clk1x'event and ChEst_Clk1x = '1' then
if BufferReady = '1' and ChEstDone_temp = '0' then
ChipBuffer_I <= ChipBuffer_temp ;
BitCount <= BitCount + 1;
end if;
end if;
end process;
regards,
freedragon
Article: 70970
Could anyone explain the meaning of
out0 <= (others => '0');
in the following VHDL code
if reset = '1' then
out0 <= (others => '0');
out1 <= (others => '0');
else
out0 <= in0;
out1 <= in1;
end if;
Thanks,
jay
Article: 70971Yes, it puts all the signal of out0 to '0', whatever is the width of out0 jaypt@hotmail.com wrote: > Could anyone explain the meaning of > > out0 <= (others => '0'); > > in the following VHDL code > > if reset = '1' then > out0 <= (others => '0'); > out1 <= (others => '0'); > else > out0 <= in0; > out1 <= in1; > end if; > > Thanks, > > jayArticle: 70972
It is possible that our University Access Program(UAP) may be able to help depending on your timescales. We have only just announced this for UK and Europe and North America is a few months away it's official launch and support. But if you are interested have a look here http://www.enterpoint.co.uk/news.html . John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Edmond Cote" <edmond_cote@yahoo.ca> wrote in message news:40e60e46$1_2@aeinews.... > > Hi, > > I currently have access to a large number of FPGA prototyping boards through > my University. Unfortunately these boards are quite simple, wire-wrapping > would need to be used to prototype memory or other peripherals. While > ordinarily this wouldn't pose too much of a problem for me, I require a > rather large amount of RAM (of the order of ~4Mbytes) for this project I > will be working on. > > Looking through electronic catalogues, I quickly realized that for one it is > nearly impossible to find DRAM IC's in DIP packages (and that even if I > could find them I would need a hella-lot of those 64Kb chips). The DRAM I > could find is obviously only availible in surface mount type packaging. > Ideally I'd love to get a custom PCB developped and get someone who could > solder to work, but in my case I don't think it is an option as I don't have > the time/money/experience/talent? to do so. > > So basically does anyone have any suggestions?, do any vendors have a SDRAM > protoboard (something like a couple MB of SDRAM on a board with prototyping > headers)? how about using DIMMs instead of individual ICs?. > > As a last resort, I might need to purchase an FPGA board from Memec, Xess, > but personally I'd much rather work with a 1M+ Virtex devices availible from > school then to have a fund such a board myself, which would be of much > lesser quality. Does anyone have any other vendors to suggest, my > requirements are having at least 2Mb of RAM and under 300$, and well at > least 100k gates. > > Thanks in advance for your help and suggestions! > > Ed. > > >Article: 70973
Have a look at the differences between fabric clocks, sometimes called asynchronous (but they are not), and global clocks. You usually get a timing shift between these. Alternatively consider negative edge clocks or if you are using Coolrunner2 the clock doubling features. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "rat" <rattt@col.edu.cn> wrote in message news:cbnvnr$2od0$1@mail.cn99.com... > Hi,friends, > To meet the Tsu requirement in my design, I think I should try to add some > clock delay to the input register, how can I do that in CPLD? (not FPGA, > without PLL,DLL) > > Thanks! > >Article: 70974
We have some products a bit like this appearing shortly. If you want to let us know your requirements and quantities contact us through one the emails listed on our website and we can discuss it further offline. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Daragoth" <daragoth@kuririnmail.com> wrote in message news:317379a8.0406302118.32829ee1@posting.google.com... > Hi, I have just began working with FPGA devices and have been trying > to apply them in real-world situations. For my first project I need a > very small, relatively inexpensive "bare-bones" type FPGA board. But > I have been having difficulty finding one. I just need one with the > following features (please tell me if I'm missing anything vital): > > -FPGA device with at least 15,000 usable gates (more would be > preferable). I only need a small number of user IOs, so that > shouldn't be an issue at all. The device doesn't need to be very fast > either, as it will be running only at around 4 MHz. > -clock with only around 4 MHz frequency range... higher isn't a > problem however. > -in-circuit reprogrammable non-volatile memory device for storing the > FPGA's configuration data. > -The most important thing is that it all fits within a 40 mm x 30 mm x > 10 mm volume or less. > > More features than this obviously isn't a problem, provided it doesn't > make the board larger than the specified volume. Do boards like this > exist for purchase, or will I have to build it myself? I am > inexperienced in the area of designing PCBs so I would prefer to buy > it already made. Is it even possible to build this device in such a > small volume? Thanks for your help. > > > Sincerely, > Darien A. Gothia
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