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Thanks Peter, I was thinking,the behaviour was: - on the clock_write rising edge : I setup Address, data, Write Enable and ENable, as setup time is not valid, BlockRam doesn't take them into account - on the next clock_write rising edge, I setup the new value, and the BlockRam gets the previous value (line above), and set the memory cell - and so on.. It works fine in behavioral not in post place and route, it seems, that some part of the value changed at the rising edge are taken from the "before rising edge" values, while others are taken from the "after rising edge" values, in post place and route. To do what you told me "at least a set-up time before", I changed my block Ram to react on FallingEdge, while my logical set all the values at the RisingEdge.... But I don't know if it's the "good way"... I didn't succeed to find any trivial example about the use of DualPort BlockRam... if anyone has one, I would love to get it. Many thanks, Arnaud "Peter Alfke" <peter@xilinx.com> a écrit dans le message de news:BD01EB55.71BA%peter@xilinx.com... > Remember, all BlockRAM operations are synchronous, activated by the clock > edge (your choice of clock polarity). > That means all inputs must be there at least a set-up time before that clock > edge. > "All" means: Address, Data, Write Enable, and ENable. > > Peter Alfke, Xilinx Applications > > > From: "Arnaud" <arnaud@trisky.com> > > Organization: Guest of ProXad - France > > Newsgroups: comp.arch.fpga,comp.lang.vhdl > > Date: Fri, 25 Jun 2004 22:11:03 +0200 > > Subject: Using a BlockRam in an async FIFO for bus width conversion ? > > > > Hi all, > > First of all, I'm a newbie in FPGA, so sorry if my questions are not very > > smart... :-) > > In a larger design, I try to use a Xilinx BlockRam for a data width > > conversion between 2 clocks domains. > > I look through the different Xilinx example (xapp131, xapp258, ..). As my > > needs was much more simpler I try to make mine (mostly to understand). > > > > During behavioral or post-translate simulation everything is ok. But during > > Post-Place & Route Simulation. It doesn't work. > > I try 2 write 2 32bits words from one side and to get on the other side a > > 64bits word. > > In my test bench, I write > > 1st - 0x00000000 and 0x00000001 > > and the read side I get 0x0000000100000000 > > 2nd - 0x00000002 and 0x00000003 > > and the read side I get 0x0000000300000002 > > and so on. > > > > BUT in place and route simulation I have > > In my test bench, I write > > 1st - 0x00000000 and 0x00000001 > > and the read side I get 0x0000000000000000 > > 2nd - 0x00000002 and 0x00000003 > > and the read side I get 0x0000000200000001 > > 2nd - 0x00000004 and 0x00000005 > > and the read side I get 0x0000000400000003 > > and so on. > > > > > > Basically, I always miss the first value, as It is not taken into account, > > and the "word" are reordered (so with the wrong pair association). > > > > I saw on the newsgroups, that maybe I have to set the WriteEnable _before_ > > the rising edge, but I don't understand how and why if it's the case ? > > > > I have isolated my problem in the two following file (testbench and > > "converter") > > > > Thanks a lot. > > > > Arnaud > > > > > > > > Converter > > -------------------------------------------------------------------------- -- > > ---------------------------- > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.STD_LOGIC_ARITH.ALL; > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > > -- Uncomment the following lines to use the declarations that are > > -- provided for instantiating Xilinx primitive components. > > library UNISIM; > > use UNISIM.VComponents.all; > > > > entity test_fifo is > > Port ( clk_wr_in : in std_logic; > > clk_rd_in : in std_logic; > > bus_in : in std_logic_vector(31 downto 0); > > bus_out : out std_logic_vector(63 downto 0); > > wr : in std_logic; > > rd : in std_logic; > > sr : in std_logic); > > end test_fifo; > > > > architecture Behavioral of test_fifo is > > > > component bram_w32_r64 > > port ( > > addra: IN std_logic_VECTOR(4 downto 0); > > addrb: IN std_logic_VECTOR(3 downto 0); > > clka: IN std_logic; > > clkb: IN std_logic; > > dina: IN std_logic_VECTOR(31 downto 0); > > doutb: OUT std_logic_VECTOR(63 downto 0); > > ena: IN std_logic; > > enb: IN std_logic; > > wea: IN std_logic); > > end component; > > > > > > signal addra: std_logic_VECTOR(4 downto 0); > > signal addrb: std_logic_VECTOR(3 downto 0); > > > > > > > > signal clk_rd: std_logic; > > signal clk_wr: std_logic; > > > > signal rst : std_logic; > > > > begin > > > > > > gclk1: BUFGP port map (I => clk_rd_in, O => clk_rd); > > gclk2: BUFGP port map (I => clk_wr_in, O => clk_wr); > > > > rst <= not sr; > > > > bram : bram_w32_r64 > > port map ( > > addra => addra, > > addrb => addrb, > > clka => clk_wr, > > clkb => clk_rd, > > dina => bus_in, > > doutb => bus_out, > > ena => wr, > > enb => rst, > > wea => '1'); > > > > > > writer: process(sr, clk_wr) > > begin > > if ( sr = '1' ) then > > > > addra <= (others => '0'); > > > > elsif (rising_edge(clk_wr)) then > > > > if ( wr = '1' ) then > > addra <= addra + 1 ; > > end if; > > > > end if; > > > > end process writer; > > > > > > > > reader: process(sr, clk_rd) > > begin > > if ( sr = '1' ) then > > > > addrb <= (others => '0'); > > > > elsif (rising_edge(clk_rd)) then > > if (rd = '1') then > > addrb <= addrb + 1 ; > > end if; > > > > end if; > > > > end process reader; > > > > end Behavioral; > > > > > > TEST_BENCH > > -------------------------------------------------------------------------- -- > > ---------------------------- > > LIBRARY ieee; > > USE ieee.std_logic_1164.ALL; > > USE ieee.numeric_std.ALL; > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > > > > ENTITY test_fifo_tb IS > > END test_fifo_tb; > > > > ARCHITECTURE behavior OF test_fifo_tb IS > > > > COMPONENT test_fifo > > PORT( > > clk_wr_in : IN std_logic; > > clk_rd_in : IN std_logic; > > bus_in : IN std_logic_vector(31 downto 0); > > bus_out : out std_logic_vector(63 downto 0); > > wr : IN std_logic; > > rd : IN std_logic; > > sr : IN std_logic > > ); > > END COMPONENT; > > > > SIGNAL clk_wr : std_logic := '0'; > > SIGNAL clk_rd : std_logic := '0'; > > SIGNAL bus_in : std_logic_vector(31 downto 0):= (others => '0'); > > SIGNAL bus_out : std_logic_vector(63 downto 0):= (others => '0'); > > SIGNAL wr : std_logic :='0'; > > SIGNAL rd : std_logic := '0'; > > SIGNAL sr : std_logic := '1'; > > > > BEGIN > > > > uut: test_fifo PORT MAP( > > clk_wr_in => clk_wr, > > clk_rd_in => clk_rd, > > bus_in => bus_in, > > bus_out => bus_out, > > wr => wr, > > rd => rd, > > sr => sr > > ); > > > > > > -- *** Test Bench - User Defined Section *** > > > > clk_wr <= not clk_wr after 30 ns / 2; > > clk_rd <= not clk_rd after 15 ns / 2; > > sr <= transport '0' after 120 ns; > > > > tb : PROCESS > > BEGIN > > wait; -- will wait forever > > END PROCESS; > > -- *** End Test Bench - User Defined Section *** > > > > writer: process( clk_wr, sr) > > begin > > > > if ( sr ='1' ) then > > > > bus_in <= (others => '1'); > > > > elsif (rising_edge(clk_wr)) then > > > > if ( bus_out /= 8 ) then > > rd <= '0'; > > wr <= '1'; > > bus_in <= bus_in + 1; > > else > > wr <= '0'; > > rd <= '1'; > > end if; > > > > end if; > > > > end process writer; > > END; > > > > > > > > >Article: 70751
what is the fanout of the IOpins in Virtex2 to devices thanks and regards vivekArticle: 70752
>what is the fanout of the IOpins in Virtex2 to devices The details are in the data sheet. It depends upon which IO standard you are using. I haven't seen the term "fanout" in data sheets for a long time. It doesn't really make much sense with modern logic. CMOS has almost 0 load current so you can drive hundreds of loads if you don't care about speed. The data sheet will give you the switching times for a specified load capacitance. If you have more capacitance it takes longer. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 70753
Jim Granville <no.spam@designtools.co.nz> schreef in berichtnieuws RTHCc.4326$NA1.419961@news02.tsnz.net... > Jim wrote: > > > Hi all, > > > > i need to implement a (D) PLL in a CPLD. > > > > Purpose is to multiply a frequency of 32KHz to 4,096KHz. > > On board PLL's don't work since the freq. is very low > > > > How do i start? > > DPLLs ( digital phase locked loops ) have phase jitter, so first > step is to decide how much phase jitter you can tolerate @ 4MHz. > To keep jitter reasonable, DPLLs need a time granularity well > above the reqired Freq out, so you need a faster clock. > You may decide an Analog PLL like a HC4046, with the divide in CPLD > gives better performance. > -jg > Thanks Jim, but your suggestion is how it's done right now, the counter resides in the CPLD. my goal was/is to get rid of the 4046, and some r/c's. since we're using a CPLD, why not create an 'all in one'approach? Regards, JimArticle: 70754
I guess this evaluation board is pretty new, but I was wondering what experiences people are having with this board. It seems like one of the few boards that have general purpose expansion (Card Bus and PCI) as well as supports the multiprocessor varient of the Xilinx Virtex II Pro family (v30). That coupled with Linux and Vxworks seems to make the board pretty interesting. However, I haven't seen much in the way of net traffic on it, and was wondering if that was because it was so new or some other reason. hawkmanArticle: 70755
Hey Hope someone can ansewer this problem quickly for me... I am using Protel DXP / Nexar i have a CLK source on GCK0... Pin 80, but when i am trying to use it as a normal port then i get this error : Class Document Source Message Time Date No. ProcessFlowError FPGA_Project1.ngd Map ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB 17:44:20 26-06-2004 11 I also tryed to use the CLK symbol from the Nanoboard libery with same problem Best regards KasperArticle: 70756
QuartusII 4.0 SP1, SOPC builder with Nios 3.2, Cyclone C4. I have the Nios32 @ 30mhz working fine with my user logic modules, but any ISR I try works a random number of times (1 to 30 times?) and then stops getting called. By bringing out some internal signals to pins, I can see that the irq signal from my module is asserted, but the ISR just does not get called. This is the first time I have tried using Nios interrupts, but I am getting it straight from the examples. As a test, I wrote an ISR that just increments and prints a count value, and does not clear the interrupt. There is no foreground code other than installing the vector and enabling interrupts. I would expect my ISR to get called indefinitely, (context save, execute, context restore), but it just works a random # of times and stops. This is the only handler I have installed, but I know the spurious handler is installed by default (it works), as well as the CWP handler (dont know if it works - how to test?). The behavior suggests stack/memory corruption from the context save/restore. I don't re-enable interrupts in my ISR, so I don't expect nested interrupts. I have seen weird behaviors whenever the systhesis does not match the assembled libraries used to compile (forgot to use 'Generate'), but I have triple-checked. Any ideas/new errata?Article: 70757
>Thanks Jim, but your suggestion is how it's done right now, the counter >resides in the CPLD. >my goal was/is to get rid of the 4046, and some r/c's. >since we're using a CPLD, why not create an 'all in one'approach? The basic idea is that it's hard to make a faster clock with digital logic. Especially clean logic. You can make a slower clock. For example if you have 1 MHz, you can get 1 KHz by dividing by 1000. You can lock the 1 KHz to a reference clock by dividing by 1001 or 999 on as many of the 1 KHz cycles as needed to make it match. The jitter in your output clock will be 1 cycle of your main clock. The external 4046 has a VCO in it. That's what you need to get the faster clock. The Rs and Cs are just a filter on the VCO control voltage. You probably can't get rid of them. You can do tricks with tapped delay lines. Read the Xilinx data sheets (or the archives for this list) on their DLLs. The numbers aren't good for building your own in a CPLD. You need enough gates so that their total delay is your cycle time. (You can go around several times, but that's the general time scale.) Then you need switching logic to select between N and N+1 or N-1 gates. The individual gate delay will be your clock jitter. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 70758
charles wrote: > Thanks Mike. I kindly of understand it now. But what is the best way to > handle clock domain crossing where you need to synchronize between the two > domains. http://groups.google.com/groups?q=fpga+dqdq > And I guess the clock domain part circuit really needs to be > tested with gate level simulation with the sdf back annotation, right? I > mean that is not part of synchronous design. No. See: http://groups.google.com/groups?q=flops+tack+Manjunathan > Thanks again! You are welcome. -- Mike TreselerArticle: 70759
Jim wrote: > Jim Granville <no.spam@designtools.co.nz> schreef in berichtnieuws <snip> >>DPLLs ( digital phase locked loops ) have phase jitter, so first >>step is to decide how much phase jitter you can tolerate @ 4MHz. >>To keep jitter reasonable, DPLLs need a time granularity well >>above the reqired Freq out, so you need a faster clock. >>You may decide an Analog PLL like a HC4046, with the divide in CPLD >>gives better performance. >>-jg >> > > > Thanks Jim, but your suggestion is how it's done right now, the counter > resides in the CPLD. > my goal was/is to get rid of the 4046, and some r/c's. > since we're using a CPLD, why not create an 'all in one'approach? To replace the 4046, look at the individual blocks of the 4046: The XOR phase comp, you can replace easily. The tri-state charge pump phase comparitor is harder, but you could probably get something with relaxed performance. The VCO is A cross coupled latch, with open drain outputs, and current sources. Current sources do not exist in CPLD, but you could make the OSC block, and use external sources. You will always need some RCs in an analog VCO/PLL. An alternative would be an LC osc, and a varicap diode, using some tiny logic - but you are still in the specialised extra parts domain. I have not seen a tiny-logic 4046, but that would be a good product. -jgArticle: 70760
Hello, dear all when I did my timing simulation, I got the warning message: # ** Warning: /X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.67 ns; Observed := 0.258 ns; At : 1.9 ns Can someone tell me more about the X_FF component from the simprim library? Or is there any link for the explanation. I failed to find out any in the past 60 minutes. Thanks for your help. Chao.Article: 70761
"Austin Lesea" <austin@xilinx.com> skrev i en meddelelse news:cb9t2d$cm02@cliff.xsj.xilinx.com... > Symon, > > Very funny. > > So we are unbelievably successful with S3. Is that our fault that we > somehow did not figure that they would be instantly shipped once they > got packaged? > > Triple whammy: 1) great part 2) great price 3)dot.com ending. > > Did you bother to read the S3 press release? 500K S3's in 2003? > > That is one helluva lot of FPGAs..... > > Some would have you beleive that 90nm was "too risky" and "had > availability issues" .... that is until they have their 90nm offering! > > Never even considered lo-K for S3 (too much $$$ for too little benefit). > > Lo-K was a Virtex II Pro 'issue' that we had to correct by process > tweaks and design. Let's face it, if we can still meet all of the > specifications without lo-K, why bother with the cost and reliability > issues? > > Austin Austinn, It seems to me that your a beating about the bush about the availability of spartan-3 chips. The thing is that Xilinx was very quick to announce the SP3 family very early, before even thinking seriously/or knowing about when they could actually be delivered (even in sample quantity). Add to that some problems about the design of IO's cells to get them 3.3V tolerant and I think also some uncertaintay about what functions should actually finally go into the chips - caused extra delay from protoypes to tested sample/volume production. Another thing is that all the software people involved in writing ISE and the EDK kits had to keep up to deliver the SW in time for the release of the chips It has given Xilinx and SP3 a somewhat bad reputation in the electronics business and propably also had the effect that a lot of designs haven't been done with SP3 (I know of a few at my job). Guess it's always a balance when to announce a new family. Too early gives a bad reputation and to late, causes the loss of design-in's. I'd say in this case it was announced 6 months too early. Don't know how it's going to go with the virtex-4 family, but I suspect we have the same story here, but I hope the delay won't bee as large as for SP3, as the 80 ns process is more mature and so are fx. the design of IO blocks with it ;-) Thanks anyway for designing good FPGA's. Keep up the good work ! Finn Nielsen DenmarkArticle: 70762
Does any development IDE have a video output tool?
The simulation tool should allow large amounts of video
data to be seen in one view. The data could be in
different formats with different line/blanking signals.
YCrCb color format would also be advantageous.
For me right now color isn't an issue.
Simple use would be to click on Video_In and
you would see a screen with your video input file,
and then write something like this, for example,
if Video_In > Threshold then
Video_Out <= 200;
else
Video_Out <= 40;
end if;
and then if you click on Video_Out, you would see
your thresholded video image, or any other video
processing you might be working on. Verilog would
be OK too.
Brad Smallridge
aivision.com
Article: 70763I developed a custom state machine design as a Master Peripheral using the Avalon Bus specifications. The purpose of this peripheral is to read/write to external memory (i.e. SDRAM). I then include this in SOPC Builder as a User-Defined Logic and define it as a Master Peripheral and associate my top-level entity ports to the appropriate names for the Avalon Bus. When I include the SDRAM controller as a slave, the SOPC Builder indicates that the Master is not connected to the slave, and the Slave is not connected to a Master. Since this is an off-chip device, I include an Avalon Tri-state Bridge into SOPC builder in order to allow SOPC Builder to automatically connect the Master to the Slave. However, when I do so, the message window indicates the contrary. The message I receive is as follows: tri_state_bridge_0/avalon_slave is not connected to any Master. Please connect it to a master of type avalon. Note that the Master peripheral defined is of type avalon and so is the SDRAM controller (as defined within the Memory devices in the System Contents directory tree). Can someone explain how I can properly connect a Master peripheral (user-defined of course) to the SDRAM controller slave? Why does the tristate bridge not allow this connection to occur? P.S. If this same excercise is done using a NIOS processor master + tristate bridge + SDRAM controller everything is connected with no errors. The only difference that I see is that my Master is a user-defined peripheral. Regards, PinoArticle: 70764
Short course: IMVIP 2004 http://www.cs.tcd.ie/IMVIP2004/ShortCourses.html Accelerating Matrix Algorithms on Reconfigurable Hardware for Image and Signal Processing Applications presented by Dr. Abbes Amira, Queens University, Belfast. (Provisional Schedule: Tuesday, August 31st 11.30-13.30). "Accelerating Matrix Algorithms on Reconfigurable Hardware for Image and Signal Processing Applications" In this Course, Dr. Amira will be presenting a number of solutions and tools to address and perform a range of applications in image, video and signal processing, 3D graphics and scientific applications. Dr. Amira will focus on the design, implementation and acceleration of matrix algorithms such as matrix operations, transforms and decompositions for image and signal processing using Field Programmable Gates Arrays FPGAs, different architectures, arithmetic techniques, design methodologies and design entries (Handel C, Schematic and VHDL). A range of matrix algorithms will be addressed including: Discrete Orthogonal Transforms DOTs for image and signal processing, Matrix Multiplication for array processing, Fast Fourier Transform (FFT) for frequency image filtering, Discrete Wavelet Transform (DWT) for Image and Video Compression, Singular Value Decomposition (SVD) for image denoising. Optimisation solutions will be also presented for reconfigurable hardware design using intelligent techniques. The problem of processing large matrices will be also addressed in this course. Course instructor Dr. Abbes Amira obtained an "Ingéniorat d'Etat" degree in Electronics and a DEA degree in image and speech processing from the National Polytechnic School of Algiers "ENP", a PhD degree in Computer Science and a PGCHET degree from Queen's University, Belfast (UK). He is currently a lecturer in Computer Science at Queen's University, Belfast, teaching computer architecture and algorithms and data structures. His research interests are in Design and Implementation of Digital Image and Signal Processing algorithms, Custom Computing using Field Programmable Gate Array (FPGAs), Hardware/Software Co- Design, System on Chip, Image Processing based Wavelet Transforms, Telecom Applications, Information Systems, Artificial Intelligence, Optimisation Techniques and Information Retrieval. He has written several papers in peer-reviwed conferences and premier journals and chaired a number of sessions in prestigious conferences. He is a regular reviewer for several IEEE, ACM, Elsevier Journals and Conferences such as DSP, TIP, ISCAS, ICASSP and DAC. Dr. Amira is a member of IEEE, ACM and SIGDA. He has carried out successful work in the use of FPGAs for implementing a range of matrix algorithms for signal and image processing applications. He is author of over 80 refereed conference and journal papers during his career to date. In October 2001 he was awarded an EPSRC grant for a proposal entitled "Coprocessor based Matrix Algorithms for Image and Signal Processing". This is a three-year project (worth £112,445). A number of solutions have been successfully implemented for processing large matrix multiplications, transforms and decompositions for image and signal processing applications. The research carried out during Dr. Amira's PhD project was concerned with an investigation into the design and implementation of a range of matrix algorithms such as matrix multiplication and one-dimensional transforms using a novel custom coprocessor system for MATrix algorithms based on Reconfigurable Computing (RCMAT). New algorithms for matrix multiplication, using both systolic and distributed arithmetic design methodologies have been developed. The architectures developed for matrix multiplication exploit different arithmetic techniques such as bit parallel, bit serial and digit serial design methods. In addition, novel architectures were developed to perform matrix transforms using both systolic and distributed arithmetic design methodologies. These architectures are scalable, modular and require less area and time complexity with reduced latency in comparison with existing structures. One of the most notable achievements of this work was a parallel matrix multiplier developed, outperforming the PAMBlox multiplier developed at Stanford University, USA. Dr. Amira has been invited several times to give talks to Universities and companies in UK and US, including University of Oakland at Michigan State, USA, University of Dundee, Scotland, UK and ANDOR company in Belfast.Article: 70765
In article <9qgDc.6750$OT6.5544972@news4.srv.hcvlny.cv.net>, news.optimum-online.com <anonymous@NOSPAM.org> wrote: >That coupled with Linux and Vxworks seems to >make the board pretty interesting. However, I haven't >seen much in the way of net traffic on it, and was >wondering if that was because it was so new or >some other reason. It may simply be that the board costs $2500 and requires the incredibly expensive full version of ISE rather than the freely- downloadable one to develop for; I get the impression that quite a lot of Net traffic comes from hobbyists who don't have the spare cash. TomArticle: 70766
Hello All,
I am a student in India .......
I have few queries regarding Sparatan 2 FPGA. demo board...
1) I am using a spartan 2 demo board from Insight ... I did implement
a design that use block rams on my circuit . i need to read back the
contents of block ram after the operation to verify my design. I am
trying to perform readback using hardware debugger with xchecker
cable. I have included the capture block in my design and also proerly
aplied the clock signal and cap signal .. but my readback gives me an
error ..." Readback data conatins all '1' , verify if rt/rd are
connected and readbcak is enable" I have enabled readback and clock
as CCLK during configuration. Mode is set to slave serial and m0,m1,m2
pins are made floating(no pullup)
2) I want to know if it is possible to use xchecker cable on
spartan-ii board or is multilinx a must ... i have been able to
properly configure using xchecker but couldnt readback .. that may be
bcos multlinix in slave serial uses same configuration for
configuaring device ....
3) To which fpga pins are rt/rd pins of xchecker cable connected ...
On xc4000 i belive rt/rd are multiplex with m0/m1 pin .. I have
verified using multimeter ... that rt/rd is not connceted to m0/m1 for
Sparartan 2 demo board.
4) Is there any CAD tools support for generating test vectors( esp
Delay Faults ) for Sparatan2 FPGA or any form of fault model is
availble for SParatan 2 FPGA.
Thanking all in anticipation
Sushmita
Article: 70767Hey... i hope there is a clever guy reading this channel and using Protel.... i have buyed a 3rd party FPGA board with a SpartanII SX2S300E... There is onboard Jtag (normal Xillinx Jtag) But when i want to use it with protel and use soft instruments etc... i have to connet "2 Jtags" at one time, one for the Hard Jtag to program the FPGA and one to normal I/O Pins... Quite easy just a multiplexer... but... Their owm Nanoboard has some kind a multiplexer so both chains can be selected at the same time... www.altium.com/learningguides/ AR0130_PCToNanoBoardCommunications.pdf i also hae the schematic here.... I can see on the schematic there is 2 parellel jtags in the parellel cable.. but i can't use the 2'nd as it is... but even more there is a mode and a control bit i dunno if i can do something m,ultiplexing with... Any one haveing a solution exept buying their board ? Regards KasperArticle: 70768
Hi, In ISE, in the properties of "Simulate Post-Place..." , you have to change the value of "UUT instance name" (which defaults to UUT), to the name you have used in your testbench to instantiate the design you are testing. Arnaud "Kavitha" <fpga_group_04@yahoo.com> a écrit dans le message de news:3bcfe252.0406251255.1cbf4ad6@posting.google.com... > Hi! > I am new to this news group.I am doing my project work in Xilinx(ISE > 5.2).I use Modelsim 5.6e for simulations. My design is in VHDL. The > simulations for Behavioral and Post-Translate are coming as > expected.But Modelsim is showing error when I do Post-Map simulations. > Name of my entity is strem_entity and testbench is test_bench. > > ---------------------------------------------------- > Modelsim is giving the following error: > ---------------------------------------------------- > # ** Error: (vsim-SDF-3250) stream_entity_map.sdf(0): Failed to find > INSTANCE '/UUT'. > # Error loading design > # Error: Error loading design > # Pausing macro execution > # MACRO ./test_bench.mdo PAUSED at line 10. > ------------------------------------------------------- > > When I open and see test_bench.mdo in note pad,it has following > contents: > ------------------------------------------------------------------------- > ## NOTE: Do not edit this file. > ## Auto generated by Project Navigator for VHDL Post-Map Simulation > ## > vlib work > ## Compile Post-Map Model for Module streamcompression > vcom -just e -87 -explicit -work work stream_entity_map.vhd > vcom -skip e -87 -explicit -work work stream_entity_map.vhd > vcom -just e -93 -explicit -work work test_bench.vhd > vcom -skip e -93 -explicit -work work test_bench.vhd > vsim -t 1ps -sdfmax /UUT=stream_entity_map.sdf -lib work testbench > do test_bench.udo > view wave > add wave * > view structure > view signals > view process > run 0ps > ## End > -------------------------------------------------------------- > > I don't have a instance by name UUT in my design.I think that is > created by project navigator.Could any one help me regarding this.I am > not able to understan why is modelsim giving the message.It would you > be great if any one can help me to over come this problem. > > Thank you, > -KaviArticle: 70769
Is there any difference apart from physical location of the global clk inputs GCK0 and GCK4 in a virtex fpga??Article: 70770
"chuk" <charlesg77@yahoo.com> skrev i en meddelelse news:faa526d6.0406271002.2222757@posting.google.com... > Is there any difference apart from physical location of the global clk inputs > GCK0 and GCK4 in a virtex fpga?? Proberly not... i just had a problem with using it before i enabled the clock_buffer :) cheersArticle: 70771
If your dividend is small enough and your target FPGA has enough spare memory, you also might consider table lookup. Another alternative is to let your synthesis tool create the table out of logic - write a program to create the verilog or vhdl ( for (i=0; i<2047; i++) print i, ":", i/11 ); etc). -StanArticle: 70772
The latest version of Precision is checking for the distribution, is there an environment variable that I can set to fake Precision into thinking that it's running on Redhat 8? The older versions of Precision run fine on Mandrake 10, unfortunately they added a test into Precision 2004a.Article: 70773
Hi,friends, To meet the Tsu requirement in my design, I think I should try to add some clock delay to the input register, how can I do that in CPLD? (not FPGA, without PLL,DLL) Thanks!Article: 70774
On Sat, 26 Jun 2004 15:40:40 -0700, "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote: >Does any development IDE have a video output tool? Not directly, but you can write some behavioural code in your test bench to capture the video and write it into a memory. Use the scripting facility of your simulator to read the contents of the memory and write it to a bitmap in a popup window. I know Modelsim can do this; I've seen it. (Note: this only works in the (expensive) versions of Modelsim that support Tk.) Regards, Allan.
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