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Philip Freidin wrote: > The output buffers of the Xilinx FPGAs can be configured for tri-state > control. Drive high, Drive low, and don't drive. The "don't drive" > state is generated by having a logic high on the tristate control > pin of the output buffer. If this signal is low, then the output is > driven, and the drive level depends on the other internal signal > that goes to the output driver. This is what a typical TS output does. No problem here. The problem arises with the PCI outputs configured as LVTTL TP outputs which, at least historically, were the very reason OC outputs were introduced because the latter would enable the designer to connect outputs in parallel without sinking huge currents (from another high driven TP driver for example). In the PCI case, the additional sink current (coming from the pull-up resistor) cannot be predicted since it's an implementation detail of the host system. > Connect "I" to ground, and connect your interrupt signal to "T". > The O pin will have the desired behavior. When T is high, O is > tri-stated, and either some other driver pulls the line low, or > the pull up resistor pulls the line high. So, are you suggesting to employ a TS TP output as OC output ? > Note: Do not use the on-chip pull-up resistor to establish your > logic high. Use an external resistor (probably in the rang 1K to 5K) > for the pull-up. Why? because the on-chip pull-up has too high a > resistance. Fiddling with the pull-up resistors is what basically would violate the PCI spec since it is the responsibility of the system board designer to apply these. Actually not my cup-o-tea this one ;) Cheers, ChrisArticle: 72901
The question is "Has anyone successfully integrated two DDR SDRAM controllers controlling one block of ram?" The alternate approach is to use the DSP HPI port as the transfer port between the shared SDRAM and the DSP. This would not rely on using the DSP DDR SDRAM controller to access the shared ram. The bandwidth takes a hit but the overall system preformance is not affected. Oh the internal memory of the DSP is large enough to hold program and data. The System: The system consist of a Cyclone or Stratix FPGA with a NIOS II, DMA and a DDR SDRAM controller internal to the FPGA. External are a TI DSP capable of being a DDR SDRAM controller. There is a block of DDR SDRAM shared between the FPGA and the DSP. The shared ram is for data exchange between the NIOS and DSP. After spending a few days looking over the ram, DSP and DDR SDRAM controller documents I'm thinking that the simplest approach to integration is to use the DSP's HPI port for data transfers between the shared memory and DSP. The HPI can be ran under DAM and has buffers both for read and write . While this approach isn't the fastest I think it has the best chance of working. The timing for the ram is tight, the control signals are slaved to the differential clock (implies switching the source of the clock between the FPGA and the DSP), debug nightmare and something I wouldn't want to argue in front of a peer review board. Comments? ARRRGGGGGHHHHH JerArticle: 72902
Thomas Rudloff wrote: (snip) > My suggestion is to > use a cypress Roboclock to get > four phases and use a CPLD to modulate the pulse. The CPLD path delays > are expected to be allmost > the same as long as you take care not to use more than five PTs. I just learned about the roboclock last week. According to the sheet I have it only goes to 80MHz. Maybe there are newer ones that go faster. > So in my application I have a 100MHz clock with four phases (1.25ns > increment) and the FF triggering > at rising and falling edges giving 800MHz resolution. > My interrest is to know whether I can archive the same precission > (<100ps) in an FPGA? The IOB FF's avoid the routing delay to internal FF's. I don't know about 100ps, though. -- glenArticle: 72903
At start-up for about 1 minute.
There is no problem with my internet connection (I get the "no updates
available" message before the hang)
I have Windows 2000
Help About says : Version 4.1 Build 207 08/26/2004 SJ Full Version
SP1 Installed
I had no problem with 4.0 SP1.
I uninstalled 4.0 before I installed 4.1
Does anyone have any ideas ?
Thanks,
Gary
Article: 72904
"sd" <azdunes@cox.net> wrote in message
news:r3spj0hosuefukrdbu1tts3dmkd65h56vv@4ax.com...
> Hello,
>
> I am a third year computer engineering student and have been given the
> task of completing an FPGA based project utilizing a Xilinx Spartan 3
> FPGA and VHDL. It just happens to be my luck that I have limited
> experience with FPGA architecture or VHDL however I do no intend to
> let this stop me from achieving this projects requirements. I am
> looking for experienced individuals of the FPGA development community
> that would be willing to aid me as mentors or technical advisors
> during the development of my project.
> The project is strictly academic and unfortunately the only thing that
> I can offer for any assistance is my gratitude.
>
> The proposed project has the following requirements:
> Must utilize a Spartan 3 FPGA
> Must be described using VHDL
> Must provide an accurate simulation of a 1980's era Pacman machine.
> Must be completed in 15 weeks.
>
> I have searched the net and discovered that this project has already
> been done by several clever individuals, however simply imitating
> their efforts will not further my education and I fear that using
> source code that has been produced by one group of individuals may
> limit my view on coding/design options.
>
> Please contact me if you feel that you can provide any assistance.
> Any assistance will be greatly appreciated.
>
I have read the above two replies. THIS IS A BIG PROJECT EVEN IF YOU KNEW
VHDL AND FPGAs.
I would go back to the professor and ask if it would be ok to:
1. Make the project a team effort.
2. Act as a system integrator/team manager using existing an CPU core,
video controller ect. Then write the code for a pacman game.
Yea you don't get to know the inner workings of a 6502 but you do
bring the project in on time which business wise is whats needed.
Managers make more money and get to be away from work on the
weekends. Engineers get to high five each other and ooggle over
thier latest creation in the lab. Engineers get out sourced and
guess who outsourced them.
Article: 72905charles wrote: > But my understanding is that you will always need stimulus or test vectors > to simulate your design to see if they are functionally correct. So I guess > what you mean by STA not needing test vectors is that the static timing > analyzer will check all the paths in the design to find the paths with > longest delay to determine the maximum operating frequency. For synchronous design all FFs clock together, so static timing tells just about all you need to know. Tools are designed for synchronous logic, and people design using synchronous logic because that is what the tools do. If you have multiple clock domains, gated clocks, or otherwise not all FF's have the same clock then you need to do timing analysis that takes that into account. There is also dynamic logic, similar to DRAM where data is stored on capacitors. Many early Intel processors used dynamic logic, where the minimum clock frequency was 2MHz or so. Possibly that is the origin of the static/dynamic timing analysis. -- glenArticle: 72906
Hi Rene,
I know a CD is available if requested. I wil forward this to the person
responsible for this so that he can get you the CD.
Subroto Datta
Altera Corp.
"Rene Tschaggelar" <none@none.net> wrote in message
news:413e208e$0$700$5402220f@news.sunrise.ch...
>I got a mail that SP1 of the Quartus2 V4.1 was available
> for download.
> After a few unsuccesfull login attempts, partly due
> to the overloaded server partly due to me not knowing
> the login parameters, my motivation to download the 120MB
> or so vanished.
> Anyone knows whether the paying users get this update on
> CD mailed home ?
>
> Rene
> --
> Ing.Buero R.Tschaggelar - http://www.ibrtses.com
> & commercial newsgroups - http://www.talkto.net
Article: 72907
Hi Gary,
On the Tools->Options->Internet Connectivity first disable the two
startup boxes. If the problem still persists, check if the license that is
being used under Tools->Options->License Setup is accessible. It is not
clear from your description if you have a floating license or a node locked
license, or if you are using the LM_LICENSE_FILE. If licensing is the
problem send me email describing the type of licensing that is being used
and the platform on which you are running Quartus.
Subroto Datta
Altera Corp.
"Gary Pace" <xxx@yyy.com> wrote in message
news:UWs%c.46628$Xi.6548@fe1.texas.rr.com...
> At start-up for about 1 minute.
>
> There is no problem with my internet connection (I get the "no updates
> available" message before the hang)
>
> I have Windows 2000
>
> Help About says : Version 4.1 Build 207 08/26/2004 SJ Full Version
> SP1 Installed
>
> I had no problem with 4.0 SP1.
>
> I uninstalled 4.0 before I installed 4.1
>
> Does anyone have any ideas ?
>
> Thanks,
> Gary
>
>
>
Article: 72908If I were you I would use the Picoblaze to talk to the A2D. I'm not sure how good at VHDL or Verilog you are, but the Picoblaze is an easy to use softcore CPU availible on the Xilinx Website. You'll write assembly instructions and connect the output/input port on the Picoblaze to the A2D. Xilinx has excellent app notes on how to use the Picoblaze. Good Luck.Article: 72909
"Rene Tschaggelar" <none@none.net> wrote in message news:413e208e$0$700$5402220f@news.sunrise.ch... > I got a mail that SP1 of the Quartus2 V4.1 was available > for download. > After a few unsuccesfull login attempts, partly due > to the overloaded server partly due to me not knowing > the login parameters, my motivation to download the 120MB > or so vanished. I've just downloaded it without any problems. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 72910
"Gary Pace" <xxx@yyy.com> wrote in message news:UWs%c.46628$Xi.6548@fe1.texas.rr.com... > At start-up for about 1 minute. > > There is no problem with my internet connection (I get the "no updates > available" message before the hang) > > I have Windows 2000 > > Help About says : Version 4.1 Build 207 08/26/2004 SJ Full Version > SP1 Installed > > I had no problem with 4.0 SP1. > > I uninstalled 4.0 before I installed 4.1 > > Does anyone have any ideas ? FWIW, it works OK for me with WinXP. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 72911
Thomas Rudloff wrote: <snip> > Hi, > > I am currently developping the oposite and came up that it might not be > good to use an FPGA because of > routing delays that might no be equal on all paths. My suggestion is to > use a cypress Roboclock to get > four phases and use a CPLD to modulate the pulse. The CPLD path delays > are expected to be allmost > the same as long as you take care not to use more than five PTs. "almost the same" depends on what precision matters.... > > So in my application I have a 100MHz clock with four phases (1.25ns > increment) and the FF triggering > at rising and falling edges giving 800MHz resolution. > > My interrest is to know whether I can archive the same precission > (<100ps) in an FPGA? > > Regards > Thomas > > PS: It is a PWM modulator for a digital amplifier. It is not clear what you are trying to do. From the application, more than your questions, it sounds like you wish to control an edge position to a precision of ~100ps ? On what lower Frequency ? You can use multiple phase clocks to improve timing precision above 1/fclk and getting to 1ns has the consensus of do-able. If your modulator frequency is high, you can also use rate-multiplier edge modulation, to give better audio-band precision ? To get to 100ps is going to push away from the realm of clock edges, and into the realm of silicon delay lines. I think there are test modes in the DLLs, and carry chains are the user fabric with the most speed. Philip F. made this comment in another thread re Virtex4 > Looks like a 32 bit counter hits 360 MHz, in a -11, with preliminary > speed files. Gotta love the 41.5 ps/bit carry chain. that suggests a time granularity of sub 50ps will be doable in the next generation devices - these delays need continuous calibration, as they will be Vcc/Temp/Process dependant. -jgArticle: 72912
Philip Freidin wrote: > Phil Hays wrote: >>Generally this is a bad place to ask for help with homework questions. > >Which I think is a bit harsh, as S. Daniel does seem to indicate that >he/she wants to further their education. So this is not our typical >lazy homework hunter. Perhaps. I wanted to give help without encouragement to the "typical lazy homework hunter". >>But here are some hints. > >Which are all pretty good, except maybe the following: > >>Keep at it. We should not hear from you for the next 15 weeks. > >I think better guidance is that if you come to this news group looking >for a solution on a plate, you will get ridiculed pretty strongly. On the >other hand, if you demonstrate you have thought about the problem, have >some tentative solutions, and would like some guidance in better focussing >on the trade offs, then we tend to be a pretty helful bunch. I agree. -- Phil Hays Phil-hays at posting domain should work for emailArticle: 72913
Rune Christensen wrote: > > I think that this must the easiest solution to the problem. Create a VGA > card that transfer the screen to ethernet instead of a screen. Maybe a PCI > FPGA card could be used to do this. > > To the people on comp.arch.fpga have anyone tried to create a VGA card on a > PCI FPGA card? > There are VGA capturing solutions, but it's probably easier to do with DVI. Doing a VGA card is pretty difficult; VGA is a pretty complex thing. It is probably easier to have a standard video chip which outputs DVI or some kind of LCD interface, and then capture it and send out the Ethernet in whatever protocol you wish. -hpaArticle: 72914
Hi, Can anybody elaborate on the speed of the simulation in systemC in comparision with Verilog. In our case we have used the systemC for the modeling of RTL design, then verified the systemC RTL models. As a final step systemC RTL is converted into verilog RTL(line by line translation). we are surprised to see the both systemC models and Verilog models are running at almost same speed. Can you through some light on it, what went wrong in the process? is it systemC coding is not proper or may be testbench not written properly or if we code systemC and Verilog at same level of abstraction we should same speed only.Article: 72915
awsome_vedant@yahoo.com (vedant) wrote in message news:<5c3117ba.0409052301.7c13fdf4@posting.google.com>... > hi ! > (1) untill which stage does SOC development and FPGA development is > common ?(i.e. design entry,simulation,synthesis,implementation). > > (2) Are there any tools available for SOC development like those > available for FPGA development by xilinx and altera on their > respective websites? > > Regards > ved Hi, It looks like SOC is a Classification of chip not a technology. Any SOC can be implemented in FPGA / ASIC. If the chip contains functionality of a system, then we shall call it as SOC. Some one correct if my understanding is not correct. Here is a question further on this, Normally people refers any FPGA / ASIC project which contains many IP cores and some RISC processors as SOC. How ? Regards, MuthuArticle: 72916
mnamky@hotmail.com (Mohamed Elnamaky) wrote in message news:<bceb5f12.0409062154.6c8ea159@posting.google.com>... > Dear all; > Please tell me if I'm wrong. A typical design cycle for FPGA is to use > the IEEE and Unisim libraries and their primitives (if you wish) and > run the functional simulation with Modelsim and after that you go for > some synthesis tool like LeonardoSpectrum or Precision RTL. Am I > right? > > ps. I know, that in case you don't want to sue the primitives as IPs > in your design, the synthesis tool will extract them automatically if > you restrict yourself to some kind of standard templates. > > I know that I might be missing a lot. Give me directions please. > > Thank you.. > > ps. in what way can I use SIMPRIM library? Hi, FPGA design cycle looks as below: -Requirement gathering -Architecture and high level design -Low level Design -RTL Coding (Can include Xilinx primitives like block RAM, FIFO - coregen module) -RTL simulation -Synthesis & place and route -Bit file generation and Bit downloading To answer you question on SIMPRIM; Since a portion of RTL contains primitives from Xilinx / any FPGA vendors, we need some behaviroual model for RTL simulation. thats what SIMPRIMS - SIMulation PRIMitiveS During synthesis, we will be adding the FPGA library which has gate implemenetaion of these primives. Regards, MuthuArticle: 72917
Try the newsgroup comp.lang.vhdlArticle: 72918
"Rene Tschaggelar" <none@none.net> wrote in message news:413e208e$0$700$5402220f@news.sunrise.ch... > I got a mail that SP1 of the Quartus2 V4.1 was available > for download. Is there anything much new in SP1? Full programming support for a Max II and a Stratix II device is all very well if you are using these devices, but if not, is there anything much changed? I'll no doubt download it sometime, but I'm just wondering how urgent it is.Article: 72919
"David Brown" <david@no.westcontrol.spam.com> wrote in message news:chmbo6$a9m$1@news.netpower.no... > > "Rene Tschaggelar" <none@none.net> wrote in message > news:413e208e$0$700$5402220f@news.sunrise.ch... > > I got a mail that SP1 of the Quartus2 V4.1 was available > > for download. > > Is there anything much new in SP1? Full programming support for a Max II > and a Stratix II device is all very well if you are using these devices, but > if not, is there anything much changed? I'll no doubt download it sometime, > but I'm just wondering how urgent it is. There seems to be lots of new stuff, here are the headings: a.. New Device Support b.. EDA Tool Support c.. Optimization Advisors d.. In-System Memory Content Editor e.. Technology Map Viewer f.. Version-Compatible Database Files g.. Stratix II Physical Synthesis Optimization h.. Copy Project Feature i.. ISP CLAMP State Editor j.. SOF Manager in SignalTap II Logic Analyzer k.. Importing & Exporting Assignments in CSV Format l.. Chip Editor m.. Messages Window n.. The Quartus II Tutorial o.. MegaCore IP Library p.. Nios II Embedded Processor q.. Logic Options r.. I/O Standards s.. Megafunctions LeonArticle: 72920
Hello: We work in a similar way than you, we first made the RT model in SystemC, we verificate it using TLM style with SCV features and then we made a automatic translation to Verilog using a tool we will release very soon under GPL license at www.opensocdesign.com. You are rigth, our measures also indicates that the simulation in SystemC and in Verilog run at almost the same speed. SystemC creators said that one of the advantages of SystemC is the speed, obviously is not true, maybe Cadence NCSystemC is faster, I dont know, but the GPL implementation of SystemC not. But the main advantage I think is not the simulation speed. I think the main advantage of SystemC is the verification environment, the SystemC Verification Library and the easy way to integrate C code that allows to create a very powerfull verification environment. It is true that you can also can made similar things using Verilog and PLI but is not so easy and here with simulating Verilog with PLI, the simulation is slower than one only with SystemC. Regards Javier Castillo jcastillo@opensocdesign.com www.opensocdesign.com singh.shailendra@gmail.com wrote in news:ab4d6621.0409072214.6b8ae5a@posting.google.com: > Hi, > Can anybody elaborate on the speed of the simulation in systemC in > comparision with Verilog. In our case we have used the systemC for > the modeling of RTL design, then verified the systemC RTL models. As > a final step > systemC RTL is converted into verilog RTL(line by line translation). > we are surprised to see the both systemC models and Verilog models are > running at almost same speed. Can you through some light on it, what > went wrong in the process? > is it systemC coding is not proper or may be testbench not written > properly or > if we code systemC and Verilog at same level of abstraction we should > same speed only. >Article: 72921
sd wrote: > The proposed project has the following requirements: > Must provide an accurate simulation of a 1980's era Pacman machine. > Must be completed in 15 weeks. May I suggest that you use a readily-available CPU core. It's a tall order to ask that in 15 weeks you learn VHDL and implement a full CPU core as well as the surrounding logic. Are you looking at copying the arcade machine behaviour verbatum? Or is a functional equivalent sufficient? For the former, you'll need to study and understand the game schematics completely. For the latter, you'll need to understand the function of the components in the game (tiles, sprites, etc) and come up with your own designs for those. Obviously you need to choose a game. A Z80-based game is probably the easiest as a fnuctional opencore is available (grab the version from fpgaarcade.com). As for the game, well, Pacman has been done to death! <http://members.iinet.net.au/~msmcdoug/pace/Nanoboard/nanoboard.html> You will probably be limited by the amount of ROM/RAM available as well. If you choose your direction and CPU I might be able to give you some suggestions on which games would be suitable. You *should* have fun doing this! Good luck! Regards, -- | Mark McDougall | "Electrical Engineers do it | <http://to be announced> | with less resistance!"Article: 72922
> > > > Is there anything much new in SP1? Full programming support for a Max II > > and a Stratix II device is all very well if you are using these devices, > but > > if not, is there anything much changed? I'll no doubt download it > sometime, > > but I'm just wondering how urgent it is. > > There seems to be lots of new stuff, here are the headings: > a.. New Device Support > b.. EDA Tool Support > c.. Optimization Advisors > d.. In-System Memory Content Editor > e.. Technology Map Viewer > f.. Version-Compatible Database Files > g.. Stratix II Physical Synthesis Optimization > h.. Copy Project Feature > i.. ISP CLAMP State Editor > j.. SOF Manager in SignalTap II Logic Analyzer > k.. Importing & Exporting Assignments in CSV Format > l.. Chip Editor > m.. Messages Window > n.. The Quartus II Tutorial > o.. MegaCore IP Library > p.. Nios II Embedded Processor > q.. Logic Options > r.. I/O Standards > s.. Megafunctions > That sounds a bit more reasonable for a 120 MB download ! However, I too keep getting "server too busy" errors. I can't understand why Altera is so obsessed with using https and getting personal details of everyone downloading these things - it's a service pack, useless to anyone who doesn't already have licensed Altera software. It should be a straight ftp download, which would avoid such irritations.Article: 72923
Dear George, I would like to thank you for your understanding. Unfortunatelly I'm not student. (I'm too old to be a student.. When I was student, I was working with tubes (not even with transistors) ). It is not so easy in my age to keep track with the all this new technologies. I'm trying my best to follow the technology. I recently started to study the VHDL. I'm almost on the "page one" of the VHDL study and want to learn by implementing simple little projects. Thank you once again for your understanding. Regards. "George" <clarkgsmith@comcast.net> wrote in message news:Lu6dnWOuIaK8v6PcRVn-iQ@comcast.com... > > "jamie" <jamie@noway.com> wrote in message > news:vSi%c.11928$lP4.871282@news20.bellglobal.com... >> Patrick Harold wrote: >> > I'm new to VHDL and I want to learn as with examples. >> > I want to build a 16,24 or 32 bit counter for quadrature encoder >> > signals > (ie >> > A,B signals). >> > Can someone help me how to create following functionality in VHDL ? > <snip> >> > >> >> Taking a VHDL class are we? > > What difference does it make if he is taking a VHDL class and needs help. > He seems honest, and forthcoming. "I'm new to VHDL...." etc. Bro, if I > knew VHDL I would personally help you, but last time i saw VHDL was in > college about 11 years ago. > > Yall should help the guy, ESPECIALLY if he is a student. > >Article: 72924
Thank you. I'm afraid, I did not realized that there exists "comp.lang.vhdl" group. "ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0409072251.5626ab3c@posting.google.com... > Try the newsgroup > > comp.lang.vhdl
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