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>And being a professional EE for over 25 years, having designed a few dozen >ASICs, and worked with hundreds of ASIC designers, I've never heard anyone >refere to ASICs as anything but hardware. So, I can't imagine what >professionals he is referring to that would think an ASIC was software! How about software that gets burned into a ROM? What fraction of the design manpower for a typical modern ASIC is like designing software in the sense of simulation and chasing logic bugs as compared to analog and chasing timing bugs? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 73051
But for CPLD there may be a limit as > its technology is > based on flash/eeprom. Hi ,, i have one more doubts., ie., I used my parallel cable III , that detect my fpga say spartanII. also, i have parallel cable IV, i used this one to detect my fpga.. but it doesn't detect. I tried many times. But not possible. Is there any configuration to detect the fpga via parallel cable IV. r what is the diff between the parallel cable III & IV? Give me some suggestions.. Regard Senthil.RArticle: 73052
Austin Franklin wrote: > I need some help with something. Someone made some technical claims > that I am questioning are correct or not ;-), and would like to see > what you guys think about these claims: Homework?Article: 73053
Austin Franklin wrote: > One more claim from our "candidate": > > "And none of the professionals I've talked to referred to ASICs being > hardware. You can't buy an ASIC, you have to design it, which makes > > its function software." > > And being a professional EE for over 25 years, having designed a few dozen > ASICs, and worked with hundreds of ASIC designers, I've never heard anyone > refere to ASICs as anything but hardware. So, I can't imagine what > professionals he is referring to that would think an ASIC was software! Until it is sitting there, gleaming at you on the wafer, it is 100% software. Once it is designed, and you want your second million, then it is very much hardware. So it is one of those semantics arguments, that depends on where you are in the design life cycle. -jgArticle: 73054
pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0409061419.32cb8013@posting.google.com>... > To all, > > I am currently using an example from a book which codes a simple > FSM. The code is seen below. I simulate the following FSM obtained > from a text book under Quartus 4.0 with the condition that "in1" > signal is low for one clock-cycle commencing at the negative edge of > the clock for an entire period. During this time, the state machine > is in the "START" state, and the output changes to sequence = > "continue" and the output changes immediately given a small delay > (less than 1/2 clock period). I have sketched out the timing diagram > as it appears in the simulation from the text book. For some reason, > when I simulate this same state machine in Quartus with the same 10 ns > clock period, I end up getting "out1" delayed by more than half the > clock period. I'm simulating using a stratix chipset speed grade -6. > Unbelievably long time of a propagation delay, so does this sound > right to anyone? > > ---- ----- ----- > | | | | | <= clock > | | | | | > ---- ---- ---- > > ---- -------------- > | | <= in1 > | | > --------- > > --------- > | | <= out1 > | | > ----------- --------- > > --------- > | | <= out2 > | | > --------------------- --------- > > ENTITY Test IS > PORT( > clk, in1 :IN STD_LOGIC; > out1, out2 :OUT STD_LOGIC > ); > END ENTITY Test; > > ARCHITECTURE a OF Test IS > TYPE PULSER IS (start, continue); > SIGNAL sequence: PULSER; > BEGIN > > PROCESS(clk) > BEGIN > IF clk'EVENT AND clk = '1' THEN > > CASE sequence IS > when start=> > IF in1 = '1' THEN > sequence <= start; > out1 <= '0'; > out2 <= '0'; > ELSE > sequence <= continue; > out1 <= '1'; > out2 <= '0'; > END IF; > when continue=> > sequence <= start; > out1 <= '0'; > out2 <= '1'; > > END CASE; > END IF; > END PROCESS; > > END ARCHITECTURE a; Hi, It looks like out1 is a top-level output of your design. That means it is being implemented in an IO pad, and the delay you are getting includes the output pad delay driving the default load (10 pF for Stratix LVTTL IOs). That will be a significant delay. Also, there is a significant delay in getting the clock from the clock input pad (where the simulator monitors it) to the clock input of the various flip flops (unless you use a PLL). So a ~5 ns delay (Tco) is not unreasonable. Vaughn AlteraArticle: 73055
Hi, Can anyone explain me at what maximum frequency does the OPB,PLB and DCR bus operates in a vitex2p based powerpc's.Any idea which is slowest and which is fastest? Regards, NavyaArticle: 73056
Hello I am trying to learn systemc. Systemc was already installed in one of the servers and I am using Solaris 2.8 with gcc 3.3 I am trying to run example programs from the installation directory. However when I run make i get error message -------compiles the code and generates .o -------- ---- g++ -I. -I.. -I/_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8/include -L. -L.. -L/_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8/libS/gcc-3.2.2 -o run.x source.o sink.o fft.o main.o -lsystemc -lm 2>&1 | c++filt Undefined first referenced symbol in file CoolLog::CoolLog[in-charge](char const*, char*, bool)/_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8/libS/gcc-3.2.2/libsystemc.a(sc_main.o) ld: fatal: Symbol referencing errors. No output written to run.x collect2: ld returned 1 exit status I tried to do everything I could but it seems there is some problem in makefiles. Following are the makefiles I used. Makefile TARGET_ARCH = gccsparcOS5 CC = g++ OPT = -O3 DEBUG = -g OTHER = -Wall EXTRA_CFLAGS = $(OPT) $(OTHER) # EXTRA_CFLAGS = $(DEBUG) $(OTHER) MODULE = run SRCS = source.cpp sink.cpp fft.cpp main.cpp OBJS = $(SRCS:.cpp=.o) include ../Makefile.defs Makefile.defs ## Variable that points to SystemC installation path SYSTEMC = /_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8 INCDIR = -I. -I.. -I$(SYSTEMC)/include LIBDIR = -L. -L.. -L$(SYSTEMC)/libS/gcc-3.2.2 LIBS = -lsystemc -lm $(EXTRA_LIBS) EXE = $(MODULE).x .SUFFIXES: .cc .cpp .o .x $(EXE): $(OBJS) $(SYSTEMC)/libS/gcc-3.2.2/libsystemc.a $(CC) $(CFLAGS) $(INCDIR) $(LIBDIR) -o $@ $(OBJS) $(LIBS) 2>&1 | c++filt .cpp.o: $(CC) $(CFLAGS) $(INCDIR) -c $< .cc.o: $(CC) $(CFLAGS) $(INCDIR) -c $< clean:: rm -f $(OBJS) *~ $(EXE) core ultraclean: clean rm -f Makefile.deps Makefile.deps: # $(CC) $(CFLAGS) $(INCDIR) -M $(SRCS) >> Makefile.deps #include Makefile.deps Please help somebody, bu mailing me a running code or suggesting any modifications to this code.Article: 73057
I am having a problem with the timing on our new board. I need to delay one of the output signals from my cpld by 80nS. Im not that familiar with using the altera quartus software, all the timing issues it talks about is to speed it up. Is there a way of adding a delay, i've also tried adding a delay into a vhdl block but it is having no effect! i would b grateful for any help paulArticle: 73058
Hi In theory it's possible to create a device class for for a Virtex II pro, just take an existing one for Virtex II and alter the constants. I think this is possible because all the components are equal they are just displayed in a different manner but you can only work with areas without PPC because there is no information to how the surroundings GRM work. So in conclusion i think it's possible to have limited support to Virtex II pro but some reverse engineering is needed. Miguel mahim_usenet@yahoo.com (Mahim Mishra) wrote in message news:<759865b0.0409111313.3cbbcd9e@posting.google.com>... > Hello all! > > I am using Xilinx Virtex-II Pro (XC2VP20 and XC2VP50) chips, and was > wondering if I can use JBits 3.0 to manipulate the configuration > bitstreams for these chips. It seems not, since the JBits "Device" > class seems to only have defined constants for Virtex and Virtex-II > chips. Has anyone done this before, or knows that it can be done? > > Thanks, > MahimArticle: 73059
Austin Lesea <austin@xilinx.com> wrote in message news:<cht42i$6o86@cliff.xsj.xilinx.com>... > Symon, > > Yes, it would. That is a nice trick, but you trade one problem (duty > cycle) for another, getting a 622 MHz signal into the chip (SI is much > tougher the higher the frequency). > > I think John's problem is more that he has a clock that switches between > two sources. If the clock must switch, then you best reset the DCM. > > Austin > > Symon wrote: > > Austin, > > If John's used the input divide-by-2 mode, to make 311MHz from 622MHz > > wouldn't that take care of any duty cycle problems? > > Cheers, Syms. > > "Austin Lesea" <austin@xilinx.com> wrote in message > > news:chprct$73l1@cliff.xsj.xilinx.com... > > > >>John, > >> > >>There have been cases where the frequency, jitter, and duty cycle are > >>just on the edge of where the DCM phase detector will operate reliably. > >> > >>Check the input duty cycle. It will need to be as close to 50% as you > >>can make it. The spec is 45 to 55%, but at the higher frequencies, it > >>may have to be even closer to 50% when you take clock jitter into > >>account (as if it is 45%, and it has jitter, then it is sometimes less > >>than 45%!). > >> > >> > >>John Cappello wrote: > >> > >> > >>>Hi, > >>> > >>>We are seeing evidence that a DCM is intermittently selecting the > >>>wrong tap position after it completes its lock sequence after a DCM > >>>reset pulse. I'd like to know if anyone has experienced this effect, > >>>and if they were able to resolve this problem. > >>> > >>>In a 2v6000, I am using a variable phase shift DCM which is driven by > >>>a 622 MHz clock (divide-by-2 mode). The DCM generates 311 MHz clocks > >>>on its clk0/clk180 output pins. This interface uses IOB DDR regs for a > >>>622 Mhz/16-bit LVDS transmission solution. > >>> > > > > > > Hi Austin, I wanted to focus more on the DCM reset. As you may recall, we can fix or break our system with multiple DCM resets. Whether due to bad clock or fluctuating voltges, why would you suppose the integrity of the dcm's output is decided only during this reset sequence? I am confused because it seems that the DCM is constantly updating its tap position in response to its phase comparators even during the locked state. Thanks. JohnArticle: 73060
Thanks a lot Peter, It solved the problem ! Stéphane On Wed, 08 Sep 2004 08:06:14 -0700, Peter Ryser wrote: > You seem to be using just one clock for the whole system. On the other > hand you specify a 3:1 ratio between processor and OCM with the > following settings: > PARAMETER C_DSCNTLVALUE = 0x85 > PARAMETER C_ISCNTLVALUE = 0x85 > > Try changing these values to 0x81. > > You might also want to consider to upgrade to the latest EDK version. > > - Peter > >Article: 73061
I have a Cyclone Nios development board, which I'm using for some test development work. The clocking system on the board seems very strange to me - I'm wondering if it *is* strange, or if I've just misunderstood things. The board has a 50 MHz oscillator that is used to generate the base clock for the fpga and a signal out to the prototyping cards. That's fair enough. However, there is only one available clock signal out of the fpga, which is then passed through an external clock buffer to generate clocks to the prototype cards and a feedback signal to the fpga. I find this painfully limiting, and can't think of a good reason why the card is designed this way. It means I have to use the same clock signal to both prototype connectors, and it means that the feedback signal used for the sdram pll comes from this same clock. In my design, I want the processor to run at 60 MHz, while the external clock to the prototype cards is at 50 MHz. This means that the sdram pll must generate its 60 Mhz signal from a 50 MHz feedback, independantly from the main 60 MHz system clock. The phases for these clocks are therefore not determined - sometimes my sdram works, sometimes not. Is there something I'm missing here, or is it just a strange card design? -- David "I love deadlines. I love the whooshing noise they make as they go past." Douglas AdamsArticle: 73062
Thanks for the response guys, but I have just realised I made a stupid beginners mistake ! I made the silly assumption that devpor was 'active high' because it doesn't have an 'n' suffix like the 'active low' devclrn. Consequently, when I thought I had cancelled devpor, it was actually active. Made the adjustment and everything kicks into life. "Subroto Datta" <sdatta@altera.com> wrote in message news:<TLt0d.1308$Vu2.948@newssvr16.news.prodigy.com>... > Johnny, Can you send the small design along with your testbench to us. We > would like to understand the problem. It will be very useful if you can > describe the time slice where the problem is seen, and the expected > behavior. > > Subroto Datta > Altera Corp. > > "JohhnyNorthener" <johnnynorthener@yahoo.co.uk> wrote in message > news:95e91aaf.0409100134.4730959c@posting.google.com... > >I am having problems simulating fifos with quartus and modelsim. > > My environment is set up as follows: > > > > Quartus II v4.1 SP1 > > Modelsim-Altera 5.8c (with updated sim models) > > > > I was seeing problems on a large design I have, whereby the the data > > was not coming out of the fifo when being read. > > As this was a large desing I decided to create a new project/design > > which contains ONLY a fifo (LMP_FIFO+, single clock) and simulate > > that. > > I have generated the .vho file for use with Modelsim-Altera and > > simulated this with my own testbench. > > > > > > One thing worth mentioning is that when I start the simulation, I get > > a load of warnings from Modelsim:- > > > > ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an > > arithmetic operand, and it has been converted to 0. > > # Time: 0 ps Iteration: 0 Instance: > > /fifo_test_tb/fifo_test_i0/fifo_i0/scfifo_component/auto_generated/dpfifo/fiforam/segment_a0_a_a0_a > > > > ...this is just because I haven't specified an .init file for the > > fifo, but this won't prevent correct operation...will it ! ? > > > > When I bring up the waves I can see the following:- > > > > (i) the clock is running > > > > (ii) reset, devpor, devclrn are all asserted (correct polarity) > > at start of the sim and then de-asserted 100 ns later. > > > > (iii) the wr_req is set active, and the data_in has an > > incrementing pattern > > > > (iv) valid_wrreq (internal to the LPM_FIFO+ component) is active > > as expected > > > > (v) ww_fiforam_wraddress (internal to the LPM_FIFO+ component) > > increments as expected > > > > (vi) fifo_usedwd (internal to the LPM_FIFO+ component) increments > > as expected > > > > (vii) empty and almost_empty (internal to the LPM_FIFO+ component) > > get cancelled as expected > > > > (viii) rd_req is set active > > > > (ix) valid_rdreq (internal to the LPM_FIFO+ component) is active > > as expected > > > > (x) ww_fiforam_rdaddress (internal to the LPM_FIFO+ component) > > increments as expected > > > > (xi) fifo_usedwd (internal to the LPM_FIFO+ component) freezes > > since I am writing and reading at the same rate as expected > > (only start read once fifo_usedwd reaches about 12) > > > > (xii) BUT, no data appears at the output port, even though > > everything else suggests that the fifo is being operated > > correctly ! > > > > > > Can anyone offer any assistance > > (I have also submitted a service req to Altera, but on previous > > experience am not to confident in the response I 'might' receive) > > > > Any assistance would be very much appreciated > > > > JohnnyNorthenerArticle: 73063
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:s791d.3289$mZ2.305623@news02.tsnz.net... > Austin Franklin wrote: > > One more claim from our "candidate": > > > > "And none of the professionals I've talked to referred to ASICs being > > hardware. You can't buy an ASIC, you have to design it, which makes > > > > its function software." > > > > And being a professional EE for over 25 years, having designed a few dozen > > ASICs, and worked with hundreds of ASIC designers, I've never heard anyone > > refere to ASICs as anything but hardware. So, I can't imagine what > > professionals he is referring to that would think an ASIC was software! > > Until it is sitting there, gleaming at you on the wafer, it is 100% > software. By your understanding, any design, what so ever, is software? Even a schematic? So, a board level schematic is software as well? VHDL and Verilog code is software? > So it is one of those semantics arguments, that depends on where you > are in the design life cycle. I very much disagree that it is a semantics argument. It is an argument of understanding or not understanding concepts IMO. Regards, AustinArticle: 73064
"Mark McDougall" <markm@vl.com.au> wrote in message news:41451b41$0$22790$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > Austin Franklin wrote: > > > I need some help with something. Someone made some technical claims > > that I am questioning are correct or not ;-), and would like to see > > what you guys think about these claims: > > Homework? Not really.Article: 73065
Hello, I am programming EPM3064ALC44-7 using JTAG-ByteBlaster. I will use the exact circuit shown in Figure 2 of application note AN-95 from Altera which describes connections to JTAG header and will also supply power to device through, VCCIO and VCCINT pins (3.3 Volts). However, I am trying to make a prototype board, which will only program devices using JTAG header (might seem crazy, but this is purely academic). Question: So, I need to know, how much current (Icc) is drawn by the device while only programming it (through pins VCCIO, VCCINT and JTAG pins on device), so that I can use a supply with minimum current requirement. Thanks, DrewArticle: 73066
agarvey@kimble.ie (Paul Gray) wrote in message news:<263cf391.0409130157.7676f3ed@posting.google.com>... > I am having a problem with the timing on our new board. I need to > delay one of the output signals from my cpld by 80nS. Im not that > familiar with using the altera quartus software, all the timing issues > it talks about is to speed it up. > Is there a way of adding a delay, i've also tried adding a delay into > a vhdl block but it is having no effect! > i would b grateful for any help > paul 80ns is a long delay. What's your clock speed? You could make a shift register using a chain of flip flops or even use a counter. Failing that, you could cascade several I/O block delays i.e. go off- and back on-chip a few times. You might even consider buying a passive delay line.Article: 73067
Hi, Is anybody here tried to design it's own IP with a PLB master/slave ? Is the PLB IPIF OK ? How did you managed with the template ? Indeed, My EDK version (Release Xilinx EDK 6.2 - platgen EDK_Gm.11) lacks some of the templates wich are described in the "User Core Templates Reference Guide". Does anybody could give me those templates ? Thanks a lot for your help StéphaneArticle: 73068
"Paul Gray" <agarvey@kimble.ie> wrote in message news:263cf391.0409130157.7676f3ed@posting.google.com... > Is there a way of adding a delay, i've also tried adding a delay into > a vhdl block but it is having no effect! Delay is not synthesizable, that's why it is not having any effect. Prevailing FPGA design philosophy today is that it has to be synchronous, i.e. everything that happens in the FPGA has to happen on a clock edge. Thus, having a clock is essential. Look at what kind of clocks you have in your design and see whether you can achieve what you need by pipelining your output signal. /MikhailArticle: 73069
Has anyone on here used the ML300 with the Gigabit ethernet (1000-SX) multimode connectors? If so, what PCI/PCI-X/PCI-E NICs have you used on the PC side? Thanks. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 73070
Hi, I want to learn to use the Xilinx Software and was wondering which one to download.. What is the difference between Xilinx Student Edition 4.2i and Xilinx webpack?? which is better to download??? and How are they and what do they offer?? I am new to this and would appreciate the help!!! Thank you. Kranthi.Article: 73071
All, As Peter would say, the teasing is over: V4 is ALIVE. http://www.xilinx.com for all of the details. Now I can finally talk about it. AustinArticle: 73072
Have you considered the EDK IP Import Wizard? I see that you are are not using the latest EDK service pack. There are more features in this area in EDK 6.2.2 EDK 6.3 should be coming out shortly, and I figure there will be more additions in there as well. Paul Mancini Stephane wrote: > > Hi, > Is anybody here tried to design it's own IP with a PLB master/slave ? > Is the PLB IPIF OK ? > How did you managed with the template ? > Indeed, My EDK version (Release Xilinx EDK 6.2 - platgen EDK_Gm.11) lacks > some of the templates wich are described in the "User Core Templates > Reference Guide". Does anybody could give me those templates ? > > Thanks a lot for your help > > StéphaneArticle: 73073
1. Have you positively check any free '51 cores for spartan/xilinx devices?? Ive tried some but have big problems with implementing. 2. Can you give me any links with examples - projects with spartan devices?? Not inside - i need some power suply method to see so protel or other. Greetings Thx in advance 5hinkaArticle: 73074
Judging from the behavior you are seeing, I would guess that5 you are
not connecting the Parallel Cable 4 to your PC correctly. The Parallel
Cable 3 just needs to be connected to the parallel port and then the
target device. The parallel Cable 4 needs to be connected to the
parallel port plus the keyboard connector (for power) and then the
target device. If the LED is NOT green on your 4 then you have not
powered it correctly.
senthil wrote:
> But for CPLD there may be a limit as
>
>>its technology is
>>based on flash/eeprom.
>
>
> Hi ,,
>
> i have one more doubts., ie., I used my parallel cable III , that
> detect my fpga say spartanII. also, i have parallel cable IV, i used
> this one to detect my fpga.. but it doesn't detect. I tried many
> times. But not possible. Is there any configuration to detect the fpga
> via parallel cable IV. r what is the diff between the parallel cable
> III & IV? Give me some suggestions..
>
> Regard
> Senthil.R
--
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z