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On Tue, 14 Sep 2004 11:08:35 +0200, "Rune Christensen" <rune.christensen@adslhome.dk> wrote: >Hello > >I'm looking for information about clock dividers. > >I need information about clock dividers that can divide an 100MHz clock with >for example 7812.50 (fixed point number) that gives an output of 12800Hz. Tell us more about your application. For example, is 7812.5 a fixed number, or will it be varied at "run" time or compile time? What precision do you need? Does the 7812.5 have to be exact, or is there some tolerance? How much jitter can you tolerate on the output? What range of duty cycles can you tolerate on the output? Whatever. The answer is probably going to involve a phase accumulator, and I'll probably end up directing you to this web site: http://fractional-divider.tripod.com/ Regards, AllanArticle: 73101
Rune Christensen wrote:
> Hello
>
> I'm looking for information about clock dividers.
>
> I need information about clock dividers that can divide an 100MHz clock with
> for example 7812.50 (fixed point number) that gives an output of 12800Hz.
>
> Thanks
> Rune Christensen
>
>
I have written a divide by 2.5 routine. You could use this followed by a
divide by 3125 to give 7812.5 that you require.
--- Divide by 2.5 counter ---
entity div2p5 is
port (
clk : in std_logic;
q : out std_logic);
end div2p5;
architecture div2p5_arch of div2p5 is
signal cnt0 : std_logic_vector (2 downto 0) := "000";
signal cnt1 : std_logic_vector (2 downto 0) := "000";
signal q0 : std_logic;
signal q1 : std_logic;
begin
q <= q0 and q1;
process (clk)
begin
if(clk'event and clk = '0')then
if(cnt1 = "000") then
q0 <= '1';
end if;
if(cnt1 = "100") then
cnt0 <= "000";
q0 <= '0';
else
cnt0 <= cnt1 + 1;
end if;
end if;
end process;
process (clk)
begin
if(clk'event and clk = '1')then
cnt1 <= cnt0;
if(cnt0 = "010")then
q1 <= '0';
elsif(cnt0 = "011")then
q1 <= '1';
end if;
end if;
end process;
end div2p5_arch;
----------------------------
Regards
Andrew
--
Spartan3 configuration JTAG download tool for GNU/Linux available from
http://www.rogerstech.co.uk/xc3sprog/
Article: 73102"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> skrev i en meddelelse news:kmddk09b2o4cvjn822m3ippeogh9duobin@4ax.com... > On Tue, 14 Sep 2004 11:08:35 +0200, "Rune Christensen" > <rune.christensen@adslhome.dk> wrote: > > >Hello > > > >I'm looking for information about clock dividers. > > > >I need information about clock dividers that can divide an 100MHz clock with > >for example 7812.50 (fixed point number) that gives an output of 12800Hz. > > Tell us more about your application. For example, is 7812.5 a fixed > number, or will it be varied at "run" time or compile time? > > What precision do you need? Does the 7812.5 have to be exact, or is > there some tolerance? > > How much jitter can you tolerate on the output? > > What range of duty cycles can you tolerate on the output? > > > > Whatever. The answer is probably going to involve a phase > accumulator, and I'll probably end up directing you to this web site: > http://fractional-divider.tripod.com/ > > Regards, > Allan 7812.5 will vary during run time because it will depend on the osc frequency nom. 100MHz The reference that I use is a PPS (pulse per second) signal that has a precision on +/- 50nsec A small jitter on 12800Hz +/- 1000 ppm is okay but a control loop should remove the jitter when measured over e.g. 1000 secs Regards Rune Christensen --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.760 / Virus Database: 509 - Release Date: 10-09-2004Article: 73103
Hello: I dont want to have a discussion about what is better, because is obvious that actually Verilog or VHDL are more mature HDLs and SystemC is a newbie. The thing I want to transmit is that systemC can be used for RT design with its current limitations. I say current because the SystemC Synthesis Working Group is working in improve the SystemC capabilities in order to make SystemC a RT solution as Verilog is. About your comments, I am agree in some of them because is obvious that tools have a Verilog input and doesnt support SystemC. This Verilog input is the reason to make a translation of the SystemC code, but I expect the EDA suppliers will add SystemC support in their products. But I am not agree in other things, for example when you said: > In addition to design, I also doubt that SystemC is a good choise for > the whole verification environment. For the system-level verification, > it is a good choise since it allows seamless interoperability with the > software. For the functional verification, verification-specific > languages (HVL)or SystemVerilog would be much better choise. > Functional verification requires advanced coverage, random generation, > assertion support as well as may other items such as random stability > etc. I doubt that SystemC has similar capabilities comparing to HVLs > or SV. One of the strongest features of SystemC is the verification capabilities. The SystemC Verification Library provides random generation, transaction recording and many other features. Assertion or advance coverage is not possible, the only thing you can do is a line coverage metric using GNU gcov program. But as I said I expect EDA vendors will supply a SystemC front end in their products. > 1. Translation problems. I am really suspicious about "complete > automatization" of language translation process. The problem is to > make it work in ALL the cases. The easiest way to cleanup translation > may be to reduce "translatable" subset in SystemC. It may not be a > problem, but then it reduces "synthesizable" subset of SystemC and > converts it to even more limited subset of synthesizable Verilog RTL. > 2. Descriptive power. > Verilog as a language was developed for RTL coding and constantly > improves during years of practice. For example, Verilog 2001 and then > SystemVerilog defines new useful constructs such as always_comb, > always_ff etc allowing designer to specify design intent in a way that > tools can verify. I doubt that SystemC has similar operator or can > produce them during code translation. We are talking about using SystemC as a RT language, and as a RT language you can do the same things you make in Verilog. Verilog and SystemC are different, and since they are different some things are described in a different way, for example assign statement in Verilog has to be translated into a combinational process in SystemC, but it can be translated. I think that all the Verilog RT subset has translation into SystemC. Regards Javier Castillo jcastillo@opensocdesign.com www.opensocdesign.comArticle: 73104
I need to delay one of the output signals from my cpld by 80nS. The clock frequency of our board is 48MHz. Im using the altera quartus software. We have data and address lines and a chip select going into the cpld. The outputs are open drain. When the data and address lines are changed from a Low to a High state they take about 60ns to rise up on the ouputs of the CPLD. The problem is the chip select line is active low and drops from a high to a low almost instantaneous. So things aren't lining up. I was able to move the chip select drop to a low by adding in LCELL's. This delayed the chip select until the data and address lines are set up on the outputs. The problem now is that the chip select line is now moved along and does not return high before the data and address lines change. i am trying to set the chip select back high after a set amount of time but the software does not seem to be registering the TIMING in the VHDL code. For example, in my open drain code i am trying to reset the output of the chip select high but it is not happening. temp <= A; process(temp) begin if temp = '1' then Y <= 'Z'; else Y <= '0', 'Z' after 800ns; end if; end process; end cont; i would b grateful for any help paulArticle: 73105
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes: > On 10 Sep 2004 11:00:43 +0200, Petter Gustad > <newsmailcomp5@gustad.com> wrote: > > >"apai" <arjunpai23@hotmail.com> writes: > > > > > >> I wanna generate EDIF netlist from Verilog code. I am using Xilinx > >> ISE6.2i software, and cannot find any trace of EDIF netlist > >> generated. > > > >I don't think XST can generate EDIF anymore. If you want EDIF you need > >to use a third party synthesis tool like DC-FPGA. > > XST produces a .ngc file, which can be converted to EDIF with > ngc2edif.exe. You can then convert the EDIF to a .ngd file using > edif2ngd.exe. As I said earlier, I think they have removed this functionality. In ISE 6.2i SP3 you get the following message if you try to run ngd2edif: "The ngd2edif program and generation of back-end EDIF netlist for simulation is no longer supported in the current software. Please use netgen program to generate Verilog or VHDL netlists for simulation." Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 73106
Austin Lesea <austin@xilinx.com> wrote in message news:<ci4p3r$imf1@cliff.xsj.xilinx.com>... > All, > > As Peter would say, the teasing is over: V4 is ALIVE. > > http://www.xilinx.com for all of the details. > > Now I can finally talk about it. Austin, How fast will the MicroBlaze run in the fastest speed grade? Cheers, JonBArticle: 73107
Hi, I think it's better that I answer that. MicroBlaze will run about 185 MHz in speedgrade -12. With the new architecture Virtex4, I will need to create a different aspect ratio on the RPM block since this architecture is smaller and higher. VII and V2Pro was more rectangular in the shape. With the new floorplan I achieves 165 MHz in -11 and this will give us around 185 MHz in -12. Göran Bilski Jon Beniston wrote: >Austin Lesea <austin@xilinx.com> wrote in message news:<ci4p3r$imf1@cliff.xsj.xilinx.com>... > > >>All, >> >>As Peter would say, the teasing is over: V4 is ALIVE. >> >>http://www.xilinx.com for all of the details. >> >>Now I can finally talk about it. >> >> > >Austin, > >How fast will the MicroBlaze run in the fastest speed grade? > >Cheers, >JonBArticle: 73108
hi, Can any one tell me how, i can compile my application in EDK for montavista linux... Regards, Mack.Article: 73109
Hi all, I have a board that has an XC2S300E-6PQ208 on it that gets hot after I configure it. Before the FPGA is configured, it stays cool. I have all the VCCO's tied to 3.3V and all the VCCINT's tied to 1.8 (I probed all of them). My design uses only 4 x LVTTL I/O's and the remainder of the I/O's are left unused. I have mucked around with the default I/O treatment with Bitgen switches (pullup / pulldown / float) but all seem to produce the same result. I tried a couple of different design images, all with the same pinout. The designs have a single clock that is _very_ low frequency and I am not using any DLLs. Any ideas of what I should look for? Thanks in advance for any suggestions. ChrisArticle: 73110
On 14 Sep 2004 03:37:01 -0700, agarvey@kimble.ie (Paul Gray) wrote: >i am trying to set the chip select back high after a set amount of >time but the software does not seem to be registering the TIMING in >the VHDL code. > >For example, in my open drain code i am trying to reset the output of >the chip select high but it is not happening. > >temp <= A; > >process(temp) >begin > if temp = '1' then > Y <= 'Z'; > else > Y <= '0', 'Z' after 800ns; > > end if; > >end process; > >end cont; > > >i would b grateful for any help >paul Hi Paul, From your question, I am guessing you are new to VHDL, new to CPLDs, and probably new to digital design. While you could be given a straight answer to your question, I think you would be better served with advice on what you should do to learn why you aren't getting the results you want. The first thing I would recommend is to read the data sheet for the CPLD, and in particular, the resources that the CPLD has. No matter what you write in VHDL, the chip only has a fixed number of specific resources. So if you write "after 800ns" you need to look at the CPLD resources, and see what it has that may be able to do this. If you can't find such a resource, then it is unlikely that the VHDL could somehow magically change what is available in the CPLD. Second, You should read some introductory text on VHDL, and in particular, note that it is really two languages. There is the full language that is designed for simulation, and there is a subset language, for synthesis. Since you are trying to create a design for a CPLD, you must restrict your self to the synthesis subset for the design part of your project. For the simuation part of your project, you can create a test bench wrapper that can use the full language. You will find that the synthesis subset does not support "after 800ns" Third, the use of open drain busses is highly unusual for address and data in current design practice (mini computers of 30 years ago did this for their backplane busses). Current designs typically use a tristate bus, that can actively drive high and low for the duration of a transaction, and thus you would not see the resitive pull up problems you are experiencing. Good luck, Philip =================== Philip Freidin philip.freidin@fpga-faq.com Host for WWW.FPGA-FAQ.COMArticle: 73111
> Vaughn, > > I gather then that to decrease this delay I would need to use the > output of a PLL to feed the above process statement sensitivty list? > If so, how could the PLL routing to the various flip flops be any > different then going from the input pad? Would there be that much of a > difference? Incidentally, this significantly dampers the overall > speed at which the state-machine can operate. > > Cheers, > Pino Hi Pino, If you're worried about the state machine delays you see in simulation, and you plan to use this on-chip (i.e. you're not sending the signals off chip in the final design) then add a register between each of your outputs and the top-level design output. Then the outputs you are monitoring will be on-chip, rather than off-chip, signals, and will have shorter delays. Alternatively you could go to the Quartus node finder and find the name of the register output that is driving out1, and monitor that (again, it will be faster since it is before the output pad, which is your slowest part). The delay of the output pad should not be limiting the speed of your state machine, although it would impact any downstream chip that was receiving this data. What does Quartus report as a maximum clock frequency for this clock domain? To get the best performance, make sure you have set a timing constraint on this clock, and that it is for a high speed. As for a PLL decreasing the delay to the register inputs, that is done by generating a clock that is frequency matched to the input, but earlier in time. So a PLL does not decrease the routing delays; it shifts the clock in time to cancel out the routing delays. Hope this helps, Vaughn AlteraArticle: 73112
Hi Austin, As I shake my head in wonderment reading your post, I think to myself (and not for the first time :-) "Self, isn't it great that all the really crazy clients end up in Austin's bucket" On Sat, 11 Sep 2004 03:00:29 -0400, "Austin Franklin" <austin@dark99room.com> wrote: >I need some help with something. Someone made some technical claims that I >am questioning are correct or not ;-), and would like to see what you guys >think about these claims: > >#1> Programming FPGAs doesn't actually change or rewire those logic gates >#1> in the silicon wafer. It changes bits of non-volatile memory that is >#1> used as inputs to these gates. (These are not the gates you see when >#1> you write the FPGA code, those are emulated by a combination of >#1> hardwired gates and your code.) Depending on vendor, the memory that is changed may be volatile or non-volatile. By far, the volatile memory devices are the dominant products in use. A & X. Since the devices are volatile, and infinitely re-programmable, just like a CPU, no physical modification of the internal wires occurs. But, for the non-volatile devices that use anti-fuse, the interconnect intersections are physically changed, and I think you might describe it as "wiring" , not "rewiring" since the initial state is nothing conected to nothing. >#2>Software is defined as the part of a digital circuit that can be >#2>changed without mechanical modifications, as opposed to hardware, >#2>which is HARDwired. So FPGA code is software Absolute B.S. Hardware: Case, PSU, PCB, ALL components on the PCB, disk drives, terminals resistors, caps, diodes, transistors, wires, connectors, switches, CPU chips, modems, FPGAs, CPLDs, etc, etc, etc. Software: Fortran, COBOL, Assembler, BASIC (All forms), C, C++, Python, Perl, TCL/TK, ...... The compiled or interpreted version of the above list when loaded into memory (typically volatile) on a processor. Firmware: Software that is loaded into non-volatile memory. Specifications: (in your head, in a file on disk, printed on paper, punched on punch cards, punched on paper tape, On magnetic tape........) Any description of the hardware, including: Schematics, VHDL, Verilog, PAL eqn, AHDL, CUPL, ..... Any description of the software that is not the actual software >#3> OTP EPROM data ... has always been regarded as software. B.S. i.e. character map for a CRT. >#4> A LUT is not a device soldered onto the circuit board. It's not even >#4> implemented in silicon (at least during the development stages). Last time I designed an FPGA (and I do mean "designed", not "designed with") it sure had a lot of real LUTS being implemented in silicon. >#4> It's programmed into an FPGA or suchlike and therefore software because you >#4> can change it without any mechanical changes on the board. Total B.S. What if the FPGA config stream is in a ROM. If I need to make a change, out comes the soldering iron. What if I am insane and chose to use an anti fuse part. Need a soldering iron to make changes here too. >#5> Using a sufficiently parallelized, a LUT done in a DSP can be just as >#5> efficient as using an FPGA or ASIC. B.S. Todays FPGA LUTs are sub 1.0 ns. A DSP needs to fetch an instruction, decode it, figure out it is indexing memory, go fetch, etc, etc, etc. >"And none of the professionals I've talked to referred to ASICs being >hardware. You can't buy an ASIC, you have to design it, which makes >its function software." He couldn't have looked very far, since he hasn't talked to me about reality. Please do not give him my name. You should handle this. >Any input appreciated ;-) Enjoy your argument :-) Philip Philip Freidin For the US news media, there is nothing so important or relevant, that it can't be ignored in favor of some new, bright and shiny irrelevancy.Article: 73113
Thanks a lot, Yes but my version allow me only to have PLB slave. What I'm wondering is if the IPIF PLB master is OK despite the fact that the EDK IP Import Wizard doesn't have the feature. The problem is that it will be long until we have the new version... Can I use the IPIF PLB master with EDK 6.2 with no problem ? I can hack the slave only version to use a master but it would be easier if someone could give me a VHDL wrapper with a single master. Thanks a lot for your help. Stephane On Mon, 13 Sep 2004 11:44:15 -0700, Paul Hartke wrote: > Have you considered the EDK IP Import Wizard? > > I see that you are are not using the latest EDK service pack. There are > more features in this area in EDK 6.2.2 > > EDK 6.3 should be coming out shortly, and I figure there will be more > additions in there as well. > > Paul >Article: 73114
Jim, Here we go, (below) Austin Jim Granville wrote: > Austin Lesea wrote: > >> Jim, >> >> Thanks for the encouragement, >> >> (long-winded, who me?) > > > You're welcome :) > > To give you a chance to wind up on Virtex-4, here are a > couple of questions : > > Virtex-4 does not seem to be supported in WebPACK > - when is this planned ? Don't know. I am not in the software world at all, so maybe someone else can answer. > > Virtex-4 seems only available in large, BGA packages. Yes, V4 is a flip chip only device due to the ASMBL architecture (no wirebond packages possible). Flip chip does offer real advantages in the SI realm, as the advanced packaging used in V4 has 1/3 to 1/4 the inductance of any other competitive FPGA packaging to date, which will lead to much less ground bounce LdI/dt (SparseChevron-tm power and ground pins are always within 2-3 pins of an IO pin leading to far better SI). Since almost all problems with the most advanced FPGAs have to do with SI (signal integrity engineering on the part of the customer) we decided that we would do what we could to make their job easier. The triple oxide allows us to keep the advantages of the low leakage memory cells for config at 130 nm (and soft error resistance), without any penalty for speed. Using three different oxide thicknesses, and low Vt and high Vt transistors means that an IC designer's choices are much better when it comes to designing for speed, and power. No one else has this triple oxide process, and those that have 100% 90 nm core may have issues with thermal runaway due to leakage, as well as serious power issues. But when customers crank the clock up to 500 MHz, and run all that stuff, even at 40% less dynamic power than V2P, there is 2X the logic per area, so that BGA package is needed to get the heat out! (higher clock rate + more logic in the same space = more heat -- nothing is free). When > do we expect to see Spartan-4? GSD (Spartan) is their own division now, with their own set of customers (set top boxes, big screen TV's, automobiles, etc.) and their needs are quite different. I suspect that Spartan [n+1] devices will look less and less like the APD (Virtex) division devices due to the customer needs. Spartan is all about gates/$ and IO/$. The more, the better. MHz/ns/speed is almost ignored, as long as the devices meet the bare minimum that folks seem to want. There are also issue of low power in these markets, although V4 is 40% less power than V2P for fabric, and 1 mW/100 MHz for the DSP48 MAC blocks (measured on a full FFT from a column of DSP48's), which puts in the best in the world class, as no one is building 90nm DSPs (yet), let alone with kind of performance. The 405PPC core was a low power version for V2P that was redesigned for V4, so it too is extremely low power. I think that V4 is the lowest power part around right now. Spartan plans to catch up, and beat it, however. in TQFP and anything < 360 pins ?. In fact, puting a V4 in a wire bond package (even if it was possible, which it is not) would be like putting a 700 hp V12 in a Austin Mini Cooper: if would fly apart. Sorry, if you want all that performance, it will only come in the package that can handle it. > > Xilinx has a nice Spartan-3 Eval PCB for $99, what is the > Virtex-4 EvalPCB status ? ( $99 ? :) Unknown. Sampling of LX25's is open immediately, with stock. Other parts to follow shortly after I get done verifying and characterizing them (which is pretty easy after we've done the LX25). There is a network board demo'ing 1 GB/s network interfaces, etc with automatic per bit deskew (now built into every IOB). There is a memory interfaces demo board also which shows the superiority of all of the memory interfaces in speed and ease of use. Contact your local FAE or disti. And, there are tons of other boards folks are doing as well, that I do not know about. > > -jg >Article: 73115
Adam, And how do you propose to read out the bits from the key memory? Austin Adam Megacz wrote: > Hey Nick, 441 Soda Hall just isn't the same without you.... =( > > >>Thus you have the encrypted bitfile loading on the Virtex lines. > > > Well, IMHO it doesn't qualify as encryption when the chip itself -- > which you're giving to your customers -- contains the decryption key. > > >>Personally, I think the V4 version is easily good enough for >>protecting a $10,000 secret, and I could probably be OK comfort wise >>protecting a $100,000 secret. > > > $10k (loaded cost) will buy you about half a month of a mediocre > hardware engineer's time. I doubt many of Xilinx's customers' designs > are that simple. Even <$100k designs probably constitutes an > unimportant fraction of their market. > > But I agree with your estimate. I could envision the task of > extracting the decryption key from a Xilinx part as being a feasible > project with around $300k of funding and the right team to pull it > off. > > So, basically, I wouldn't trust the security of any serious commercial > design to Xilinx's obfuscation. Now lawyers, on the other hand... =) > > - aArticle: 73116
The max bus frequencies are determined by the amount of logic you have in your design. For example, the EDK reference design for the ML300 board where a 2VP7 is pretty much filled up with peripherals runs PLB and OPB at 100MHz. There is no minimum frequency. - Peter Navya wrote: > Hi, > > Can anyone explain me at what maximum frequency does the OPB,PLB > and DCR bus operates in a vitex2p based powerpc's.Any idea which is > slowest and which is fastest? > > Regards, > NavyaArticle: 73117
Mack, please see application note XAPP765 on how to get started with EDK and MontaVista Linux: http://direct.xilinx.com/bvdocs/appnotes/xapp765.pdf - Peter mack wrote: > hi, > Can any one tell me how, i can compile my application in EDK for > montavista linux... > > Regards, > Mack.Article: 73118
Chris Alexander wrote: > Hi all, I have a board that has an XC2S300E-6PQ208 on it that gets hot > after I configure it. Before the FPGA is configured, it stays cool. > I have all the VCCO's tied to 3.3V and all the VCCINT's tied to 1.8 (I > probed all of them). > > My design uses only 4 x LVTTL I/O's and the remainder of the I/O's are > left unused. I have mucked around with the default I/O treatment with > Bitgen switches (pullup / pulldown / float) but all seem to produce > the same result. > > I tried a couple of different design images, all with the same pinout. > The designs have a single clock that is _very_ low frequency and I am > not using any DLLs. > > Any ideas of what I should look for? Thanks in advance for any > suggestions. > > Chris Do you have tri-state logic description inside your FPGA code. If you have the RTL schematic of the FPGA find 'TBUF'? Larry www.amontec.comArticle: 73119
"Robert Sefton" <rsefton@abc.net> wrote in message news:2qn4qtF111ef9U1@uni-berlin.de... > Can someone explain this to me? > > Here's the LVTTL I/O timing for Virtex-2 -4 and Spartan-3 -4 (Fast 12mA > drive for the outputs): > > Virtex-2 Spartan-3 > -------- ---------- > TIOPI 0.88ns 2.15ns (pad to IOB .I output) > TIOOP 1.74ns 0.48ns (IOB ,O input to pad) > > According to these numbers the Spartan-3 input buffer got 1.27ns slower and > the output buffer got 1.26ns faster. Is this possible? > > I have a Virtex-2 1000 design that fits perfectly in a Spartan-3 1000, but I > just routed it and got a ton of input path timing errors. So much for saving > $125 per chip with S3. > > Thanks, > Rob > (email is bogus, please reply to group) I don't have your answer but I have a suggestion: consider using a DCM to move the clock up by about 1.25 ns. If your clock is continuous, you can match the input and output timing to your original design.Article: 73120
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:ci521a$va$1@gnus01.u.washington.edu... > > > Austin Franklin wrote: > > > I need some help with something. Someone made some technical > > claims that I am questioning are correct or not ;-), > > and would like to see what you guys think about these claims: > A while back I was deposed for a patent infringement law suit. The oppositions lawyer were trying to prove that my "hardware search engine" built in an FPGA was really a "software search engine" because anything in an FPGA was really software. Don't know how that one turned out as I'm no longer with that company, but: Lawyers - ya gotta love em!Article: 73121
On 14 Sep 2004 07:04:47 -0700, info@bostonsemiconductor.com (Chris Alexander) wrote: >Hi all, I have a board that has an XC2S300E-6PQ208 on it that gets hot >after I configure it. Before the FPGA is configured, it stays cool. >I have all the VCCO's tied to 3.3V and all the VCCINT's tied to 1.8 (I >probed all of them). > >My design uses only 4 x LVTTL I/O's and the remainder of the I/O's are >left unused. I have mucked around with the default I/O treatment with >Bitgen switches (pullup / pulldown / float) but all seem to produce >the same result. > >I tried a couple of different design images, all with the same pinout. > The designs have a single clock that is _very_ low frequency and I am >not using any DLLs. > >Any ideas of what I should look for? Thanks in advance for any >suggestions. It certainly sounds like contention in I/O pins. Create a new design, with just one input connected to one output. Unspecified pins default to inputs with light pull up. See if that gets hot. Create more designs with more and more of the pins you think are outputs, and set them to their expected idle level (high or low). Keep doing designs, adding pins till it gets hot. Let us know how it works out. >Chris Philip Freidin FliptronicsArticle: 73122
"John_H" <johnhandwork@mail.com> wrote in message news:wnE1d.2$l1.691@news-west.eli.net... > > I don't have your answer but I have a suggestion: consider using a DCM to > move the clock up by about 1.25 ns. If your clock is continuous, you can > match the input and output timing to your original design. > True, if you can use the DCM. Not always an option. I'm just trying to understand the physics of the timing differences. Just doesn't make sense to me. RobArticle: 73123
Adding 800ns is quite heavy, possibly done with a counter 800ns/ 20ns period after which the signal is asserted. The same can be done for 80ns (only 4 periods). The compilers are usually intelligent when it comes to optimizing. You add more time wasting gates and it removes it to increase speed. The one option is to route a signal to a pin and back through another but that is usually ineffective and ugly, and ony adds a few ns to the signal. My suggestion is to create a small counter and count 4 x 20ns periods for 80ns (or 40 x 20ns periods for 800ns) before asserting the signal. At these slow speeds you can also consider a simple state machine to handle the I/O. Victor Schutte victor@zertec.co.za http://www.zertec.co.za "Paul Gray" <agarvey@kimble.ie> wrote in message news:263cf391.0409140237.5b966c4e@posting.google.com... > I need to delay one of the output signals from my cpld by 80nS. > The clock frequency of our board is 48MHz. > > Im using the altera quartus software. > > We have data and address lines and a chip select going into the cpld. > The outputs are open drain. When the data and address lines are > changed from a Low to a High state they take about 60ns to rise up on > the ouputs of the CPLD. > > The problem is the chip select line is active low and drops from a > high to a low almost instantaneous. So things aren't lining up. > > I was able to move the chip select drop to a low by adding in LCELL's. > This delayed the chip select until the data and address lines are set > up on the outputs. > > The problem now is that the chip select line is now moved along and > does not return high before the data and address lines change. > > i am trying to set the chip select back high after a set amount of > time but the software does not seem to be registering the TIMING in > the VHDL code. > > For example, in my open drain code i am trying to reset the output of > the chip select high but it is not happening. > > temp <= A; > > process(temp) > begin > if temp = '1' then > Y <= 'Z'; > else > Y <= '0', 'Z' after 800ns; > > end if; > > end process; > > end cont; > > > i would b grateful for any help > paulArticle: 73124
Hi, I'm thinking about ERSA IR 500/550 A, Universal BGA/MST Rework systems. Does anybody have an idea about the price of these systems? How good are they for modern FPGA boards assembly? Are there any better, low-cost systems out there? What has been your experience with such systems, especially comparing to outsourcing the assembly of BGAs for sample quantities? Best Regards Arash
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