Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
hol wrote: > One of our customers will be asking us to > implement a bunch of math functions on an FPGA-boards. > There are a lot of "decisions" that affect control > processing/algorithm selection, so they specifically > requested an FPGA with "PowerPC." (This immediately > tells me Xilinx's marketing has done an A+ job of getting > managers and other non-technical people to subconsciously > associate 'FPGA CPU' with Xilinx's Virtex2Pro product. :)) Just get a board with the VirtexIIPro on it, and try to use it. It is not difficult at all. I had the VirtexIIPro Eval Board from Avnet, and I was pretty happy with it. It is less then $1000, and includes the boards, linux and EDK, so if you have a working linux box, you can start in few minutes compiling your own kernels. BTW, if you don't like (I have no idea why you wouldn't, but) the PowerPC core, you can still use the microblaze on the same chip. just my .0000002Article: 73651
ok apologising on comp.arch.fpga is good sign too, BUT if I am looking for ISE update I will look primarly on www.xilinx.com not start with searching on comp.arch.fpga comp.arch.fpga is not for xilinx only - first information about xilinx solution is still expected to be available on xilinx website IMHO antti "Symon" <symon_brewer@hotmail.com> wrote in message news:2rppmsF1clvh7U1@uni-berlin.de... > Ah, but Steve Lass posted and apologised on comp.arch.fpga about it. Check > out the thread entitled "Webpack 6.3 and Spartan3-1000/1500". > Cheers, Syms. > > "Antti Lukats" <antti@case2000.com> wrote in message > news:cj74jc$le8$00$1@news.t-online.com... > >> : So as the things stand today: since ISE 6.3 free webpack is no longer > >> : available, not from web download not as CDROM (20USD shipping charges > >> : apply). I dont mind the 20USD and I dont need the Webpack either, but I > > also > >> : dont like people being fooled around with incorrect information. > >> > >> The 6.3 Webpack had problems and was withdrawn. Expect a corrected > >> version > > soon. > > > > thanks! > > I wonder why that information is not available from Xilinx!! > > Antti > > > > > >Article: 73652
Isn't this a rather clumsy piece of code? Isn't there a way to use a few simple lines to infer a block ram (that is not written) and then init the contents separately? It is not often that I want to hard code my ROM contents. Subroto Datta wrote: > > Hello Sebastian, > You have a pointed out an error in the handbook which will be > corrected. The piece of code that will infer a ROM in Quartus (used > 4.1) is shown below: > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > ENTITY sync_rom IS > PORT ( > clock: IN STD-LOGIC; > address: IN STD_LOGIC_VECTOR(7 downto 0); > data_out: OUT STD_LOGIC_VECTOR(5 downto 0) > ); > END sync_rom; > > > > ARCHITECTURE rtl OF sync_rom IS > BEGIN > PROCESS (clock) > BEGIN > IF rising_edge(clock) THEN > CASE address IS > WHEN "00000000" => data_out <= "101111"; > WHEN "00000001" => data_out <= "110110"; > ... > > WHEN "11111110" => data_out <= "000001"; > WHEN "11111111" => data_out <= "101010"; > WHEN OTHERS => data_out <= "101111"; > END CASE; > END IF; > END PROCESS; > > END rtl; > > > Hope this helps, > > Subroto Datta > Altera Corp. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73653
glen herrmannsfeldt wrote: > > rickman wrote: > (snip about ROMs in FPGA's) > > > I'm not sure I follow this, but in an FPGA a ROM is nothing but a RAM > > that is never written. You can infer them the same way as a RAM, just > > don't use a write signal and input data. They can be initialized in > > different ways. I find it most useful to init the data *after* > > compliation and routing of the design. Both Xilinx and Altera support > > this. > > Quartus II for me, if I have a design with RAM in it, such > as a FIFO has a warning that I haven't provided initialization > data for the RAM. I believe it takes the old intel hex format, > and maybe others. > > Are you using the BRAM's or LUT's for your ROM? I am talking about block rams. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73654
hol wrote: > > One of our customers will be asking us to > implement a bunch of math functions on an FPGA-boards. > There are a lot of "decisions" that affect control > processing/algorithm selection, so they specifically > requested an FPGA with "PowerPC." (This immediately > tells me Xilinx's marketing has done an A+ job of getting > managers and other non-technical people to subconsciously > associate 'FPGA CPU' with Xilinx's Virtex2Pro product. :)) > > As an engineer, for me, the problem isn't the choice of > CPU; Any embedded CPU (OpenRISC, Microblaze, > Nios, etc.) would serve the purpose; as its only going > to read/write internal status/contorl registers > every few 10,000 cycles. The problem is 'how to run > the software app' on the CPU. > > Now for my awkward question. I've never done this kind of > 'embedded' development before, so I have no clue as to > the normal development flow. > > In digging around a few enthusiast websites, I think I > the normal flow requires > a) 'embedded O/S' (running on the embedded CPU target) > b) development tools (C-compiler to target the CPU) > c) your own custom files (for defining I/O ports, > application hardware, etc.) > > It sounds all very complicated to me. Can I "skip" the > embedded O/S? I'm just read/writing some registers, not > trying to access a TCP/IP network or USB-filesystem. > > I'm an ASIC engineer (mostly RTL Verilog coder) by training, > so I know my way around hardware development. > > So, what do you guys recommend to the novice embedded engineer? > Is the Xilinx EDK a good choice? What about the 'OpenRISC' > CPU on opencores.org? Now that everyone else has given you their opinion, let me offer mine. This is just the sort of app where I would seriously consider Forth. You may not need an OS, but an OS can often help ease any IO and scheduling you may end up performing. Forth is a language which also includes the basic functions of an OS. It also provides basic debug features. You can easily do your full development without ever needing an emulator. One other feature is that a Forth kernal can include the full compiler. So you can boot into an embedded app, or you can boot the kernal and quickly compile the app at startup. Then updates can be done at a source level! But the best part is that a full Forth kernal can be well under 64 KB, even as small as 16 KB! Try that with Linux!!! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73655
...or, if you're using ModelSIM (say), you can map the virtex2 library to the UNISIM one. But Ken's solution is better... Cheers, Syms. "Ken McElvain" <ken@synplicity.com> wrote in message news:GwV5d.11117$NC6.495@newsread1.mlpsca01.us.to.verio.net... > Use the unisim library instead. > > library unisim; > use unisim.vcomponents.all; > > the "virtex2.components" package is only > there for compatability with old projects. > > - Ken > > > van de Kerkhof wrote: > > > Hi, > > > > How do I get this library trough compilation. When I include this in my vhdl > > it gives an error with compilation. > > If I leave it out synplify giveas an error with synthesis. And I don't like > > to manual add this to the vhdl every thime. > > > > Bram > > > > >Article: 73656
"Channing_W" <channing@pldsupport.com> wrote in message news:cj9a7q$7vc$1@mail.cn99.com... > Steven, > > As your mention, "If the power supply doesn't have enough capacity, then the > FPGA may fail to configure.". Does it effect in only the master serial mode > or all configuration mode include JTAG mode? > The limitation is if ... * The VCCO supply ramps faster than the minimum data sheet specification (Tcco) and * The VCCO supply does not have excess current capacity then the FPGA may fail to configure. If the supply ramps slower than the specified Tcco, then no problem. If the supply does ramp faster than Tcco, then the problem could potentially occur regardless of the configuration mode. Just FYI, the Tcco specifications have already been improved to "No Limit" for the XC3S50 and XC3S1000. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC [snip] > > > > If the 2.5V, 300 us ramp is on the VCCAUX supply only, then no problem. > > However, if one of the VCCO_# supplies also connects to the 2.5V supply, > > then yes, the design violates the current Tcco specification in the > > Spartan-3 data sheet (Table 3 of the Spartan-3 data sheet, page 3). > > http://www.xilinx.com/bvdocs/publications/ds099-3.pdf > > > > The Tcco specification for the XC3S200 in the FT256 package is 600 us (0.6 > > ms). That's a worst-case value. Most devices, but not all under > worst-case > > conditions, should function with a 300 us ramp rate. Your prototype > design > > should be fine, although Xilinx does not guarantee it with a 300 us ramp > > rate. Can you ignore it for your production design? Not if you want > > guaranteed success for every board. > > > > So what happens if you violate the specification? In the XC3S200, you > could > > potentially trigger the aggressive ESD protection circuit. You will see > > additional current draw, but only if the VCCO ramps too fast. If the > power > > supply doesn't have enough capacity, then the FPGA may fail to configure. > > If the supply does have enough capacity, then the FPGA will configure, but > > may still draw current. If the VCCO supply ramps slower than the Tcco > > specification, then you will never see this condition. > > > > The overly aggressive ESD circuit is tamed in the XC3S50 and XC3S1000 > FPGAs > > available today. There is no ramp limit for these devices. If the > > ramp-rate is a concern in your design, the XC3S1000 is also available in a > > pin-compatible FT256 package. > > --------------------------------- > > Steven K. Knapp > > Applications Manager, Xilinx Inc. > > General Products Division > > Spartan-3/II/IIE FPGAs > > http://www.xilinx.com/spartan3 > > --------------------------------- > > Spartan-3: Make it Your ASIC > > > > > >Article: 73657
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:10lec6t8eabsua1@corp.supernews.com... > I often get Xilinx error messages saying that I can't read a pin that is > configured "out mode" (or something like that). Up to now, to get around > the error, I have been mirroring such a pin with an internal register and > reading the output of the register instead. Recently I find that making > such a pin an inout instead of an out will also let it be read. That's > reasonable but seems contrary to what I believe that an inout pin is a > bidirectional pin. What is the best way to do this, as a matter of style? > > b r a d @ a i v i s i o n . c o m > > For some reason VHDL won't let you read a mode "out" pin, just one of VHDL's quirks I guess - Verilog doesn't seem to have this problem. And, no you don't want to change the pin to an inout because then you are reading the signal on the wrong side of the I/O buffer. Just use a buffer to connect the internally generated signal to the output pin. Then you can read the internally generated signal as much as you want, and the Xilinx optimizing software will throw the buffer out when it optimizes the design. DanArticle: 73658
Since you have specifically been asking about embedded Linux on the embedded PPC processor in Virtex-II Pro and Virtex-4 I recommend you to read application note 765 that explains how to get started with EDK and Linux. As additional reading I recommend the application note on UltraController that is kind of the other extreme of running a full-fledged operating system. UltraController is tiny and might be sufficient for your application. http://direct.xilinx.com/bvdocs/appnotes/xapp765.pdf http://www.xilinx.com/bvdocs/appnotes/xapp672.pdf - Peter hol wrote: > One of our customers will be asking us to > implement a bunch of math functions on an FPGA-boards. > There are a lot of "decisions" that affect control > processing/algorithm selection, so they specifically > requested an FPGA with "PowerPC." (This immediately > tells me Xilinx's marketing has done an A+ job of getting > managers and other non-technical people to subconsciously > associate 'FPGA CPU' with Xilinx's Virtex2Pro product. :)) > > As an engineer, for me, the problem isn't the choice of > CPU; Any embedded CPU (OpenRISC, Microblaze, > Nios, etc.) would serve the purpose; as its only going > to read/write internal status/contorl registers > every few 10,000 cycles. The problem is 'how to run > the software app' on the CPU. > > Now for my awkward question. I've never done this kind of > 'embedded' development before, so I have no clue as to > the normal development flow. > > In digging around a few enthusiast websites, I think I > the normal flow requires > a) 'embedded O/S' (running on the embedded CPU target) > b) development tools (C-compiler to target the CPU) > c) your own custom files (for defining I/O ports, > application hardware, etc.) > > It sounds all very complicated to me. Can I "skip" the > embedded O/S? I'm just read/writing some registers, not > trying to access a TCP/IP network or USB-filesystem. > > I'm an ASIC engineer (mostly RTL Verilog coder) by training, > so I know my way around hardware development. > > So, what do you guys recommend to the novice embedded engineer? > Is the Xilinx EDK a good choice? What about the 'OpenRISC' > CPU on opencores.org?Article: 73659
"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:<zTQ4d.307654$vG5.228612@news.chello.at>... > Some SRAMS need a data hold after rising edge of nwe. Your > timing between data out and nwe depends on the routing. If you pack the output flip flops into IOBs the timing is very well defined. > To not waste an > additional clock cycle on write I've used a neg-edge triggered FF for the > nwe signal. Or with spartan-3 use a second clock that is a few nanoseconds earlier compared to the global clock to output the WE. Kolja SulimmaArticle: 73660
Ben,
Since you are pointing to a 32-bit value (int), incrementing a pointer
to this a value of this type will add the sizeof(int) to the address.
Since MicroBlaze addresses are on byte boundaries, the address will be
incremented by 4 (32 bits = 4 bytes).
To increase your address by 1 byte, change the type of the variable you
are pointing to to a char, which has sizeof(char) = 1 byte.
Matt
Ben G wrote:
> I have an EDK design with a MicroBlaze processor and use the External
> Memory Controller (EMC) to get access to off-chip SRAM.
>
> I access the SRAM from c using a pointer and have a loop in my program
> that writes a value and increments the pointer to the next address.
>
> As I am using a pointer to type integer it is increased by 4 locations
> each time I increment it. The SRAM I am accessing however is 32 bits
> wide so I am not getting access to the full memory capacity. Is there a
> setting somewhere for the compiler to tell it to increase by 1 address
> location or am I using the wrong approach.
>
> I am a beginner with this technology so apologies if this is a dumb
> question.
>
> >>>>
>
> int *sram_addr_data;
> int i;
>
> sram_addr_data=(int *) XPAR_SRAM0_MEM0_BASEADDR;
> for(i=0;i<NUM_LOOP;i++)
> {
> *sram_addr_data = i;
> sram_addr_data++;
> }
>
> >>>>
Article: 73661>> To not waste an >> additional clock cycle on write I've used a neg-edge triggered FF for the >> nwe signal. > >Or with spartan-3 use a second clock that is a few nanoseconds earlier >compared to the global clock to output the WE. That fixes the trailing edge problems (hold times), but it might break the other/leading edge, the setup times. I haven't checked the details on any data sheets lately. Most older SRAMs had 0 setup and 0 hold (maybe worse) for WE so just moving the WE pulse didn't solve the problem, just pushed it to someplace else. What particular SRAM is on the board that started this thread? Can the DDR logic be used to generate a 1/2 clock pulse? That would work with a slightly advanced clock. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 73662
I am moving onto Verilog now from VHDL due to it being too complicated for me to start off with and not having any calsses available to go to in order to teach me it. So far Ive been just trying to make a simple counter that would pulse an led every second, and so far no luck. Im getting errors left and right, when I change one thing, I get another error, and when I fix that I seem to get others. I have no idea what Im doing wrong, everyhting looks like it would run fine from what Ive read. So if you can let me know what my errors are. Thank you!
CODE:
module pulse(led_o, clk50);
input clk50;
output led_o;
reg [15:0] c;
always @(posedge clk50) //Trigger on 50MHz clock
begin
if (c == 50000000) //Convert 50MHz Clock to 1Hz <= 0; led_o <= 1; //Turn led on
wait (50ms) //wait 50ms
led_o <= 0; //turn led off
else
c <= c + 1; //Step up c +1
end
endmodule
ERRORS:
ERROR:HDLCompilers:26 - clock.v line 12 unexpected token: '50'
ERROR:HDLCompilers:26 - clock.v line 15 expecting 'end', found 'else'
ERROR:HDLCompilers:26 - clock.v line 16 unexpected token: '<='
ERROR:HDLCompilers:26 - clock.v line 16 unexpected token: '+'
ERROR:HDLCompilers:26 - clock.v line 16 expecting 'endmodule', found '1'
ERROR: XST failed
Ive been useing this as a reference: <http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html>
I suppose it isnt very good considering how far it has gotten me. If anyone else knows of a good online resource just to look up little things like wait, if, begin type stuff with proper sytax let me know!
Thanks!
-Weizbox
Article: 73663It's a while since I did any Verilog, so I'm not gonna fix your syntax, but I don't think wait(50ms) is synthesisable. Also, a sixteen bit register isn't big enough to count to 5e7. You might like to try comp.lang.verilog ? Cheers, Syms. <Weizbox> wrote in message news:ee89141.-1@webx.sUN8CHnE... > I am moving onto Verilog now from VHDL due to it being too complicated for me to start off with and not having any calsses available to go to in order to teach me it. So far Ive been just trying to make a simple counter that would pulse an led every second, and so far no luck. Im getting errors left and right, when I change one thing, I get another error, and when I fix that I seem to get others. I have no idea what Im doing wrong, everyhting looks like it would run fine from what Ive read. So if you can let me know what my errors are. Thank you! > > CODE: > > module pulse(led_o, clk50); > > input clk50; > output led_o; > reg [15:0] c; > > always @(posedge clk50) //Trigger on 50MHz clock > begin > if (c == 50000000) //Convert 50MHz Clock to 1Hz <= 0; led_o <= 1; //Turn led on > wait (50ms) //wait 50ms > led_o <= 0; //turn led off > > else > c <= c + 1; //Step up c +1 > end > > endmodule > > ERRORS: > > ERROR:HDLCompilers:26 - clock.v line 12 unexpected token: '50' > ERROR:HDLCompilers:26 - clock.v line 15 expecting 'end', found 'else' > ERROR:HDLCompilers:26 - clock.v line 16 unexpected token: '<=' > ERROR:HDLCompilers:26 - clock.v line 16 unexpected token: '+' > ERROR:HDLCompilers:26 - clock.v line 16 expecting 'endmodule', found '1' > ERROR: XST failed > > Ive been useing this as a reference: <http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html> > > I suppose it isnt very good considering how far it has gotten me. If anyone else knows of a good online resource just to look up little things like wait, if, begin type stuff with proper sytax let me know! > > Thanks! > -WeizboxArticle: 73664
Thanks! Im really new to this and a lot of differnt sites dont make things all that clear so its hard to tell whats right and whats wrong. The sixteen bit was an oversight :-/ Thanks for the input tho.. Ill try the group as well!Article: 73665
jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0409221210.42177261@posting.google.com>... > Hi, > > When targeting the Cyclone II, the NIOS II/f configuration in SOPC > builder doesn't seem to list support for either multipler, > barrel-shifter or divide. Support for these only seems to be available > when the target is a Stratix device. Is this correct? Is it not > possible to get h/w multiply support on the Cyclone II? > > I'm using the eval version of NIOS II. > > Cheers, > Jon Hi Jon, The HW multipliers in Cyclone II will absolutely be supported. Just stay tuned for the next Nios II release. Jesse Kempa Altera Corp.Article: 73666
meng.engineering@bluewin.ch (Markus Meng) wrote in message news:<aaaee51b.0409221149.73b65bf3@posting.google.com>... > Hi all, > > I just wonder if someone in the US could comit the following: > > ALTERA will bring out an update for its SOPC set featuring the > MMU and optional a FPU for the NIOS-II system. > > These enhancements shall be availabel this year? > > This would make it possible to run standard > unix like Linux (MMU required) ... > > Best Regards > Markus Hi Markus, I cannot comment on specifics of future releases, but please watch for official press releases concerning Nios II - they will let everyone know about new features - stay tuned :) Jesse Kempa Altera Corp.Article: 73667
In article <ee89141.-1@webx.sUN8CHnE>, Weizbox <> wrote: > >module pulse(led_o, clk50); > >input clk50; >output led_o; > reg [15:0] c; make that big enough to hold 50000000, at least 26 bits. make an output register reg led; assign led_o = led; >always @(posedge clk50) //Trigger on 50MHz clock > begin > if (c == 50000000) //Convert 50MHz Clock to 1Hz <= 0; led_o <= 1; c <= 0; // reset counter led <= ~led; // toggle led > >else > c <= c + 1; //Step up c +1 > end > >endmodule Offhand I think that will do what you want. With clock driven logic you can't just 'wait', you have to maintain some sort of state (in this case just whether the LED is off or on) and come back to it at a later clock edge, based on some counter or signal. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 73668
Hi -
The synthesizer isn't going to know what to do with wait(50ms). In
fact, I've never seen wait() used with a delay inside.
Here's my template for an up counter. ga_reset is the global
asynchronous reset:
> always @(posedge clk or posedge ga_reset)
> if (ga_reset) <name>_ctr <= 0; // Asynchronous reset
> else if (sync_reset) <name>_ctr <= <name>_sync_init_val; // Synchronous init
> else if (<name>_preload_en) <name>_ctr <= <name>_preload_val; // Synchronous preload
> else if (<name>_up_count_en) <name>_ctr <= <name>_ctr + 1; // Synchronous count
I wouldn't be too quick to dismiss Stuart Sutherland's reference
guide. I use the printed version all the time, and it's extremely
handy. His online guide says:
wait (expression)
Delays execution until the expression evaluates as true.
This agrees with the IEEE spec.
John Sanguinetti has a free online training course:
http://www.vol.webnexus.com/
Bob Perlman
Cambrian Design Works
On Mon, 27 Sep 2004 12:01:32 -0700, Weizbox <> wrote:
>I am moving onto Verilog now from VHDL due to it being too complicated for me to start off with and not having any calsses available to go to in order to teach me it. So far Ive been just trying to make a simple counter that would pulse an led every second, and so far no luck. Im getting errors left and right, when I change one thing, I get another error, and when I fix that I seem to get others. I have no idea what Im doing wrong, everyhting looks like it would run fine from what Ive read. So if you can let me know what my errors are. Thank you!
>
>CODE:
>
>module pulse(led_o, clk50);
>
>input clk50;
>output led_o;
> reg [15:0] c;
>
>always @(posedge clk50) //Trigger on 50MHz clock
> begin
> if (c == 50000000) //Convert 50MHz Clock to 1Hz <= 0; led_o <= 1; //Turn led on
>wait (50ms) //wait 50ms
>led_o <= 0; //turn led off
>
>else
> c <= c + 1; //Step up c +1
> end
>
>endmodule
>
>ERRORS:
>
>ERROR:HDLCompilers:26 - clock.v line 12 unexpected token: '50'
>ERROR:HDLCompilers:26 - clock.v line 15 expecting 'end', found 'else'
>ERROR:HDLCompilers:26 - clock.v line 16 unexpected token: '<='
>ERROR:HDLCompilers:26 - clock.v line 16 unexpected token: '+'
>ERROR:HDLCompilers:26 - clock.v line 16 expecting 'endmodule', found '1'
>ERROR: XST failed
>
>Ive been useing this as a reference: <http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html>
>
>I suppose it isnt very good considering how far it has gotten me. If anyone else knows of a good online resource just to look up little things like wait, if, begin type stuff with proper sytax let me know!
>
>Thanks!
>-Weizbox
Article: 73669Ben G <nospam@nospam.nospam> wrote in message news:<2rqnfnF1d29pnU1@uni-berlin.de>... > I have an EDK design with a MicroBlaze processor and use the External > Memory Controller (EMC) to get access to off-chip SRAM. > > I access the SRAM from c using a pointer and have a loop in my program > that writes a value and increments the pointer to the next address. > > As I am using a pointer to type integer it is increased by 4 locations > each time I increment it. The SRAM I am accessing however is 32 bits > wide so I am not getting access to the full memory capacity. Is there a > setting somewhere for the compiler to tell it to increase by 1 address > location or am I using the wrong approach. You are getting access to full capacity. Addresses are always byte addresses. Integers are 4 bytes wide. When you move from one integer in an array to the next, the address differs by 4. Cheers, JonArticle: 73670
Call for Participation 2004 IEEE International Conference on Field Programmable Technology (FPT'04) 6 - 8 December 2004 The University of Queensland, Brisbane, Australia We invite you to join us in Brisbane in December for the 3rd annual IEEE International Conference on Field Programmable Technology. This year sees a program of three full days, comprised of two keynote talks, 34 lecture presentations, 44 posters, two social events, and an optional tutorial on "Using FPGAs for Networking Research" by Dr Gordon Brebner. Further details, including the preliminary program, may be found at http://icfpt04.itee.uq.edu.au/ Please note that the early registration deadline has been extended to 8 October (Brisbane time). Discounts are available for IEEE members and full-time students. Secure online registration is available. In association with the conference, a Xilinx University Program Professor's Workshop on "Embedded Linux for the Xilinx Microblaze Processor" will run on Thursday December 9 and repeated on Friday December 10. (The workshop is open to university academics, postgraduate students and tutors. There is no cost but you must register with Xilinx to attend this workshop.) Further details can be found at http://icfpt04.itee.uq.edu.au/xup_workshop.html We hope you will be able to join us in Brisbane. Prof. Neil Bergmann ICFPT04 Conference Chair School of Info. Tech. and Elec. Eng. The University of Queensland Brisbane 4072 Australia. Phone: +61-7-3365-1182 Fax: +61-7-3365-4999 E-mail: n.bergmann@itee.uq.edu.au Web: http://www.itee.uq.edu.au/~bergmannArticle: 73671
Hi, I have a design (basically a FIR filter) that is clocked by the output of a DCM. I understand that I should not do anything before the locked signal goes high. However, what is the right way to do this? I also have a small state machine that resets the FIR filter, sets some stuff, and then enable everything. The state machine is also clocked by the output of the DCM (it is the only clock of the design). Should I use the locked signal as an asynchronous reset of the state machine so that nothing happens before locked goes high? I wonder if this is what people do, or if there is an easier way. Thanks, DavidArticle: 73672
> > I often get Xilinx error messages saying that I can't read a pin that is > > configured "out mode" (or something like that). Up to now, to get around > > the error, I have been mirroring such a pin with an internal register and > > reading the output of the register instead. Recently I find that making > > such a pin an inout instead of an out will also let it be read. That's > > reasonable but seems contrary to what I believe that an inout pin is a > > bidirectional pin. What is the best way to do this, as a matter of style? > > > > b r a d @ a i v i s i o n . c o m > > > > > For some reason VHDL won't let you read a mode "out" pin, just one of VHDL's > quirks I guess - Verilog doesn't seem to have this problem. And, no you > don't > want to change the pin to an inout because then you are reading the signal > on the > wrong side of the I/O buffer. Just use a buffer to connect the internally > generated signal to > the output pin. Then you can read the internally generated signal as much > as you want, > and the Xilinx optimizing software will throw the buffer out when it > optimizes the design. > > Dan In this case my situation is reversed. I have an out pin (it's the Write*/Read SRAM line) and want to read it internally (one use would be to control the tristate data outputs).Article: 73673
I need help on Serpent implementation. It has a very large transformation table which i need to optimize. could anyone help?? The transformation table is basically a series of 3 input or 7 input XOR...please help.Article: 73674
I'm working on a quadrature decoder to interface with a rotation sensor. My thought was to have an asynchronous process that operates on the A and B signals, and then have the 'state' variable synchronous with the clock in a seperate process. The following vhdl works as expected in one simulation tool, but produces garbage when I use Quartus. begin process(A_in, B_in) begin state(3) <= state(1); state(2) <= state(0); state(1) <= A_in; state(0) <= B_in; end process; state_out <= state; direction <= ( (not state(3)) and (not state(0)) ) or ( state(3) and state(0)) ; end a; I expect that 'state' will always be of the form XXYY where XX is the old state, and YY is the current state of the inputs A and B (for example, 0001, 0111, 1110 etc). With one simulation tool I have, it works exactly as expected. With Quartus, the 'state' variable is always 0000, 0101, 1111, or 1010. Is there something wrong with the way I'm trying to implement this? Any suggestions on a better way?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z