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On Tue, 17 Aug 2004 12:54:58 +1200, SneakerNet wrote: > Hi All > > We are currently involved in some DSP work where by we need to do further > analysis on the final results. > The final result is 16bits which is being captured at 48kHz. > Currently I am using SignalTap and using this I'm able to capture a max of > 8k samples, however this is not enough (as RAM is finite) and I was > wondering is there anyway of real-time spooling this data back to PC? > > I'm using Nios Development Board (Cyclone FPGA) and ByteBlaster II. > This sounds like audio data. How about buying an audio card with s/pdif in and hooking your DSP to that via the fpga.Article: 72476
"Jesse Kempa" <kempaj@yahoo.com> wrote in message news:95776079.0408190852.4c900dcd@posting.google.com... > > I've figured it out now, and got my devices working perfectly. The process > > was not too hard - all I needed was to write a class.ptf file for each type > > of device, and get the signals and timing parameters specified correctly. > > All in all, I needed to write about 100 lines of text class.ptf file. > > However, to get that I had to read hundreds of pages of documentation in the > > Avalon Bus Spec and the SOPC references, as the information is pretty > > scattered. For the sake of others who face the same situation, could you > > suggest to the powers that be that they > > > > a) update these manuals to refer to the Nios II (I know not much has changed > > in the bus, but it'd be nice to be told that in the manual), > > > > b) put links to these manuals in the Nios II literature section as well as > > the Nios section, > > > > c) write a 10-page application note covering connection of external memory > > to tristate buses, to save lots of reading and collection of information, > > > > d) write a nice wizard, like the "interface to user logic" and "flash" > > wizards, making it easy to see the timing. > > > > > > Having figured out all the required signals and timing settings, the system > > worked great - I added the memory components, re-generated the design, and > > it worked first time. But a bit more directed information would have made > > the process much easier. > > > > David > > > > Thanks I will pass this on to the relevant people on the engr & doc > team for SOPC Builder. Work is already being done for a future release > on enhancing this functionality for more complex systems, but I am > surprised to hear that you had to write a PTF file for an off-chip > memory interface (the wizard in its current state should handle such a > thing) - you're right that better docs are in order for this. > The memory involved was pipelined synchronous static ram, so it needed things like latency settings. It's quite possible that I could have got something to work using the flash memory wizard (or is there a ram memory wizard that I missed?), but I don't think that would cover the latency. Incidently, are the Nios II masters latency-aware? And how about the DMA controller? I have a vague feeling the first answer is no, but I don't know about the second. It's just that if they are latency aware, they could read my ram chips at 3-1-1-1... timing rather than 3-3-3... I must say, though, that I like the way the master and slave are independant and don't need to know how the other side works - burst will work for masters that support it, and not for other masters. > Jesse Kempa > Altera Corp. > jkempa at altera dot comArticle: 72477
gerd?NO?SPAM@rzaix530.rz.uni-leipzig.de (Gerd) wrote in message news:<cfsd0d$i3i$1@news1.uni-leipzig.de>...
> Gerd <gerd?NO?SPAM@rzaix530.rz.uni-leipzig.de> wrote:
> > that I wouldn't consider it _better_ than the PPC. In fact with the PPC,
> > you only loose the couple columns associated with that PPC (and you can
>
> Have to correct myself on this one. I'm not sure you'ld "loose" these
> columns at all - I simply haven't tried reconfiguring these columns
> with the PPC active. Has anybody?
>
>
> regards,
> -g
Hi there,
I am working on a project in which I need to use modular
design to achieve partial reconfiguration using microblaze and its
peripherals (as one module). I am using opb_hwicap. The way I am doing
is... making a system design in xps, taking desing as sub module and
exporting it to ISE. In ISE I am deleting the system_stub.vhd,
system.bmm files and generating ngc for system.vhd without I/O
buffers(xilinx option for modular design). I made a top level file in
which the system and another module are used as blackboxes. ngc of top
level is generated with I/O buffers using ISE. Then as per the modular
design rules, I copied top level ngc to folder intial and generated
ngd of it. coming to active module phase of system, when I am using
this
ngdbuild -p xc2v1000fg456-4 -uc top_level.ucf -modular module -active
system.ngc ../../Top/Initial/top_level.ngd system.ngd
I am getting error....
ERROR:NgdBuild:559 - Cannot find active block 'system.ngc' in the
design.
Annotating constraints to design from file "top_level.ucf" ...
Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:885 - logical block 'testled' with type
'led_submodule' is
unexpanded and will be presumed to be a module.
WARNING:NgdBuild:885 - logical block 'top_micro/opb_hwicap_0' with
type
'opb_hwicap_0_wrapper' is unexpanded and will be presumed to be a
module.
WARNING:NgdBuild:885 - logical block 'top_micro/rs232_p160' with type
'rs232_p160_wrapper' is unexpanded and will be presumed to be a
module.
WARNING:NgdBuild:885 - logical block 'top_micro/mb_opb' with type
'mb_opb_wrapper' is unexpanded and will be presumed to be a module.
WARNING:NgdBuild:885 - logical block 'top_micro/dlmb_cntlr' with type
'dlmb_cntlr_wrapper' is unexpanded and will be presumed to be a
module.
WARNING:NgdBuild:885 - logical block 'top_micro/dlmb' with type
'dlmb_wrapper'
is unexpanded and will be presumed to be a module.
WARNING:NgdBuild:885 - logical block 'top_micro/ilmb' with type
'ilmb_wrapper'
is unexpanded and will be presumed to be a module.
WARNING:NgdBuild:885 - logical block 'top_micro/lmb_bram' with type
'lmb_bram_wrapper' is unexpanded and will be presumed to be a
module.
WARNING:NgdBuild:885 - logical block 'top_micro/microblaze_0' with
type
'microblaze_0_wrapper' is unexpanded and will be presumed to be a
module.
WARNING:NgdBuild:885 - logical block 'top_micro/ilmb_cntlr' with type
'ilmb_cntlr_wrapper' is unexpanded and will be presumed to be a
module.
I didn't understand why those wrappers are still unexpanded.
Can any one please tell me how to get rid of this error?
any help would be greatly appreciated.
regards
arun
Article: 72478"Jerry" <nospam@nowhere.com> wrote in message news:<10iakepgo6i76bd@corp.supernews.com>... > I replaced my NIOS I with a NIOS II and did a simulation. Hummm it seems > to take a lot more CPU time with a NIOS II. Has anyone else experienced > this? That's the price of progress...Article: 72479
Hi, I'm trying to enable the instruction cache on the Microblaze to compare the speed of executing code from BRAM with SRAM plus cache. I'm using the Insight XC2V1000 board with EDK 3.2. In a piece of test code which executes from SRAM, I enable the cache using microblaze_enable_icache() and disable using microblaze_disable_icache(). Any code between the enable and disable instructions does not get executed. I haven't checked that bit 26 of the MSR is set yet, but that's the next thing to verify. Has anyone else had a similar problem ? Should I try setting the MSR bit in assembly ? I use the default value for the tag address bits and the cache covers the whole of the available SRAM. Below is the section of the MHS file defining my Microblaze: BEGIN microblaze PARAMETER INSTANCE = mblaze PARAMETER HW_VER = 2.00.a PARAMETER C_USE_ICACHE = 1 PARAMETER C_CACHE_BYTE_SIZE = 1024 PARAMETER C_ICACHE_BASEADDR = 0xffe00000 PARAMETER C_ICACHE_HIGHADDR = 0xffefffff BUS_INTERFACE DLMB = d_lmb BUS_INTERFACE ILMB = i_lmb BUS_INTERFACE DOPB = opb_bus BUS_INTERFACE IOPB = opb_bus END Thanks, Alastair.Article: 72480
Hi Austin, Spartan3 suports 5V using external resistors. So, I suppose I can also use a resistor for interface a signal that swings from -18V to +18V. Ok? There are internal diodes to VCC and GND, isn't it? Luiz Carlos.Article: 72481
Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com> wrote in message news:<41235d89$0$338$ba620e4c@news.skynet.be>... > colin wrote: > > Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com> wrote in message news:<4122353f$0$2518$ba620e4c@news.skynet.be>... > > > >>colin wrote: > >> > >>>I would like to embed a device that has a PCI inteface with an FPGA > >>>(preferably a SPARTAN 3). > >>> > >>>Two questions have arisen before I start > >>> > >>>1) Many PCI based chips (including the one I want to use) can be > >>>purchased as a PCI card to speed up development. I have had a good > >>>google without success but does anyone know of an FPGA development > >>>platform that includes a PCI card site, I could then develop the > >>>firmware without designing a PCB. > >> > >>By PCI site, you mean a slot where you can put PCI cards or a PCI edge so > >>that you can use it your FPGA board as a PCI device. > >> > >>Look at the avnet spartan 3 kit. I have it and it's real nice ;) > >> > > > > Err. You seem to have missed the point. I want to buy a PCI card with > > the silicon I want to use on it and plug it into an FPGA development > > board. The avnet card looks like just another FPGA based PCI card, > > I've googled and I've found many of them. > > My FPGA will be a high performance slave with just enough mastering to > > do the config cycles to the other chip (unfortunately the config > > registers reset to zeroe's else I wouldn't need to do this) and to set > > up the DMA's > > > > By the loud silence I assume the FPGA board I want doesn't exist. > > Look for a passive PCI backplane. I have one that came with a Intel dev board. > > > Sylvain Unfortunately a passive backplane is just that. I would need a card plugged into the "master" slot which provides the clock and arbiter. I think that I would also need to plug the fpga card into the master slot so that it can drive idsel but I'm on the limits of understanding at about this point (at the moment). ColinArticle: 72482
Hi,
I've got it working again - comments underneath.
"Jesse Kempa" <kempaj@yahoo.com> wrote in message
news:95776079.0408191527.4bf80942@posting.google.com...
> "David Brown" <david@no.westcontrol.spam.com> wrote in message
news:<cg2eqt$s7v$1@news.netpower.no>...
> > Hi,
> >
> > I don't know what Mr. Brookes method is, since it was not posted here.
> > Perhaps he (or you) tried to email me a copy, but failed to notice the
"no
> > spam" addition to my news-posting address.
> >
> > However, just at the moment I have a far bigger problem that is stopping
me
> > doing any debugging at all - nios2-gdb-server is now refusing to connect
to
> > my Nios2 jtag port. I have tried all sorts of things, including
rebuilding
> > a new (fairly minimal) nios2 design on my board, with no luck. The last
> > thing I did was take a test project I made on my original Nios Cyclone
> > development kit and replace the Nios 1 with a Nios 2, and I still can't
get
> > any contact. This is hardware that I know without doubt is working
fine - I
> > can download designs with the jtag interface (ByteBlaster II), and can
> > connect gdb to the Nios 1 design. But I can no longer contact a Nios 2
for
> > debugging over the jtag interface. When I run
> > "nios2-gdb-server --verbosity=4" and try to connect to it with
> > nios2-elf-gdb, I get the information:
> >
> > # [nios2-gdb-server] g_verbosity: 4
> > # [nios2-gdb-server] nios2-gdb-server listening on port 2342
> > # [nios2-gdb-server] accepting gdb connection
> > # [nios2-gdb-server] connecting to JTAG debug module
> > # [nios2-gdb-server] CPU will be reset on connect
> > # [nios2-gdb-server] JTAG cable: ""
> > # [nios2-gdb-server] JTAG device: -1
> > # [nios2-gdb-server] JTAG debug module instance: -1
> > # [nios2-gdb-server] using MDI port: "sld"
> > # [nios2-gdb-server] MDI error FindAndOpenNode Lock Chain:
> > AJI_BAD_HARDWARE. -105 (nios2-gdb-server_mdi.c line 161)
> > # [nios2-gdb-server] failed to connect
> >
> > Similarly, the IDE debug setup finds my ByteBlasterII on lpt1, but
reports
> > <no devices connected> for the jtag device. I had this same effect when
I
> > first used the Nios 2, with the ByteBlaster II connected to lpt2. This
> > worked fine for the Nios, and for downloading fpga designs, but the
Nios2
> > debugger could not see the Nios 2. Switching to lpt1 fixed that. I was
not
> > too surprised with that, since I have had little luck getting my lpt2
card
> > to work with other jtag-type debuggers - in fact, I was very surprised
when
> > it *did* work with the Nios 1.
> >
> > I've now tried everything I can think of, so if anyone else has any
bright
> > ideas for me, I'd be very grateful!
> >
> > David
>
> Hi David,
>
> Sorry, the reference to that gentleman was only in the context of
> talking to GDB directly from within the IDE as you had originally
> inquired about - I posted that information during the first reply (I
> just forgot to remove some of the email chain that wasn't relevant to
> your question).
>
I see what you mean now - you had given me instructions how to do what I
wanted (although I couldn't try it until now), along with a note saying it
couldn't be done... I've now got my gdb command prompt from within Eclipse,
just as I wanted.
> About your problem: Can you download/debug a hello-world type
> application without doing the gdb commands manually? This would be a
> good starting point. One thing I noticed from the error message dump
I couldn't get that far - I'd have been happy getting a "0x00000000 in ??
()" message indicating some contact with gdb.
> is that there is no JTAG cable ("") -- you might try the following:
> Make a new "run" or "debug" target in the IDE (this is covered in the
> Nios II SW dev tutorial in the IDE on-line help), and in the 'Run'
> screen go to 'Target Connection' and manually pick the programming
> cable you're using from the drop-down, and if necessary the device in
> the JTAG chain (if there are multiple devices). Here you can also
> 'Refresh' the lists to see that things are being detected properly.
> This is necessary more often than not if you have two programming
> cables installed (and it sounds like you might, one in lpt1, and one
> in lpt2).
>
I'd been doing that until I was blue in the face...
> FYI, the "list" of programming cables comes from Quartus (what ever
> programming cables the Quartus programmer sees, the IDE will have
> access to).
>
I had two cables in the jtag setup from Quartus programmer, and had tried
swapping between them - both worked fine for programming from Quartus. What
finally got the debugger working was to remove lpt2 from the Quartus setup -
after that, the IDE had no problem seeing the Nios2 and selecting it
automatically. I can see now why running gdb-server from the command-line
was unlikely to work when I had two cables set up - I had tried without
specifing a cable, and with "lpt1" and "lpt2" as cable arguements. Now when
I run nios2-gdb-server from the command line, it reports the cable as
"ByteBlasterII [LPT1]", so maybe I should have specified that whole string.
Anyway, I'm only using one board at a time, so I'm happy enough with just
lpt1 setup. The strange thing is that both were set up in Quartus the other
day when Nios2 debugging was working fine. Perhaps there is an obscure bug
in the debugger server - after all, I doubt that two parallel port cables is
a setup that has figured greatly in testing, and I suppose I'll be moving to
a USB Blaster before long anyway.
> If the above doesn't help I'd suggest that you contact your FAE or
> Altera support team for some one-on-one help on the issue.
>
I've talked to him, and he was going to ask others at Altera. I'm happy
that my debugging is now working exactly as I wanted, both on the
development kit and my own hardware.
Many thanks!
David
> Jesse Kempa
> Altera Corp.
> jkempa at altera dot com
Article: 72483GAL,PAL,PLD, CPLD,FPGA, (what else...?) GAL : Generic Logic Array PAL : Programmable Array Logic PLD : Programmable Logic Device CPLD : Complex Programmable Logic Device FPGA : Field Programmable Gate Array Can someone explain with comparison what is the difference between all these GAL,PAL,PLD, CPLD,FPGA, (what else...?) logic units? Can all these units can be programmable with VHDL ?Article: 72484
<many gates> wrote in news:4125f816$0$6317$afc38c87@news.optusnet.com.au: > GAL,PAL,PLD, CPLD,FPGA, (what else...?) > > GAL : Generic Logic Array I thought this was: Gate Array Logic. > Can all these units can be programmable with VHDL ? That's a language. As long as someone has a tool to convert VHDL source code to the device's expected "bit" file then yes. -- - Mark -> --Article: 72485
<many gates> schrieb im Newsbeitrag news:4125f816$0$6317$afc38c87@news.optusnet.com.au... > GAL,PAL,PLD, CPLD,FPGA, (what else...?) > > GAL : Generic Logic Array > PAL : Programmable Array Logic > PLD : Programmable Logic Device > CPLD : Complex Programmable Logic Device > FPGA : Field Programmable Gate Array > > Can someone explain with comparison what is the difference between all these > GAL,PAL,PLD, CPLD,FPGA, (what else...?) logic units? > > Can all these units can be programmable with VHDL ? > > > Hello, As a long year digital expert I'll try to tell you the difference of all these logic parts. First: the content of all of them can be described by the language VHDL. But this makes sense only with higher complexities, which big CPLDs and FPGAs have. PLDs, PALs and GALs are the lowest complexity of logic arrays (f.e. 22V10 -> 10 Flip-Flops + AND/OR-Logic). CPLDs and FPGAs have more gates and Flip-Flops, where CPLDs have a more fixed structure (predefined number of gates and FFs) , while FPGAs are consisting sometimes of pure gates (ACTEL, Antifuse) and can be handled like true gate arrays. FFs are built by gates then. For the high complexities VHDL is the right tool to handle big designs. But you should keep in mind, that the later layout of the FPGA-chip depends on the design (how many IO-ports, number of FFs, number of gates, number of logic blocks etc.). The best way to learn about the digital designs is to use the partly free tools and do a design by yourself. All suppliers have nice kitparts and offer design software . Have fun. Regards, RolandArticle: 72486
manygates asked: >GAL,PAL,PLD, CPLD,FPGA, (what else...?) > >GAL : Generic Logic Array >PAL : Programmable Array Logic >PLD : Programmable Logic Device >CPLD : Complex Programmable Logic Device >FPGA : Field Programmable Gate Array > >Can someone explain with comparison what is the difference between all these >GAL,PAL,PLD, CPLD,FPGA, (what else...?) logic units? > >Can all these units can be programmable with VHDL ? This could take awhile :) The most basic thing all of these have in common is the ability to create unique circuit configurations on a standard device, and with most, the ability to erase these configurations, and create new ones. If we had a time machine to go back - way back, we would find only devices with fixed architecture elements, e.g. SSI devices(small scale integration) andgates(7408) nandgates(7400), or gates (7432) inverters (7404) and then a big jump to MSI (medium scale integration) like 7474(d flipflop with set/reset) counters (74161 - 4bit counter) , and the industry continues into LSI, VLSI, ASICs, uprocessors, memories, etc.... then this idea of PLD - programmable logic device by using fuses in an array, speicific configurations can be accomplished- by connecting traces in the metal layers on a device, making the gates connected to them form new circuits - unfortunately, fuses only work once :) - testing by the manufacturer was limited - after all, how do we test a fuse? PAL programmable array logic early PALS were in preset configurations - where fuses could acitivate some customization - the pal16l2, the pal16r4, had and/or gate structures, or limited registers to certain points - somewhere along the way - UVerasable arrived, displacing one time programmable fuses - with a nice quartz window, so you could flood the connections with UV to reset the programming cell - and use a nice paper label to cover it up when programmed - and with UV, testing by the manufaturer improved, as a pattern could be built, then removed, although with 30-60minute erase times, it was still limited - GALs - neat concept - all possible PAL configurations could be accomplished,e.g., 16v8 - Variable function, as the 'macrocell' for each output pad had both combinatorial and registered capability, and even better, these werre electrically erasable(EECMOS) and could easily be tested and erased in milliseconds Along came FPGA and CPLD I know I am leaving out a bunch of detail - the various vendors do a superb job of describing in detail in their literature - CPLD - Complex Programmable Logic Device early CPLD structures were closely related to the GAL/PAL idea, and created an array of PALs ( think LAB, or GLB, or PALblock, or functionblock) in various sizes and what not - CPLDs at their most basic are this A COMPLEX LOGIC BLOCK - with anywhere from 36 to 68 inputs available per block, with a range of PTERMS(and gate) from 1 to 160, available to drive each macrocell - combinatorial or registered. Mostly NONVOLATILE devices(EECMOS) with some newer devices also incorporating SRAM as part of the architecture, decent clock structures, high performance for large, single logic level functions - think statemachines, decoders, counters etc - Routing and interconnect is typically a single large central routing array - so interconnecting logic has little penalty in routing - and within the LOGIC BLOCK - there is full interconnect for the various elements FPGA Field programmable Gate Array - FPGAs are devices which can achieve significantly larger logic gate counts, with each logic element TYPICALLY being built with a 4input LUT(look up table - which allows pretty much any combination of 4 inputs ) with a combinatorial and/or registered output available per logic element - each vendor has thier own 'tweek' on this with additinal logic for muxes, carrychainsfor arithmetic/ counting functions, etc -I'm sure others will jump in here) - nad since the logic element is small, a lot more fit on a device!. To interconnect these logic cells requires significant routing, or interconnect, resources, to build a larger function out of the many small functions. Much magic is required here, by the silicon designers to balance resource requirements, and the SW designers, to implement algorithms which efficiently connect the elements together. FPGAs generally offer additional elements, e.g. RAM BLOCKS, so that more complex system functions can be implemented within the single device. As technology has moved forward, many different elements have found their way into FPGA - processors, SERDES, DSPBLOCKS etc. MOSTLY based on SRAM processes, they offer rapid reconfigurability as well, with the burden of storage somewhere in the system for the datastreams required to configure the device. There are Vendors with NONVOLATILE FPGAs as well, running form FUSE BASED(one time programmable) to Flash and eecmos based devices which incorporate flash and eecmos memory to carry the datastream for configuration on chip. I hope this was a good start - Peter, Paul, Austin, Jim, Rick, Ray, Uwe, any others out there want to expand on these points? Mike Thomas Lattice SFAE NY/NJArticle: 72487
Dear Roland, Thank you for your clear and easy to understand summary. > The best way to learn about the digital designs is to use the partly free > tools and do a design by yourself. Can you recomment a particular one to learn CPLD/FPGA and VHDL? "Roland Macho" <RMacho@t-online.de> wrote in message news:cg51qu$j5n$04$1@news.t-online.com... > > <many gates> schrieb im Newsbeitrag > news:4125f816$0$6317$afc38c87@news.optusnet.com.au... > > GAL,PAL,PLD, CPLD,FPGA, (what else...?) > > > > GAL : Generic Logic Array > > PAL : Programmable Array Logic > > PLD : Programmable Logic Device > > CPLD : Complex Programmable Logic Device > > FPGA : Field Programmable Gate Array > > > > Can someone explain with comparison what is the difference between all > these > > GAL,PAL,PLD, CPLD,FPGA, (what else...?) logic units? > > > > Can all these units can be programmable with VHDL ? > > > > > > > > Hello, > As a long year digital expert I'll try to tell you the difference of all > these logic parts. > First: the content of all of them can be described by the language VHDL. > But this makes sense only with higher complexities, which big CPLDs and > FPGAs have. > PLDs, PALs and GALs are the lowest complexity of logic arrays (f.e. > 22V10 -> 10 Flip-Flops + AND/OR-Logic). > CPLDs and FPGAs have more gates and Flip-Flops, where CPLDs have a more > fixed structure (predefined number of gates and FFs) , while FPGAs are > consisting sometimes of pure gates (ACTEL, Antifuse) and can be handled like > true gate arrays. FFs are built by gates then. > For the high complexities VHDL is the right tool to handle big designs. > But you should keep in mind, that the later layout of the FPGA-chip depends > on the design (how many IO-ports, number of FFs, number of gates, number of > logic blocks etc.). > The best way to learn about the digital designs is to use the partly free > tools and do a design by yourself. > All suppliers have nice kitparts and offer design software . > > Have fun. > > Regards, > Roland > > >Article: 72488
Luiz, Yes, absolutely. Examine the ASCII IBIS file and you will directly see the IV curve of the protection (clamp) diodes to ground, and Vcco. Select your resistor value such that the current is less than 10 mA into the diodes, and everything is just fine. Austin Luiz Carlos wrote: > Hi Austin, > > Spartan3 suports 5V using external resistors. > So, I suppose I can also use a resistor for interface a signal that > swings from -18V to +18V. Ok? There are internal diodes to VCC and > GND, isn't it? > > Luiz Carlos.Article: 72489
B. Joshua Rosen wrote: > > This is good news, hopefully the new GUI tool kit will be X windows > friendly. The current toolkit is awful, FPGA Editor (which is the only GUI > tool I ever use) is unusable over a network... I don't run FPGA Editor over a network. But as a performance data point, I often having seti running in the background reniced to the lowest priority. If I run fpga_editor while seti is running, performance is terrible; in fact unusable. If I stop seti, then performance is quite acceptable; I would even say pretty good. -- My real email is akamail.com@dclark (or something like that).Article: 72490
Hello, I need to change some logic for a board with Spartan XL chip. I got ISE 3.3 Foundation installed and when I want to synthesize, it tells me that it cannot check out a license. Doing some diagnostics with the licenses utility it tells me that the FPGA Express licenses expired in 2002. Does that mean I have to buy another FPGA Express licenses to do the synthesis? Seems like synthesis is not for free for those old chips? I guess I could try using a newer version, like 4.1, but I am not sure when the FPGA Express licenses for this one will expire. I searched in the archives for similar postings. I found some older postings from last year. I read from people keeping older versions of the software. Do they buy an update of the FPGA Express license? Did I do something wrong with the FPGA Express licenses and I can actually still use it? Thanks for the help. GuenterArticle: 72491
lecroy wrote: >>Description: want to code a state machine and if it goes into an > undefined >state, what does he need to code to reset the state machine > I wonder if using the "minimal" gate feature and define a 2^nth FSM, > then encode all of the states if it would optimize out states that > have no entry point or not. Maybe there is a switch for the optimizer > as well? I don't want to waste a lot of time trying things to find a > method that works. This has been discussed at great length on comp.lang.vhdl: http://groups.google.com/groups?q=safe+state+machine+vhdl There's no simple answer. Consider using the binary (minimal bits) setting and see what you get. -- Mike TreselerArticle: 72492
"Jerry" <nospam@nowhere.com> wrote in message news:<10iakepgo6i76bd@corp.supernews.com>... > I replaced my NIOS I with a NIOS II and did a simulation. Hummm it seems > to take a lot more CPU time with a NIOS II. Has anyone else experienced > this? > > ARRRRRGGGGGHHHHH > Jer The wonderful thing about simulation is that it shows you what happens, in detail, in your system for debugging purposes. Things like processor cache initialization, SDRAM controller initialization, and other things required to a get a processor-based system from power-up to main() take a while. That said we offer two things which you might be interested in if you don't want to see every bit of detail: - "Simulation" software libraries & crt0 code for use only with RTL simulation (skips lengthy things like cache initlaization). - The instruction set simulator. Both of these are described in the Nios II SW Dev Handbook & AN333 (Simulating Nios II processor systems). JesseArticle: 72493
<many gates> wrote in message news:41261019$0$30602$afc38c87@news.optusnet.com.au... > Dear Roland, > > Thank you for your clear and easy to understand summary. > > The best way to learn about the digital designs is to use the partly > free > > tools and do a design by yourself. > Can you recomment a particular one to learn CPLD/FPGA and VHDL? I have a simple CPLD design on my webs site that may be used with the free Xilinx Webpack software. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 72494
>Unfortunately a passive backplane is just that. I would need a card >plugged into the "master" slot which provides the clock and arbiter. > >I think that I would also need to plug the fpga card into the master >slot so that it can drive idsel but I'm on the limits of understanding >at about this point (at the moment). I think you could plug some normal "master" card into the master slot, say a PC. It will do the configuration setup work. Then just let it sit there. Now you can play with your FPGA card and whatever else you have installed. Your FPGA card can do PCI cycles to talk to other cards. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 72495
> The memory involved was pipelined synchronous static ram, so it needed > things like latency settings. It's quite possible that I could have got > something to work using the flash memory wizard (or is there a ram memory > wizard that I missed?), but I don't think that would cover the latency. > Incidently, are the Nios II masters latency-aware? And how about the DMA > controller? I have a vague feeling the first answer is no, but I don't know > about the second. It's just that if they are latency aware, they could read > my ram chips at 3-1-1-1... timing rather than 3-3-3... I must say, though, > that I like the way the master and slave are independant and don't need to > know how the other side works - burst will work for masters that support it, > and not for other masters. > Aha, My apologies, I forgot you mentioned this was SSRAM (for some reason I was thinking it was async). You're right about latency; this currently requires a PTF entry to speciy max pending read transfers. About your question: The Nios (and Nios II) instruction master is latency aware; after getting the first 'n' reads through the pipe, you get a word per clock (assuming that the memory can handle it). The data master is not latency aware. DMA controller is on both of its masters. However, this should not affect your slave peripheral design! (You shouldn't need wait states unless your SSRAM can't handle the desired clock speed). A master is "latency aware" if it has the "readdatavalid" pin (Avalon spec has more detail on this). Masters which aren't latency aware are just told to "wait" until the data comes back (and can therefore only issue one access at a time). This is the beauty of the whole system - masters designed with performance in mind can get it from slaves despite pipelining between the two; masters designed for low logic usage need not impose wait states on the otherwise high-speed memory. JesseArticle: 72496
Dear FPGA, I am looking to find a schematic with FPGA SPARTAN 2 OR 3 with 208 pin (or more) in Protel format or Orcad. Thank you in advance, Bob E-MAIL : VIDEOREMOTE1@YAHOO.COMArticle: 72497
On Fri, 20 Aug 2004 13:02:54 +1000, Allan Herriman wrote: > On Thu, 19 Aug 2004 17:39:55 -0400, "B. Joshua Rosen" > <bjrosen@polybus.com> wrote: > >>On Wed, 18 Aug 2004 16:43:35 -0700, Neil Glenn Jacobson wrote: >> >>> The short answer that avoids almost all the specific issues you raise is >>> that we are moving away from a GUI toolkit that is encumbered with a >>> per-seat license fee. >> >>This is good news, hopefully the new GUI tool kit will be X windows >>friendly. The current toolkit is awful, FPGA Editor (which is the only GUI >>tool I ever use) is unusable over a network. > > FPGA Editor is also the only GUI tool I use. > I use it over a network quite successfully, using TightVNC, since my > desktop machine is too small and slow to run FPGA Editor itself. > What makes you say it's unusable? > > Regards, > Allan. I'm running it over X not VNC (I don't want a desktop just the application), it takes minutes to draw a screen. VNC is a Windows way of doing things, it moves pixels which is horribly ineffecient compared to X which moves commands. However since FPGAeditor is a Windows application I can see where VNC might do a much better job because it's pixel oriented. However all of my servers are running Mandrake 10.0 now so I can't run FPGAEditor on them anyway, at least until 7.1 comes out.Article: 72498
The new serial devices can not be programmed with old Byteblaster, new ByteBlaster II is required. To make ByteBlaster II (or convert MV to II) only one change is needed: the loopback wire from pin 10 should go to pin 6 (not 7 as for MV), after this small mod Quartus programmer recognizes the cable as ByteBlaster II. The additional signal connections for Active serial programming can be found in Altera ByteBlaster II datasheet. Hope this info is sufficient :) Antti http://altera.openchip.orgArticle: 72499
Howdy Gurus,
I've seen the Xilinx Virtex 2 IOB documentation describing their LVDS
i/o and their DDR i/o, but haven't found a clear explanation yet of
the two being used together.
DDR by itself is pretty obvious, but the LVDS appears to work by a
magical connection between two neighboring IOBs.
For an LVDS input pair (Dp and Dn) coming in at DDR, does the
differential-to-single-ended conversion take place before the input
flops of the IOB?
i.e., if Dp comes into IOB1 and Dn comes into IOB2, is there a
single-ended output from some magical cell after the IOBs that I have
to feed into two general CLB flops to get my registered Qre (rising
edge) and Qfe (falling edge) outputs? (or specify an attribute to
request that they be mapped into IOB flops?)
Or, if the conversion to single-ended is done before the IOB flops,
then the single-ended DDR data is easily clocked into the two IOB
flops on opposite clock edges, right?
If that is the case:
Dp -> IPAD -> IOB1 ---\
(diff2single) >----- Dddr -----> to IOB flops
Dn -> IPAD -> IOB2 ---/ (single-ended)
then which flops (those in IOB1 or IOB2) get the DDR data?
A clear explanation would be great, code/constraint snippets would be
lovely!
Thanks,
MarkJ
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