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In article <acc68109.0410120613.6e669b1b@posting.google.com>, mete wrote: > Is there method that is more efficient than regular division for > calculating modulus ? Depends on the modulus. For example, if you want to calculate x mod 2^4 you can just take take the four lowest bits and set the rest to zero. For more complex or non-fixed moduli it's more difficult.Article: 74476
Wong wrote:
> tatto0_2000@yahoo.com (Wong) wrote in message news:<509bfe22.0410110029.3a3cccc0@posting.google.com>...
>> I am a Actel 54SXA family user. I would like to get from the
>>fusefile what I/O standard I have selected in my Designer software
>>(i.e. PCI, LVTTL). Is that possible ? I am doing so because I have
>>been messed up my files and I cant trace back.
If you don't remember, it's probably the default.
Check with Actel and measure a programmed device for
output swing and input thresholds.
-- Mike Treseler
Article: 74477Hi! I have a XilinxVP20 chip with 2 PPC cores and a 32M SDRAM. what I want to do is to use the SDRAM as instruction memory for one of the PPC cores, but I couldn't figure out how to upload the instruction data onto the SDRAM. thanks in advance! -yangArticle: 74478
Raghavendra, Yes. M=16, D=1 will multiply the 20 MHz on CLKIN to 320 MHZ on CLKFX output. The clock GUI assumes that you are also using the DLL feature at the same time (ie CLKFB is connected) and it applies the minimum input clock frequency for that feature. If you are using the synthesizer only, the input frequency is not limited (except by the resulting output frequency as a choice of M and D). Austin Raghavendra wrote: > Hi all, > Given a clock of 20Mhz can I generate 320Mhz clock output using > single DCM in Xilinx FPGA? > > Regards > Raghavendra.Sortur.Article: 74479
I am using the virtex II. Sorry about that.Article: 74480
"Yaseen Zaidi" <yaseenzaidi@NETZERO.com> wrote in message news:a31921fc.0410120224.23a6ab0a@posting.google.com... > This may sound trivial but why is data being output (read) on the out > port during the write cycle in the Xilinx inferred RAM examples such > as: > > if (CLK'event and CLK = '1') then > if (en = '1') then > if (we = '1') then > ram(conv_integer(unsigned(addr))) <= di; > do <= di; > else > do <= ram(conv_integer(unsigned(addr))); [snip] If you want the read data to stay unchanged during a write, you *might* be able to get a good inference for the Viertex-II/Spartan-3 and later devices but you'd probably have to instantiate it or apply the constraint manually. There's a "WRITE_MODE" constraint for each of the two ports that can be set to "NO_CHANGE" if you like, keeping the read data on the port through the write.Article: 74481
Hello, Does anybody know how to initialize a BlockRam of a PARTIAL BITSTREAM with an elf file? ArunArticle: 74482
Hi, I've seen this prototype board from Altium that seems to have a very good price: http://www.altium.com/livedesign/ It comes in two flavours: one with an Altera Cyclone series EP1C12F324C8 and the other one with a Xilinx Spartand 3 XC3S400-4F456C. Both options have the same price of $99. Besides the FPGA, the both kits are exactly the same thing. My question is which one to select? Personally, I'd rather select the BIGGER one but I don't know which one it is. I know it is very difficult to compare the SIZE of two FPGAs with very different architectures. I used to compare the total number of the programmable flipflops in the FPGAs as my index. (it can be discussed if it is indeed a good index or not, but I think for syncronous and NORMAL designs this is much better than fuzzy things like system gates etc.). It seems that EP1C12 has much more FFs in the programable sections than XC3S400. So what do you think? Do you think EP1C12 is bigger than XC3S400? For designs that would be more of DSP type which one is better? And what for designs with a small processor inside? Well, one option is to buy both of them as you can easily cascade them an use them together in peace :) Regards ArashArticle: 74483
More: Looks like the data sheet has a spec of 50 MHz as the min for the CLKIN for the DFS in high frequency mode. Not sure how that got in there.... Researching that now. M=16 with Fin = 20 MHz does get you to 320 MHz output. It may also be that the jitter is not so great with large M's and small input clock frequencies (greater than 10% of the period), so I have to get the jitter calculator to also let me enter 20 MHz in HF mode to see what it tells me. Austin Austin Lesea wrote: > Raghavendra, > > Yes. > > M=16, D=1 will multiply the 20 MHz on CLKIN to 320 MHZ on CLKFX output. > > The clock GUI assumes that you are also using the DLL feature at the > same time (ie CLKFB is connected) and it applies the minimum input clock > frequency for that feature. If you are using the synthesizer only, the > input frequency is not limited (except by the resulting output frequency > as a choice of M and D). > > Austin > > Raghavendra wrote: > >> Hi all, >> Given a clock of 20Mhz can I generate 320Mhz clock output using >> single DCM in Xilinx FPGA? >> >> Regards >> Raghavendra.Sortur.Article: 74484
Hi ng, i'm currently building a serial controller between a 5V FPGA and a 3.3V microcontroller. Maybe someone of you can tell me, if there exists any common electronic component which can convert digital signals at ~ 1MHz with high level varying from 3.0 to 5.0 Volt and should output a signal with high level at 3.3Volt . (low level is always 0V) first i tried to build a simple voltage divider with two resistors, which was only acceptable with stable 0V Low /5V High input... the other problem is a fixed input capacitor at the 3.3V device of 50pF which - in combination with my voltage divider - passed only low frequencies. thanks in advance, StefanArticle: 74485
"Wong" <tatto0_2000@yahoo.com> wrote in message news:509bfe22.0410120231.5a0db886@posting.google.com... > tatto0_2000@yahoo.com (Wong) wrote in message news:<509bfe22.0410110029.3a3cccc0@posting.google.com>... > > Hi, > > I am a Actel 54SXA family user. I would like to get from the > > fusefile what I/O standard I have selected in my Designer software > > (i.e. PCI, LVTTL). Is that possible ? I am doing so because I have > > been messed up my files and I cant trace back. > > Thanks in advance. > > Any answer ? Please ..... This might work. Create a new design and compile it twice to get the same format fusefile, once with PCI and once with LVTTL without making any other changes. Then compare the two files to see what's different. Then see if the difference is evident in your old fusefile. -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email)Article: 74486
Further, Baased on the jitter predictor: Fin = 20 MHz, Fout = 320 MHz, M=16, D = 1 Output period = ~ 3.12 Period jitter = 700 ps p-p (worst case) Period Jitter = 22.2% Not a very good quality clock, as you have to deal with the worst case jitter divided by two taking away from your timing margin (worst case shortest possible period). Austin Austin Lesea wrote: > More: > > Looks like the data sheet has a spec of 50 MHz as the min for the CLKIN > for the DFS in high frequency mode. > > Not sure how that got in there.... > > Researching that now. M=16 with Fin = 20 MHz does get you to 320 MHz > output. > > It may also be that the jitter is not so great with large M's and small > input clock frequencies (greater than 10% of the period), so I have to > get the jitter calculator to also let me enter 20 MHz in HF mode to see > what it tells me. > > Austin > > Austin Lesea wrote: > >> Raghavendra, >> >> Yes. >> >> M=16, D=1 will multiply the 20 MHz on CLKIN to 320 MHZ on CLKFX output. >> >> The clock GUI assumes that you are also using the DLL feature at the >> same time (ie CLKFB is connected) and it applies the minimum input >> clock frequency for that feature. If you are using the synthesizer >> only, the input frequency is not limited (except by the resulting >> output frequency as a choice of M and D). >> >> Austin >> >> Raghavendra wrote: >> >>> Hi all, >>> Given a clock of 20Mhz can I generate 320Mhz clock output using >>> single DCM in Xilinx FPGA? >>> >>> Regards >>> Raghavendra.Sortur.Article: 74487
rickman wrote: > I believe when you say "4,7V" you mean what we call 4.7 volts in the US, > no? Damn, just gave myself away! <grin> English is not my native language, but you're right: I meant 4.7 volts. Jim Granville wrote: > If the PIC is always the master, you could try making the SCL line > always CMOS drive : In single master, only SDA needs to be open drain. I already tried that without success. > That will ensure faster clock edges - what you describe is a > little counter-intuitive, esp as you say the resistor change had > no effect, but sounds closest to edge-effects. > FPGAs tend to be slow edge intolerant. Thank you Jim, that was it! I put a buffer between the PIC and the FPGA on the SCL line and now it works. So, what do you, Jim, Rick and all the other experts, recommend to get the edges on the I2C lines faster? There must be another solution for it, I guess, since buffers won't work on bidir lines. Thank you! Markus PS: Microchip says max. rise/fall time for the I2C lines are 300ns! :-(Article: 74488
Stefan Oedenkoven <stefan-oedenkoven@gmx.de> wrote: > Hi ng, > Hi Stefan! > i'm currently building a serial controller between a 5V FPGA and a 3.3V > microcontroller. Maybe someone of you can tell me, if there exists any > common electronic component which can convert digital signals at ~ 1MHz with > high level varying from 3.0 to 5.0 Volt and should output a signal with high > level at 3.3Volt . (low level is always 0V) > Please look for "voltage translator". There are some ICs available for this purpose. You can also build them with two transtors in common base configuration. If you google for transistor voltage translator you should find it, if I am wrong just send me a mail. Best regards, Christoph > >Article: 74489
mete wrote: > Is there method that is more efficient than regular division for > calculating modulus ? For specific input base and modulus there is usually an efficient way. For decimal input and modulus of 3 or 9, you can add the digits together, and take the modulus of the sum. For binary input there are even more rules, but the modulus must be known in advance. If the modulus is variable, I don't know of a general formula. -- glenArticle: 74490
Wong wrote: > tatto0_2000@yahoo.com (Wong) wrote in message news:<509bfe22.0410110029.3a3cccc0@posting.google.com>... > >>Hi, >> I am a Actel 54SXA family user. I would like to get from the >>fusefile what I/O standard I have selected in my Designer software >>(i.e. PCI, LVTTL). Is that possible ? I am doing so because I have >>been messed up my files and I cant trace back. >> Thanks in advance. > > > Any answer ? Please ..... Take your design, and change ONLY the I/O standard in the area you are unsure about, then compare the final fuse files. When you have the I/O standard matching, the files will compare without error. [ This presumes your design has NOT changed in the meantime... ] Or, you could go to your backup files, as the I/O standard is unlikely to have changed since the PCB was designed ? -jgArticle: 74491
Stefan, TI do a CB3T family. What do you mean by common? They're common as muck in my designs! http://focus.ti.com/lit/an/scda008/scda008.pdf Cheers, Syms. "Stefan Oedenkoven" <stefan-oedenkoven@gmx.de> wrote in message news:2t2g73F1qfp5eU1@uni-berlin.de... > i'm currently building a serial controller between a 5V FPGA and a 3.3V > microcontroller. Maybe someone of you can tell me, if there exists any > common electronic component which can convert digital signals at ~ 1MHz with > high level varying from 3.0 to 5.0 Volt and should output a signal with high > level at 3.3Volt . (low level is always 0V)Article: 74492
Stefan Oedenkoven wrote: > Hi ng, > > i'm currently building a serial controller between a 5V FPGA and a 3.3V > microcontroller. Maybe someone of you can tell me, if there exists any > common electronic component which can convert digital signals at ~ 1MHz with > high level varying from 3.0 to 5.0 Volt and should output a signal with high > level at 3.3Volt . (low level is always 0V) > > first i tried to build a simple voltage divider with two resistors, which > was only acceptable with stable 0V Low /5V High input... the other problem > is a fixed input capacitor at the 3.3V device of 50pF which - in combination > with my voltage divider - passed only low frequencies. > > thanks in advance, > Stefan Two options: a) A lot (most new familes?) of CMOS Logic devices ( TI, Philips, Fairchild et al ) have overdrive tolerance, so poered from 3.3V, they do not mind 5V overdrive on IPs. Use a set of these, powered, and in the direction as needed. b) New are level converters, with dual Vccs, from TI, and IIRC Fairchild. These are a more precise solution, and will give lower Icc levels. Driving a 5V powered TTL threshold gate with >2.4V hi, works in the Logic sense, but it does draw IP buffer current, so if you are worried about static Icc, the level converters can be a better solution. -jgArticle: 74493
OK, I have a board with an XC2S150 on it, and a load of I/O pins; the wiring on the board and the configuration of the default IP blocks on the FPGA appears to set the pins up as LVTTL. On the other side of the room, I have some photo-diodes and some LM324N op-amps. If I rig up an op-amp as a comparator, I can get a signal which swings from 0V to ... umm ... inspect the datasheet ... Vcc - 1.5V. Is there some easy way I can set up the IOBs so that the FPGA believes that 0V is a zero and 1.8V a one? Or should I rig up another battery to increase the supply voltage to the op-amp by 1.5V or so; in that case I might be setting the input voltage on an FPGA pin to slightly greater than the supply voltage to the FPGA, which seems likely to be painful. I've had a look at Schmidt triggers and the like, but, whilst something like a 7414 has output swinging neatly from one supply line to the other, it seems, when running from 3.3V, to want a 2.5V input to switch the output on. These diode drops weren't such a problem when power supplies were 5V, but I can't see what to do when the total I have to play with is 3.3V. TomArticle: 74494
Thomas, If you read the datasheet you'll find out that the IOB set in PCI33 mode has Vih (min) = 60% of Vccint = 0.6 x 2.5V = 1.5V. There you go.... Cheers, Syms. "Thomas Womack" <twomack@chiark.greenend.org.uk> wrote in message news:AEz*pWWwq@news.chiark.greenend.org.uk... > Is there some easy way I can set up the IOBs so that the FPGA believes > that 0V is a zero and 1.8V a one? Or should I rig up another batteryArticle: 74495
Thomas Womack wrote: (snip) > On the other side of the room, I have some photo-diodes and some > LM324N op-amps. If I rig up an op-amp as a comparator, I can get a > signal which swings from 0V to ... umm ... inspect the datasheet > ... Vcc - 1.5V. > > Is there some easy way I can set up the IOBs so that the FPGA believes > that 0V is a zero and 1.8V a one? Or should I rig up another battery > to increase the supply voltage to the op-amp by 1.5V or so; in that > case I might be setting the input voltage on an FPGA pin to slightly > greater than the supply voltage to the FPGA, which seems likely to > be painful. How about a series diode and pull up resistor to increase by 0.7V? Hopefully not too small of a resistor would be needed. -- glenArticle: 74496
Hi Andre, > "Differential" is the wrong expression. I need > inverted clocks on a 3,3V logic level. Ooops... that complicates things a bit, since LVDS is only 2.5V in a Cyclone, and probably not enough voltage swing as well. I suggest that you use normal I/O pins to generate the clock, or maybe use some external device to make sure that the LVDS I/Os are brought to a level that is acceptable for the recipient. What was your base frequency again, and what is the output frequency? Best regards, BenArticle: 74497
Peter, All three are always running. They are all around 60 MHz. I never switch to a stuck clock, all three clocks come from an external source that is always running. THe idea is to test each of these clocks. Is the best solution to cascade the bufgmuxes then?Article: 74498
Brad, This will work if you declare the state types in a separate package file. JoeArticle: 74499
I suggest you use two cascaded versions of the circuit I published in XCell, and that you can also find in TechXcusives (#6 of Six Easy Pieces). I know and trust that that circuit works even with asynchronous select inputs, and it is very easy to analyze, since everything is out in the open. You need four slices, since each flip-flop has its own clock. I suppose you could do the same thing with two BUFGMUX circuits, but they are not that easy to analyze. The moment you said "free-running", the problem became trivial. But switching away from a dead clock is a real bear... Peter Alfke > From: Jonathan <> > Organization: (none) > Newsgroups: comp.arch.fpga > Date: Tue, 12 Oct 2004 13:53:32 -0700 > Subject: Re: multiplexing clocks > > Peter, > > All three are always running. They are all around 60 MHz. I never switch to a > stuck clock, all three clocks come from an external source that is always > running. THe idea is to test each of these clocks. Is the best solution to > cascade the bufgmuxes then?
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Compare FPGA features and resources
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