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Niels Sandmann wrote: > Jim Granville wrote: > >> Niels Sandmann wrote: >> >>> Hi everyone, >>> >>> I'm considering making a compiler for Atmels FPSLIC (combined >>> microcontroller with FPGA). The idea is to mark expensive funktions, so >>> they can be implemented in the FPGA instead of normal machine code. >> >> >> Sometimes an 'expensive' item might be an operator. >> ie Maths libraries, and their support is one productive area that >> does not need armloads of new software. >> >> > I have experience with microcontrollers and construction of >> compilers, but >> >>> I have only made very small test-projects with a very old FPGA and >>> really buggy software. >>> >>> Is this possible to make such a compiler? >> >> >> almost anything is possible ... >> >>> Does it make sense at all to compile high-level language to a FPGA in >>> this way? >> >> >> depends a lot on the FPGA, and the project, ( and the designer..) >> [ It is also a dangerous tool in the wrong hands....] > > why ? > >>> Has someone else made it/is this normal procedure today ? >> >> >> Someone has mentioned Altera's new C flow ( not cheap ) > > Do you mean their C2H-compiler for the Nios II as Mike Teseler mentioned > in another post ? yes. > >> For good examples of FPGA centric work on other languages, look at > > <snip links> > They are interesting but not exactly what I'm looking for. If you are prepared to contemplate your own language, then you should study these. The ability to write test benches should not be overlooked. >> and for an example of a smaller FPGA-Core, and what can be done >> in core-extension, look at this carefully before commiting to the >> FpSLIC ( which is rather a dead-end pathway ). > > I'm not committed to the FpSLIC in any way. It was just chosen due to my > prior experience with AVR. I guess it is OK to learn on, but the FpSLIC has many drawbacks. The biggest brick wall, is it needs a problem both large enough to need a FPGA (but not _too_ large an FPGA!), and still small enough to fit into the small AVR RAM-code space. -jgArticle: 100451
Niels Sandmann wrote: > Jim Granville wrote: > >> depends a lot on the FPGA, and the project, ( and the designer..) >> [ It is also a dangerous tool in the wrong hands....] > > why ? Simply put, because hardware design is not software design. -jgArticle: 100452
Niels Sandmann wrote: > Tim Wescott wrote: >> I suspect, though, that this would cause problems with concurrency. > > Perhaps. I still don't know which language I will use. Probably I'll > design my own pascal-like language. So I could design the language to > take care of these problems. If your clean slate includes 'fresh langauge', then look at the Structured Text side of IEC 61131 - or, all of IEC 61131. That covers the language(s) set used for Programmable Logic Controllers, so it has a firm basis in the real world of control, and also has high level structure support. -jgArticle: 100453
sachink321@gmail.com wrote: > Thanks, that helps > > i have already gone through CF spec > but one thing tht troubles me is this > > lets suppose there are some files already in a compact flash > im trying to read those files > how will i know at which adresss or at which sector number or LBA is > tht particular file??? > once i know tht particular LBA > i can acceess using read sector commmand > But how will i knw which Sector is tht particular file???? > That's what a file system does for you. You need to store a table somewhere that has the file information. Normally, this is done with a file allocation table or similar in a known place on the storage device. It could also be stored off the device somewhere in the host. If you are doing a data recorder, which was the impression I had, you wouldn't need separate files and could assume the data jsut starts at the beginning of the device. If you are going to be reading existing files, then you need to know how the CF is formatted so that you can find and interpret the file tables.Article: 100454
Another point regarding the latency of the dynamic phase shifting - the data sheet states: "The phase adjustment may require as many as 100 CLKIN cycles plus three PSCLK cycles to take effect, at which point the output PSDONE goes High for one PSCLK cycle." In reality, what does "may require" mean? Is there anything that can be done (eg. through CLKIN or PSCLK frequency selection say) to reduce this 100 CLKIN cycles? Does this "100 CLKIN cycles" vary between devices, with Vcc, temp? I would like to avoid experiments with actual devices during my design phase.Article: 100455
Hi guys, have a question can any1 help me with building a macro????? i have a VHDL design and i have mapped, placed and routed it, but all done automatically (not manual). i need to create this a macro and then replace in a new postion in the FPGA. CAN ANY1 HELP me with the step by step procedure for it. i read the xilinx documents are dint get a clear answer. Do i have to place n route manually to create a macro??? -supermanArticle: 100456
burn.sir@gmail.com wrote: > Having seen way too much spam on this newsgroup lately, I have come > with a possible solution that just might work. > > Add a section to FPGA FAQ where the known names on the newsgroup will > list the companies they recommend (plus some explanation). Next time > someone spams the list about "high quality PCB", or what the hell it > is, we post a polite response saying that no one should support spammer > companies and we suggest you choose another manufacture from the list > below (link to FPGA-FAQ follows).Given that spammers only care about > money, seeing they are loosing customers might stop them from spamming > the list. You're assuming that they actually read any responses :) Still, not a bad plan. JeremyArticle: 100457
Silicon Valley based - Neural Systems Corporation (NSC) has developed a technology called trainable digital logic (TDL), which performs many of the functions performed by artificial neural networks. TDL circuitry typically is significantly simpler and orders of magnitude faster than the equivalent neural network. General purpose TDL pattern recognizers can be constructed using FPGAs or as part of a chip that performs additional functions. Development funding was provided by the Advanced Technology Program of the National Institute of Standards and Technology. Almost all conventional neural networks are implemented on a digital computer where the computer input is a digital word (or words) and the output is binary (or a binary word). Thus, the computer implements what is generally known as a 'switching function'. It is known that all switching functions can be implemented with binary logic. TDL, which uses binary logic, is trained to implement the complicated switching functions that are equivalent to those generated by a neural network computer. During training NSC algorithms specify the logic and architecture in a compact form. Additional FPGA specific algorithms can be used to implement the logic. Conventional neural network algorithms implement large sets of interconnected neuron analogs. Each analog requires much arithmetic, and solutions of non-linear functions. The result is complexity and reduced speed. The TDL, in contrast, uses no arithmetic and no non-linear functions. Typically, it is orders of magnitude faster and significantly less complex. For non-neural network-like applications FPGA based TDL can be used in a similar manner to implement a complex switching function (or switching functions) by training in real time on sets of binary words. Using this approach, the TDL pattern recognizer hardware is capable of making millions of decisions a second. NSC is interested in aiding in the development of products that may contain TDL. For contact information and additional details about the technology visit the NSC Web site at: http://www.neuralsyscorp.comArticle: 100458
Hi Iam trying to synthesize using syn. pro and P&R using ISE. Iam planning to use XIlinx-DCM and generate 66MHz (at which my design works) from 100MHz(osc. freq in board). Now in syn.pro I gave autoconstrain frequency option. The top entity does have clk and inside the code DCM generates clkgen0_xc2v_v_Clk0B. The mul. and div. factor I gave is 2&3. It means my clk(100MHz) is multiplied by 2 and div. by 3 in DCM and I will get 66.66MHz. So in the ucf file I gave for clk 100MHz. While I translate my design in ISE, I get an warning like this. Checking timing specifications ... WARNING:XdmHelpers:681 - UCF definition of specification "TS_clk" overrides the definition found in the netlist or NCF file: UCF: PERIOD "clk" 10000.000000 pS HIGH 50.000000 % netlist/NCF: PERIOD:clk:4159.000000:pS:HIGH:50.000000% INFO:XdmHelpers:851 - TNM "clk", used in period specification "TS_clk", was traced into DCM instance "clkgen0/xc2v.v/dll0". The following new TNM groups and period specifications were generated at the DCM output(s): CLKFX: TS_clkgen0_xc2v_v_Clk0B=PERIOD clkgen0_xc2v_v_Clk0B TS_clk/0.666667 HIGH 50.000000% WARNING:XdmHelpers:662 - Period specification "TS_clkgen0_xc2v_v_Clk0B" references the TNM group "clkgen0_xc2v_v_Clk0B", which contains both pads and synchronous elements. The timing analyzer will ignore the pads for this specification. You might want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads from this group. Checking expanded design ... Why in the generated clock I see TS_clk/0.666667 instead of TS_CLK/1.5 which makes gen. clock to be 66.666MHz. Any help is appreciated, PrakashArticle: 100459
burn.sir@gmail.com wrote:
> I have an Actel design with a 3 clocks. I need to define two of them in
> Synplify (v8.5):
>
> define_clock -name {n:clk2} -freq 20
> define_clock -name {n:clk1} -freq 100
>
>
> This will make Synplify to insert clock buffers in the design:
>
> clk2_keep : CLKINT port map(A => clk2_i, Y => clk2);
>
>
>
> The problem is that the Actel PAR tool "Designer" (v7.1) doesn't like
> these buffers as it will assign the clocks to global clock networks
> anyway:
>
> Error: CMP601: This design has a CLKINT instance 'clk2_keep' driven by
> a clock net which is not needed. Before compiling this design, this
> macro must be removed from the design.
>
>
> How do i get rid of them? I tried to fix this by setting the max fanout
> to a very high value:
> define_attribute {n:clk1} syn_maxfan {200000}
> define_attribute {n:clk2} syn_maxfan {200000}
>
> but it didnt work :(
>
>
> Designer has an option for removing unsued buffers, but I never get to
> the optimization stage. Any suggestions how i can stop Synplify from
> inserting clock buffers or get Designer to ignore the buffer?
>
> regards,
> - Burns
>
>
>
> PS. here are the rest of the constraints
>
> forward annotated from Synplify to Designer (as SDC constraints):
> create_clock -period 50 -waveform {0.000000 25.00000} clk2
> create_clock -period 10 -waveform {0.000000 5.00000} clk1
>
>
>
> additional PDC constraints imported to Designer:
> assign_global_clock -net {clk2}
> assign_global_clock -net {clk1}
>
>
In your GCF file which you import into Designer:
// To assign net to global buffer
set_global clk2;
// Opposite of above
dont_fix_globals;
set_noglobal clk2;
Article: 100460Hi all, I wanted to know how many CLB's does a 8:1 mux implementation take in a ALTERA and a XILINX device. I wanetd the details of the internal implementation also(like how many LUT's )are used. One more doubt i had if the depth of the multiplexer increases can the LUT' s be shared. Regards, PravArticle: 100461
Peter Winkler wrote: > Hi ! > > I would like to use a free microcontroller core on my > Spartan 3 FPGA. > > There are quite some free cores available, but I would like to know > what everybody is using. It would be great if the free core would be > supported by gcc or some other free C-Compiler. There's PIC and Z80 clones on opencores.org. The sdcc compiler could be used for them. PhilippArticle: 100462
Hi, Iam trying to download opensource processor in xilinx dev. board XUPV2P. I'm not using any of the features like (Power PC/ controllers) which are inbuilt / xilinx prop. Now I've a doubt If suppose I configure my bit file thro' USB Jtag interface, should my logic (to be downloaded) contain the JTAG controller also, or the controller is hard coded in the chip. I get a warning while generating programming file in ISE, WARNING:Bitgen:244 - The IEEE1532 option implies that JTAG configuration will be used. Using a StartupClk setting other than JtagClk could prevent proper device startup. Please help esp. the second part of warning, PrakashArticle: 100463
Prakash wrote: > Hi, > Iam trying to download opensource processor in xilinx dev. board > XUPV2P. I'm not using any of the features like (Power PC/ controllers) > which are inbuilt / xilinx prop. > Now I've a doubt If suppose I configure my bit file thro' USB Jtag > interface, should my logic (to be downloaded) contain the JTAG > controller also, or the controller is hard coded in the chip. > > I get a warning while generating programming file in ISE, > WARNING:Bitgen:244 - The IEEE1532 option implies that JTAG > configuration will be > used. Using a StartupClk setting other than JtagClk could prevent > proper > device startup. > Please help esp. the second part of warning, > Prakash > when you generate the bitstream for JTAG programming, you need to check an option startupclk=jtagclk, otherwise (slave serial, or other non JTAG config) you need to have startupclk=cclk or startupclk=userclk) what this means? after configuration (and during configuration) a state machine will take care of the start-up of your design, ie. releasing the global reset, releasing the global tristate for the IOs, assertin DONE pin etc. This option in the bitstream generation will "tell" to the fpga the source of clk for this state machine (this information is embedded into the bitstream file) when impact will program the fpga, impact knows the interface you choose and is checking against the bistream do see is the startup-clk option makes sense for the chosen programing interface. AurashArticle: 100464
hi,
I am using opencores MAC in XUPV2P board. RxClk,RxData[3:0] are
not coming out of LXT972A. What are all the tranceiver registers need
to be set to get the data.
please help me to solve the problem
regards,
Arun
Article: 100465Steve Knapp wrote: > > We're in the process of updating the Spartan-3E numbers and I expect > the mysterious 4's to improve to 6's in the next data sheet release for > LVDS, RSDS, and miniLVDS I/O standards. > Thanks for the update BrianArticle: 100466
I implement the design using xilinx device, and one net has high
fanout, so I duplicate the register, but it does not work, the net
fanout remains the same.
The original code is:
process(clk)
begin
if clk'event and clk = '1' then
regenr <= regen;
end if;
I modified to be:
process(clk)
begin
if clk'event and clk = '1' then
regenr <= regen;
regenr2 <= regen;
end if;
but the timing analyzer still reports that regenr2 has the same fanout
as the regenr did.
I am confused and I wonder whether there was some settings that should
be modified in ISE, or I should add some constraints in UCF file to
achieve this?
Article: 100467Thanks for your reply,and I want to use spartan -3e ,because spartan-3e have the lower cost than spartan3L.the the quiescent power spartan 3e is bigger than spartan3L,except this,I want to know if the dynamic power is the same if I take the same project to each,I also want to know what will effect the de dynamic power(include the design I use and the chip architecture),Thansks!Article: 100468
Is the regenr and the regenr2 have the diffient load, or I think you can set the maxfan attribute in your hdl sourse file?For example(verilog) reg regenr /*synthesis syn_maxfan=32*/;//32 is the max fanout that for example you can add yours instead than the synthesis tools will auto duplicate the registers.also you can set the maxfan for all in the synthesis tool,you can look the synplify online help. Best regrads!Article: 100469
Hi Prav,
"prav" <praveen.kantharajapura@gmail.com> wrote in message
news:1144660513.037870.46910@z34g2000cwc.googlegroups.com...
> Hi all,
> I wanted to know how many CLB's does a 8:1 mux implementation take in
> a ALTERA and a XILINX device. I wanetd the details of the internal
> implementation also(like how many LUT's )are used.
This depends very much on exactly what family you are talking about.
Different device families have different capabilities, and also different
numbers of slices per CLB. You should look at the datasheets for details.
In all Xilinx FPGAs since Spartan-II & Virtex, there are dedicated
multiplexor resources that make 4:1 and larger muxes quite efficient. A
1-bit 8:1 mux will require 4 LUTs to implement the four first-stage 2:1
muxes. Then there are two second-stage 2:1 muxes, which can use an "F5" mux,
and a single final-stage 2:1 mux which can be an "F6".
So the total is 2 slices (the Fx muxes are "free" within the slice). In
older parts that equates to 1 CLB; in anything newer than Virtex-II, that is
0.5 CLB. In any case, this will be a very fast function since the routing to
and from the Fx multiplexors is dedicated.
> One more doubt i had if the depth of the multiplexer increases can the
> LUT' s be shared.
I'm not sure what you mean by that. I *think* the answer is no.
Cheers,
-Ben-
Article: 100470Thanks, I think that , since Iam trying to program by USB Jtag, the warning I got is harmless and in my case its correctly assigned (startupclk=jtagclk). I didnt get an answer for, whether I need to integrate JTAG controller in logic, assign the TMS, TCK...pins or controller is hard coded, and no need to concern in my logic (probably second is right). PrakashArticle: 100471
Hi Niels, I think you are starting a difficult project. In the past I've done some work with the FPSLIC and found that manual merging of hardware with software works best. Since the hardware is accessable as banked I/O registers only, there is a lot of setup overhead involved (especially if you support concurrency). You can't just combine 3 AVR instructions into one and add it as a magic instruction set extension. I achieved actual benefit of the FPGA area by implementing functions with FPGA helper circuit. Initially I created a software-only function for reference. Then I took dissected the inner loop and implemented parts of it as VHDL code, and modified the software to use it. Benchmarks with the software-only implementation helped me decide how much FPGA area to dedicate to acceleration of the function (and also for testing). I developped a concept to handle concurrency, by dividing the FPGA modules into two groups. One is accessable from interrupts, while the other one goes through a semaphore access control. This enabled me to reduce the state to 2 or 3 bytes, which is quick to save/restore on context switches. Note that this was possible only because the FPGA circuits are not randomly called (as in a compiler environment), but manually designed towards a handcrafted assembler code library. Otherwise, solving the concurrency issues would probably have voided all the performance gains. Another problem I encountered was that the PAR wasn't reliable. I frequently got bad bitstreams when the device utilization was high. The problem was probably related to the fact that the PAR tools don't address short paths (hold violations). I wrote extensive self-test software to overcome this problem. You might run into the same thing, if you rely on Atmels tools as backend for your compiler. I suggest you should try to implement a few real-world problems on the FPSLIC to learn about all the issues, before you do the compiler. Regards, MarcArticle: 100472
I try to port processor in xilinx FPGA. The processor code does 've more inputs, outputs, buffers declared in entity. Now while pin assignment in ucf file, if suppose I use only some and left others, without assigning at all , will the ISE assign those left signals to pins automatically. Iam trying to download to development board, which is assigned for some processor/logic. If suppose the tool automatically assign some pins which is not intended, it may cause board problems. Am I right, give some insight, PrakashArticle: 100473
prakash.na@gmail.com wrote: > Hi > Iam trying to synthesize using syn. pro and P&R using ISE. Iam planning > to use XIlinx-DCM and generate 66MHz (at which my design works) from > 100MHz(osc. freq in board). Now in syn.pro I gave autoconstrain > frequency option. The top entity does have clk and inside the code DCM > generates clkgen0_xc2v_v_Clk0B. The mul. and div. factor I gave is 2&3. > It means my clk(100MHz) is multiplied by 2 and div. by 3 in DCM and I > will get 66.66MHz. So in the ucf file I gave for clk 100MHz. While I > translate my design in ISE, I get an warning like this. > > Checking timing specifications ... > WARNING:XdmHelpers:681 - UCF definition of specification "TS_clk" > overrides the > definition found in the netlist or NCF file: > UCF: PERIOD "clk" 10000.000000 pS HIGH 50.000000 % > netlist/NCF: PERIOD:clk:4159.000000:pS:HIGH:50.000000% > INFO:XdmHelpers:851 - TNM "clk", used in period specification "TS_clk", > was > traced into DCM instance "clkgen0/xc2v.v/dll0". The following new > TNM groups > and period specifications were generated at the DCM output(s): > CLKFX: TS_clkgen0_xc2v_v_Clk0B=PERIOD clkgen0_xc2v_v_Clk0B > TS_clk/0.666667 > HIGH 50.000000% > WARNING:XdmHelpers:662 - Period specification "TS_clkgen0_xc2v_v_Clk0B" > references the TNM group "clkgen0_xc2v_v_Clk0B", which contains both > pads and > synchronous elements. The timing analyzer will ignore the pads for > this > specification. You might want to use a qualifier (e.g. "FFS") on the > TNM > property to remove the pads from this group. > Checking expanded design ... > > Why in the generated clock I see TS_clk/0.666667 instead of TS_CLK/1.5 > which makes gen. clock to be 66.666MHz. > > Any help is appreciated, > Prakash It looks like the time spec is a period rather than a frequency, so it should be multiplied by 1.5, not divided by 1.5 going from 100 to 66.667 MHz. i.e. period goes from 10.0ns to 15.0nsArticle: 100474
In general ,I think the tool will aotumatically remove the unused pins in the designs,but we shuld let the unused pins have the proper state,for example iin the ddr sdram if the DQM signals have hardly attached in the borad,if I don't use it in some circumstance,so we must let if high,and if we don't make it the proper state,and the data will be wrong,I don't know if I am right.
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z