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John- > Except that I can flip through a 20-page schematic and not only > understand what it does, I can usually spot hazards and bugs quickly, > sometimes in seconds. Nobody can do that with a few thousand lines of > uncommented HDL. > > Parallel beats sequential, which is what FPGAs are all about. > > And if they call you Gramps, it's easy enough to fire them and hire a > fresh batch. Sure if it's OrCAD, which we use it for complex board designs. Yes you can spot errors fast and things jump out that can save your board desgin. But ISE? A 20 page schematic in ISE is like trying to cut concrete with knife. You can do it, but only if you have a LOT of time on your hands, maybe for example a need to escape from prison :-) -JeffArticle: 99926
Erik Widding wrote:
> How do you handle the case when a local variable (very local, as in
> local to the block) is being used to store a partial calculation?
If there has been a value stored, then what's the problem? It will be
correct when referenced. If however, there may be a value stored, and
contain an undefined value at other times, then there is a programming
error.
> Many coding standards insist that a line of code not wrap (at least as
> a general rule). The point of this is not all variables have a notion
> of state (as in a flop), as they are created locally, assigned once and
> only read once locally. I would assume there are a lot of instances
> where a local variable is used for the readability of the code, rather
> than with the intent of creating another stage in a pipeline. How does
> FpgaC differentiate between variables that are meant to be another
> stage in a pipeline (i.e. a flop) and those that are merely for
> convenience (i.e. a combinatorial node)?
A variable that is always referenced after an assignment, is reduced to
a combinatorial expression, and doesn't get latched in a FF. If the
variable is referenced in a loop, before being assigned in that loop,
then it's latched in a FF.
> Many coding standards insist that global variables not be used, except
> when used as semaphores or in a similarly limited way to share data
> between two threads. As I understand it the few remaining places where
> it is considered acceptable to use a lot of global variables is in
> resource limited (i.e. 8bit micros with little ram) systems. So for
> the most part I would think the "changed outside of the scope" argument
> is moot. Most compilers assume that a variable can not be changed
> outside of the scope unless it is declared VOLATILE. So, I don't buy
> the argument as anything more than a special case.
Similarly, global's in FpgaC are frequently applied to the same coding
standard, for similar reasons. It's isn't however moot, since the value
is global, it may (and most likely is) expected not to change state
magically, just because it was easier for the compiler to cover a
"don't care" that would assign it errantly by including a broader
implicant than the conditionals explictily represent.
> In the usage of variables with scope no more global than the single
> sequential path through the a block, is it more important to take the
> strict ansi-C interpretation that anything declared is implicitly zero,
> and follow the logic tree through; or is it worth understanding when
> the logic has nodes that truly have a "don't care" component and
> optimizing as such?
If there is a don't care, then there is an uninitialized variable case,
which is in correct programming. Show me a clear case where it is not.
> If the possibility to optimize is ignored, I fear you are creating a
> tool that may have some academic interest, but not widespread practical
> use.
There is NOT a possiblity to optimize here that is being ignored. As I
understand your example, you are presenting an undefined variable case,
and wanting to define it as a don't care, which is not correct C, and
has clear side effects which can be wrong.
> I will be the first to admit that I have not played with FpgaC at all -
> and have no intention to. But I assume there have to be pragmas to
> direct the compiler to deal with pipeline and concurrency issues, as
> there is no support in the language for this. Much of the use of a
> sequential language for representing sequential logic has to implicitly
> told to the compiler so that it can understand which variables
> represent combinatorial nodes, and which represent sequential nodes.
While some C based HDL's and HLL's use pragma's to control concurrance
and pipelining, it is not required by the C language definition and
expected sequential semantics. Just as multi-issue processors are free
to concurrently execute multiple statements in parallel, so does FpgaC,
using identical strategies. The limitation to this, is that the
apparent senquencing must be preserved. So in TMCC/FpgaC every block is
assumed to be concurrent, and clocks are observed for looping and
function calls.
In Handel-C they choose to make each statement a cycle, and use "par"
blocks for concurrancy. FpgaC doesn't use that strategy, choosing
instead to make looped blocks a cycle.
In Streams-C they use pragmas to have the compiler automatically unroll
loops and insert any required retiming for the resulting pipeline.
FpgaC doesn't provide that, but offers instead that the programmer may
directly control the degree of unrolling and pipelining by the
structure and sequence of the statements. Pipeline stages are
explicitly created by reversing statement order, in a way that the
pipelines are formed using C semantics. Consider:
fpgac_input iport;
fpgac_output oport;
while(1){
int a, b, c;
a = iport;
b = a;
c = b;
oport = c;
}
this creates a combinatorial from iport to oport, transfering new
values each clock.
pipelines are created by reversing the statement order:
oport = c;
c = b;
b = a;
a = iport;
so that there is no combinatorial chain from iport to oport, but rather
a 4 cycle/stage pipeline where the values in iport require successive
clocks to walk thru a, to b, to c, and finally to oport.
This code is functionally correct executing on an FPGA, with identical
looping/pipeline behavior on a traditional processor. Including any
retiming that may be necessary for references outside a particular
pipeline stage.
> Being only C-like and not actually ansi-C, please enlighten me why it
> is important to hold on to one of the aspects of the language (implicit
> zeros which is not universal across all types of variables in the
> language, just in most cases) that kills efficiency when targetting
> hardware, when so many other aspects have to be bastardized to make the
> use of this language for this purpose even possible?
Actually, the goal for FpgaC is to become a proper subset of ansi-C,
with a few minor additions. And to that end it is NOT correct to
violate certain conventions like zero initialized memory, and making
assignments which are incorrect by the language standard.
I believe you are very wrong here. The efficiency you claim is being
lost, only exists for illegal programming practice of using an
undefined variable value in a poorly (incorrectly) formed statement
sequence.
> I ask, these questions because my cursiosity has been piqued - and I
> obviously clearly don't understand.
I do believe that is the case. Show me a valid programming example
otherwise.
Article: 99927
Eli Hughes schrieb:
> I am having an argument with another guy I work with about the Xilinx
> tools. He only draws his logic with the schematics and I use Verilog/VHDL.
>
> When one enters a design with the schematic entry tool, does the
> schematic get translated to a generic HDL before begin synthesized? The
> argument is over the fact that I don't believe schematic entry gets you
> better control of how your design actually gets implemented in the chip
> (I think its alot less control than an HDL). My contention is that the
> schematic you draw isn't always how the design is implemented in the
> chip. I was was under the assumption that the design gets translated to
> an HDL anyway before synthesis.
>
>
> Does anyone out their know?
>
>
> -Eli
Hi Eli,
The schematics from the XILINX ECS Tool are converted by the sch2hdl
tool to structural hdl. Either verilog or VHDL.
The resulting Files are named *.vhf for VHDL flows (not sure about the
verilog file naming rule).
From the schematic libraries within ECS you can use gates, FFS and
complex functions like counters muxes etc.
These become optimized by e.g. XST into LUTS and FFs etc.
Just for fun: Load a *.sch file and it's resulting *.vhf file into an
editor and see what's really happening.
The question about how much control over the synthesis results you have
from your input file depends on a lot of things.
What style of hdl code are you writing (structural, RTL, behavioral ?)
Do you use attributes in your HDL?
What elements does the schematic guy use? Slice elements (LUTS FFs etc),
simple gates and FFs or complex function blocks?
Does the schematic guy use attributes in his schematic?
Compare your styles and then you can argue about control over synthesis
by the input files.
have a nice synthesis
Eilert
Article: 99928Hi, Thank you all for the answers. I will try the advice of using the patch delivered by Xilinx which I wasn't aware of. JF HassonArticle: 99929
Eric,
Alan is most likely on the right track. The program is slowed down by
printing to the Uart.
Looking at the numbers I'd say the speed of your UART is 115200 baud.
Taking the start and stop bits into account it takes 10 bits to transfer
a character resulting in 11520 characters per second maximum throughput
on the UART. The program prints 15 characters for the start message,
i.e. the program has to wait 14 times before it can print the next
character. Thus, the number of cycles it takes to print the start
message can be calculated by:
14 characters / 11520 characters per second * 300000000 cycles per
second = 364583 cycles
That's pretty close to your measured numbers.
To improve the situation you can:
- use a UART with a buffer (ie. 16550). The hardware will buffer up the
characters and send them at the appropriate time. Works for short strings.
- use an interrupt driven UART, ideally combined with a buffer. Software
and hardware will buffer the characters and send them at the appropriate
time. The buffer in the UART helps to limit to number of interrupts.
- Peter
Eric wrote:
> Hi,
>
> I'm working with a virtex-ii pro board. I don't have previous embedded
> system experience, so I have some wonders about the execution time I
> measured. I use XTime_GetTime() function in xtime_l.h to retrieve the
> execution time of the part I want to take the measurement. The
> following is a simple example I experimented.
>
> // find overhead
> XTime_GetTime(&start_time);
> XTime_GetTime(&stop_time);
> exeTime = stop_time - start_time;
> printf("\n%llu cycles\n", exeTime );
>
>
> XTime_GetTime(&start_time);
> printf("\nstart: %llu\n",start_time);
> for(i=0; i<100; i++);
>
> XTime_GetTime(&stop_time);
> printf("\nstop: %llu\n",stop_time);
> exeTime = stop_time - start_time;
> printf("\n%llu cycles\n", exeTime );
>
> The overhead I got is 210 cycles. For the loop part, if I include both
> printf for start and stop, I got 364740 cycles. If I comment those two
> lines out, I got 513 cycles. So it takes 364740-513=364227 cycles just
> to run printf("\nstart: %llu\n",start_time) and printf("\nstop:
> %llu\n",stop_time) ??? I also did a test that reads and writes a sample
> from the audio codec. The read/write execution time I measured is 1692
> cycles. All programs are running on the 300MHz PPC processor. Are these
> numbers normal to an embedded program? They're just very big to me, so
> I have some doubts. I was getting some 10-digit execution time for some
> complex part of my program. Say, if the program takes 1,000,000,000
> cycles to run, it means it takes (1/300,000,000) * 1,000,000,000 =
> 3.33(s). If anyone can give me some ideas, I'll really appreciate it.
> Thanks.
>
Article: 99930imavroid schrieb: > Thanks for your answer. The "Slice Packing" option in ISE's > Synthesize-XST properties is already set by default but that only makes > synthesis use the LUT#_L primitives. I couldn't find the LUT-Slice > association in any file. A LUT#_L can only connect to components in the same slice so the clustering is implicit. This way you get at least clusters of half slices. You might not get information about how thes half slices are paired when the logic is independant, but in that case placement should really handle the halfs independantly anyway. > In any case, I wish there was a way to generate the netlist of Slices > using already existing tools. Is there a "SLICE" primitive somewhere, > that could be used by synthesis tools? What I'm trying to do is > generate a "uniform" synthesis output (uniform in the sense that only > one module is almost exclusively used). I don't really care whether it > is Xilinx's Slices or some other FPGA vendor's or whatever. Just a > "uniform" netlist output from synthesis. A slice has too many timing pathes and to many configuration options to be a useful primitive for anything but placement. Therefore even if I made the decision to use slices as my placement primitive (which might not be a good choice) I would implement it as a cluster of lower level primitives that describe timing and function. Therefore I doubt that you find a tool that synthesizes to slices. > Any suggestions? Yes, there are acadamic tools that map to LUTs + DFFs. See what University of Toronto has to offer. Kolja SulimmaArticle: 99931
Jeff, if you are talking about virtex4, you have some attributes to play with with PRESELECT_I0 FALSE(default), TRUE PRESELECT_I1 FALSE(default), TRUE you should try to set the PRESELECT_I0 true (to select you always active clock) or try to tie the Sel line to VCC to see if will change the behavior Aurash Jeff Brower wrote: > All- > > I'm using a BUFGMUX but consistently get no output, even though one > clock is always active. I was hoping that if: > > -the always active clock is on I0 > -the possibly active clock is on I1 > -the Sel line was tied to a reg held at zero > > that I would get I0 as output, and later if I1 clock was detected, > logic set the reg and utilize I1. But no luck. > > According to Xilinx doc the BUFGMUX should initialize to I0. I've made > sure the register used for the Sel line is always low. I've tried > connecting the always active clock to both inputs -- that works. I've > read previous posts about BUFGMUX (including Austin and Peter) > explaining that the clock being switched away from must be toggling. > > Is there any other reason why a BUFGMUX would fail to use I0 as output? > > Jeff >Article: 99932
preet schrieb: > I have written the code for my encoder below. It is synthesizable and has no errors. This is good, but does not prove too much. > What i want to do is after programming the FPGA(Spartan3 starter kit), I want to check the results from the harware. > > Means using LEDs for 3 bit output and switch for the input. This might be a nice test (or better call it play around), but a simulation is much better and does show much more. So your "test" isn't a real test, it has no practical relevance. > My code also contains the clock signal. > > IF i lock one switch to Clock and then toggle it's not working and i think it won't. You can't use a normal switch to supply a clock to a digital circuit, especially not a modern FPGA. The switch WILL bounce and produce multiple pulses. A debouncing is necessary, either by hardware (RC-filter + schmitt trigger) or software (logic inside the FPGA) > I want to test this code on hardware. > > Some one suggested Using Picoblaze, RS232,UART connection. > > I really have no clue of how to do it. Looks like you just starting to get into the digital/FPGA business. Start small. Get a simpler circuit thant a Viterby decoder. Get a feeling for simulation and testing in hardware, understand the difference and the idea behind the different ways of testing. For instance, build a simple 4 bit counter. Do a clean simulation. Implement it in hardware. Test it in hardware (use a switch debouncer). Then go on to the Viterby. > Where to get picoblaze, how to program it to take input from RS232, > where to get UART models. And how will i be writing the text in hyperterminal > to send the data through this port.Will i be actually toggling the > switch which i have locked for input. Picoblaze can be found on the Xilinx website, look for xapp213. > I badly need help on this. I think you need to understand some basic concepts first. Regards FalkArticle: 99933
faraz.khan@nssi.us schrieb: > I am working on Xilinx Virtex4 FPGA and need to design a user IP which > will interface to all the external sources like A/D or D/A etc either > over SPI or different standard. My question is what are the points that > i have to keep in mind while desiging such IP. Obviously i will develop > a SPI interface residing on FPGA. Than i have to make sure that the > clock rate is matched with the clock comming from the device. Store the > data and than send it to BRAM for sharing .... How exactly all this > work ??? That always a miracle. ;-) Serious, first you should think about the general concept of your design and not so much about the details. Whats the purpose of this board? (Data aquisition? Digital filter? DSP ?) Whats the main data flow? Whats the main data processing? How should the data processing take place (State machine, embedded procssor, just buffering and processing using external processor/DSP?) And some more. Then you can think about details. You can is microblaze as an embedded processor. This way you need IPs with a bus interface for microblaze. You might want to use on some more or less complex state machines. This way you are free to design you own internal interface. Hope this helps. Regards FalkArticle: 99934
Angelos <aamanat@ee.duth.gr> wrote: >Hi all, >I would like to ask if anyone has implemented a physical usb interface in a >development board of altera that has not mounted a usb inf. >The core for usb1.1 and 2.0 are available but do i need certain physical >layer to implement usb? >I heared that for low speed i dont need to implement anythin just drive the >wires into the fpga but for high speed i need to implement the phy intf. For USB1 1.5 Mbps it can be done with a mcu-PIC, 12 Mbps can proberbly also be accomplished fairly easily. USB2 480 Mbps is another ballgame.. but with enough MHz it maybe will work .. ;)Article: 99935
I have problems programming my EEPROM through JTAG. Most of the times it fails but I have succeeded once. When programming the FPGA directly it works all the time. I am using JTAG Cable Model IJC-2 from Insight The EEPROM is a Xilinx XCF08P The FPGA is a Xilinx Spartan 3 1500K gates What can i try to correct this problem? Is it possible to turn down the speed of the JTAG clock? Thanks Andreas BeierArticle: 99936
Andreas I don't know the cable specifically but I am guessing you have a Parallel Cable III lookalike. These sorts of cable can sometimes be upset by a lowish programming head voltage or long cable runs. Is your target board the one that came with the cable? If not you may need to look at voltages and routing on the board. Have you extended the cable or using a laptop? Laptops sometimes have poorer drive on parallel ports and long cable lengths cause issues too. Impact can change clocking rates but usually Parallel III cables will be running at the lowest rate anyway. John Adair Enterpoint Ltd. - Home of Raggedstone1. The 75€ Spartan-3 Development Board. http://www.enterpoint.co.uk "mughat" <mughat@gmail.com> wrote in message news:e0j15e$rqn$1@news.net.uni-c.dk... >I have problems programming my EEPROM through JTAG. Most of the times it >fails but I have succeeded once. > When programming the FPGA directly it works all the time. > > I am using JTAG Cable Model IJC-2 from Insight > The EEPROM is a Xilinx XCF08P > The FPGA is a Xilinx Spartan 3 1500K gates > > What can i try to correct this problem? > Is it possible to turn down the speed of the JTAG clock? > > Thanks > Andreas Beier >Article: 99937
hi everyone! hwicap can be used in the virtex4 ? I try to use it but the EDK 7.1 tell me : error: MDT - opb_hwicap (opb_hwicap_0) -C:\copy_project\XC4VFX12\EDK_Projects\Custom_Peripheral\system.mhs:321 - not supported for architecture 'virtex4' what wrong with it? who can tell please that is very important to me!!!! thanks advance! xunArticle: 99938
ubelievable, even in EDK 8.1 SP2 hwicap is only supported for V2/V2Pro so you need to edit the ipcore to get it working on V4 :( AnttiArticle: 99939
Hello all, What is the MAIN difference between Xilinx ISE Foundation and Xilinx ISE WebPACK ? Can they both do FPGA design, simulation, place and route, and post-place and route simulations ? They both seem to support the Xilinx FPGAs -RogerArticle: 99940
Also, Webpack is free. ISE Foundation is not free. Very important difference. Now, if that is the only MAIN difference...(I know it is not ;) ) -RogerArticle: 99941
Basically tool wise they are now same as of version 8.1. Used to be a few tools were not in Webpack. The difference is the devices supported. Webpack only supports the smaller end and generally lower end devices. Foundation gives you all the currently recommended for use parts. Some of the buy add-ons may not be available to Webpack as well. John Adair Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan3 Development Board. http://www.enterpoint.co.uk "Roger Bourne" <rover8898@hotmail.com> wrote in message news:1143812030.605492.54770@z34g2000cwc.googlegroups.com... > Hello all, > > What is the MAIN difference between Xilinx ISE Foundation and Xilinx > ISE WebPACK ? > Can they both do FPGA design, simulation, place and route, and > post-place and route simulations ? > > They both seem to support the Xilinx FPGAs > > -Roger >Article: 99942
Dumb question: Since USB is just a two wire serial interface and all the USB solutions I've seen are simple, though speedy, microcontrollers why can't the USB be inside the fpga? Seems like you can instantiate a small micro running at 50 mhz or so with code in a couple block rams to do what the fx2, for example, does. Apparently, doesn't exist so there must be some reason? -Clark "Mike Harrison" <mike@whitewing.co.uk> wrote in message news:37no22duhjkjtns5mh9kvock01039l4tum@4ax.com... > On 30 Mar 2006 09:56:49 -0800, "johnp" <johnp3+nospam@probo.com> wrote: > > >I've used the Cypress FX2 in the past. It has a flexible > >interface that can support byte or word interfaces. They > >used to have sample driver code, I believe they now supply > >only a pre-built driver, you may want to check. > > > >It's a very flexible part, but with the flexiblity comes the need > >for additional design work. > > > >You might look at ?QuickUSB? that has a canned design with > >the FX2, but I'm sure if it can handle full data rates sustained. > > > >John Providenza > > I used quickusb recently - removes the need to get involved in any of the low-level USB stuff at the > PC end, and supports various IO models - 8/16 bit, internal/external addressing, with various fifo > modes and UARTs plus a FPGA bitstream programming mode. Absolute minimum pin count would be 8 data + > 2 control + clock, but you'd probably need at least one extra for framing/handshaking. > http://www.quickusb.comArticle: 99943
There are low inductance 0306 and 0508 capacitor packages that have the terminations on the broad sides rather than the narrow ends. Also putting the capacitor's power and ground vias beside the cap, as close to each other (and the cap) as possible helps cancel effective inductance (minimize loop area), especially compared to vias off each end of the cap. Using a pair of vias on both sides helps even more. Capacitors on the same side of the board should not share vias, but capacitors on opposite sides should (current flow directions cancel). AndyArticle: 99944
I have some doubts about the SPT3E Phase Shifter. First: Data sheet V3.0, pg. 54, fig. 44: CLK180 is wrong. I must start as high! (easy to see) Data sheet V3.0, pg. 57, eq. 6: MAX_STEPS = +/-[integer(20*(TCLKIN-3ns))] For example a 20MHz clock, TCLKIN=50ns MAX_STEPS = +/-[integer(20*47n)] = +/-[integer(940*10E-9)] = +/- 0 Only seeing the "Answer Record: 22414" I understood. How about changing it to: MAX_STEPS = +/-[integer(20*10E9*(TCLKIN-3ns))] ? Now my doubts. What happens when we overflow the Phase Shifter? For the same 20MHz clock, MAX_STEPS = +/-940. And if I shift 941 times (same direction form zero) ? >From the data sheet, PSCLK_FREQ (phase shift frequency input) ranges from 1MHz to 167MHz. For 1MHz: MAX_STEPS = +/-19940 There must be at least 19940 internal delay taps (for each side)! So I can go past 940 (the shifter doesn't know the frequency of the clock, I think). Again the 20MHz clock. As MAX_STEPS = +/-940, the phase shift ranges from 940*20ps=18.8ns to 940*40ps=37.6ns, both below 50ns (TCLKIN). If 940 is the limit, how can the phase shifter, in the fixed mode, cover all the range from 0 to 2*pi (or 360 degrees, if you prefer)? I want to know if there is a way of changing the phase continuously, crossing the borders of +/-2*N*pi smoothly (from 2*pi back to zero). Luiz CarlosArticle: 99945
Andy wrote: > There are low inductance 0306 and 0508 capacitor packages that have the > terminations on the broad sides rather than the narrow ends. Also > putting the capacitor's power and ground vias beside the cap, as close > to each other (and the cap) as possible helps cancel effective > inductance (minimize loop area), especially compared to vias off each > end of the cap. Using a pair of vias on both sides helps even more. > Capacitors on the same side of the board should not share vias, but > capacitors on opposite sides should (current flow directions cancel). > > Andy I'd say 0306 won't buy much in comparison to 0603 as the bonding wire lengths will be defining the loop inductance in both cases. At 1.27 mm pitched BGAs, I drill all pads and put the decouplng capacitors right on the bottom side pads (where power and GND are typically next to one another). The decoupling at higher speeds is done by the (power to GND) plane to plane capacitance, and of course by the on chip decoupling which must have been taken care of by the manucfacturer. Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------Article: 99946
Anyone using this tool from Mentor? If so, any comments about it would be much appreciated. And any comments on how ModelSim + ModelSim Designer compares to Aldec's Active-HDL environment would be even better. I currently own ModelSim but am looking for a more complete environment (testbench automation, graphical tools, code coverage, etc.). Thanks, RobArticle: 99947
Hi Falk thanks for replying. I am using Virtex4FX and primarly my design will have some user logic embedded on the FPGA and PowerPC 405 Core. I am batteling on two fronts... One to make a user logic on FPGA which will deal with all the I/O and process the data. Second to connect this user logic to BRAM for storage so PowerPC can use the data. Things are not so simple as i will also have other user logic also along with this I/O logic which need to be connected to BRAM so they can access the data. I know that BRAM is dual port RAM so only two IPs can be attached. I have to use mux for data and address to make all the IPs access the BRAM as the other port of BRAM will be used by the processor. So leaving this problem aside. I am trying to UNDERSTAND how that I/O logic should be designed to grab all the data comming from outside FPGA. I/O logic will have some registers obviously how can i use these registers and how can i assign address to these. Thanks FarazArticle: 99948
else , if there have another solution for charge the bit for partial reconfigration to remplace the icap?? Antti a =E9crit : > ubelievable, even in EDK 8.1 SP2 hwicap is only supported for V2/V2Pro > so you need to edit the ipcore to get it working on V4 :( >=20 > AnttiArticle: 99949
but in the sit of xilinx , it said the hwicap support the virtex4-fx zhangxun0...@gmail.com a =E9crit : > else , if there have another solution for charge the bit for partial > reconfigration to remplace the icap?? > > Antti a =E9crit : > > > ubelievable, even in EDK 8.1 SP2 hwicap is only supported for V2/V2Pro > > so you need to edit the ipcore to get it working on V4 :( > >=20 > > Antti
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