Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I am working on Xilinx Virtex4 FPGA and need to design a user IP which will interface to all the external sources like A/D or D/A etc either over SPI or different standard. My question is what are the points that i have to keep in mind while desiging such IP. Obviously i will develop a SPI interface residing on FPGA. Than i have to make sure that the clock rate is matched with the clock comming from the device. Store the data and than send it to BRAM for sharing .... How exactly all this work ??? Please guide me on thisArticle: 99901
Do i need to make any interface controller to connect the address and data lines from the IP to mux or its direct connection to muxArticle: 99902
On Thu, 30 Mar 2006 11:53:23 -0800, the renowned John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >On 30 Mar 2006 09:32:50 -0800, "mike_la_jolla" <mdini@dinigroup.com> >wrote: > >>John -- Please, please avoid doing any mission critical or life support >>design. > >Why? What's a *rational* reason why we shouldn't use the clock >deglitcher? It has made the logic perfectly reliable, it makes sense, >it absolutely solves a problem, and it provides a clean, easy, safe >field upgrade: the user replaces an eprom, and if it passes its >powerup checksum, and then the FPGA configures, it's absolutely fixed. > >Terms like "unacceptable" and "good engineering practice" and >"hardware problem" are just dogma. If we've fixed the clock problem to >the point where it has no significant contribution to product MTBF, >what's wrong with the fix? Kluging the boards would be a bigger >reliability hazard, what with parts and wires hanging off. > > >OK: *rational* reason? > >John Jeeze, I wonder why so few real-world issues and solutions are discussed here. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.comArticle: 99903
Erik Widding wrote: <snip> > If a default value is placed into the table, it artificially over > specifies the logic, and will result in a suboptimal result. There is > no problem with equations of no more than four terms as your basic unit > is a 4-lut. But when you start getting into complex state machines > with dozens of terms, this can result in being an order of magnitude > off in utilization in specific areas of a design. I bring this up now, > as the early test cases are going to be simpler, so it may be some time > before you see that there is really a problem. > > So I am not disagreeing with you that FPGAC may not care about this for > now. I am suggesting that you should allow for this future > optimization that you will almost certainly need, by considering that > you should specify your fitter to take as input the additional state of > "don't care". All of the work out of Berkely (espresso, etc) supports > this addional state as it is crucial to quality of result. <snip> I'll expand this a little, by adding that there can also be an 'inferred else' operation, that depends on the register used. Thus a .D ff state engine, will tend to 00000 state, if it hits a non-covered instance, whilst a .T ff state engine will stay where it was. If you want to include glitch/noise recovery, that can matter... -jgArticle: 99904
On 30 Mar 2006 09:56:49 -0800, "johnp" <johnp3+nospam@probo.com> wrote: >I've used the Cypress FX2 in the past. It has a flexible >interface that can support byte or word interfaces. They >used to have sample driver code, I believe they now supply >only a pre-built driver, you may want to check. > >It's a very flexible part, but with the flexiblity comes the need >for additional design work. > >You might look at ?QuickUSB? that has a canned design with >the FX2, but I'm sure if it can handle full data rates sustained. > >John Providenza I used quickusb recently - removes the need to get involved in any of the low-level USB stuff at the PC end, and supports various IO models - 8/16 bit, internal/external addressing, with various fifo modes and UARTs plus a FPGA bitstream programming mode. Absolute minimum pin count would be 8 data + 2 control + clock, but you'd probably need at least one extra for framing/handshaking. http://www.quickusb.comArticle: 99905
Hi, I want to share the BlockRAM between the PowerPC and user logic. I have 4 user logic blocks which would be connected to a data mux and address mux to generate address and data for PORTB of dual port RAM. Q1. How can i generate these address. Are they be generated by the user logic or the address mux has to generate them as control signals. Q2. Are there any known problems connecting PowerPC to BRAM through OCM. Q3. Can i have BRAM connected to PowerPC through OCM and User logic to BRAM through PLB. Q4. If connected as Q3. How can they share the data. Thanks FarazArticle: 99906
mk wrote: >On Thu, 30 Mar 2006 14:08:38 -0500, Eli Hughes <emh203@psu.edu> wrote: > > > >>I am having an argument with another guy I work with about the Xilinx >>tools. He only draws his logic with the schematics and I use Verilog/VHDL. >> >>When one enters a design with the schematic entry tool, does the >>schematic get translated to a generic HDL before begin synthesized? The >>argument is over the fact that I don't believe schematic entry gets you >>better control of how your design actually gets implemented in the chip >>(I think its alot less control than an HDL). My contention is that the >>schematic you draw isn't always how the design is implemented in the >>chip. I was was under the assumption that the design gets translated to >>an HDL anyway before synthesis. >> >> > >There is no translation to an HDL assuming you mean RTL format. The >schematic needs to be converted to textual format (most often EDIF) >but it is just a structural netlist very much like the output of the >synthesis ie LUTs, INIT statements, DFFs, etc only what ever directly >can be mapped to the FPGA. So you get quite a bit more control over >what actually goes into the design than an RTL which needs to be >synthesized. > > Maybe I'm misinterpreting what you wrote here, but I don't think this is true. I have done both schematic and VHDL designs in Xilinx. My current favorite scheme for schematics is to enter the schematics in Protel, generate EDIF files for each sheet, tweak them to be compatible with Xilinx, and add them to the design. (I'm still stuck at ise 5.2, as I need 5 V compatible software.) I found the Xilinx scematic editor to be a HUGE pain. But, either the EDIF way or the Xilinx schematic entry way, the result is NOT LUTs and such, directly. It gets turned into an HDL description of the logic funtionality, for the most part. If you include macros with pre-compiled slices, such as the carry chain or other architecture-specific structures, then those do pass through pretty much directly. But all the other logic is reduced to the boolean equations, and these are then synthesized using the exact same tools as if you had entered the HDL equations in your favorite HDL. As for the original posters comment "My contention is that the schematic you draw isn't always how the design is implemented in the chip." He is exactly right. You can arrange all sorts of trees of gates, but the tools will turn it all into equations, minimize the HELL out of them, and render that logic. Just try throwing in a string of inverters to delay an external signal, for instance, and see what happens! So, I don't think the schematic entry provides any greater control, assuming the FPGA-specific macros like carry chain, DFF, GBUF, are available in your HDL. JonArticle: 99907
Dale, Take a look at the section Fast Simplex Link Interface Description of the mb_ref guide (page 50 in the 7.1 version). And the datasheet DS449 that describes FSL in more detiail. The following MHS fragment might help clear things up a bit. Regards, John # MicroBlaze subsystem ports PORT fsl_incoming_m_clk = fsl_incoming_m_clk, DIR = I PORT fsl_incoming_m_data = fsl_incoming_m_data, DIR = I, VEC=[0:31] PORT fsl_incoming_m_control = fsl_incoming_m_control, DIR = I PORT fsl_incoming_m_write = fsl_incoming_m_write, DIR = I PORT fsl_incoming_m_full = fsl_incoming_m_full, DIR = O PORT fsl_outgoing_s_clk = fsl_outgoing_s_clk, DIR = I PORT fsl_outgoing_s_data = fsl_outgoing_s_data, DIR = O, VEC=[0:31] PORT fsl_outgoing_s_control = fsl_outgoing_s_control, DIR = o PORT fsl_outgoing_s_read = fsl_outgoing_s_read, DIR = I PORT fsl_outgoing_s_exists = fsl_outgoing_s_exists, DIR = O begin microblaze ... PARAMETER C_FSL_PORTS= 1 ... BUS_INTERFACE SFSL0 = my_fsl_incoming BUS_INTERFACE MFSL0 = my_fsl_outgoing ... end # Incoming FSL channel - data from VHDL to microblaze # Slave port connects to MicroBlaze # Master port wired to toplevel ports begin fsl PARAMETER INSTANCE=my_fsl_incoming PARAMETER HW_VER = 2.00.a PORT SYS_Rst sys_rst PORT FSL_CLK = sys_clk PORT FSL_M_Clk = fsl_incmoing_m_clk PORT FSL_M_Data = fsl_incoming_m_data PORT FSL_M_Control = fsl_incoming_m_control PORT FSL_M_Write = fsl_incoming_m_write PORT FSL_M_Full = fsl_incoming_m_full end # Outgoing FSL channel - data from microblaze to VHDL # Master port connects to MicroBlaze # Slave port wired to toplevel ports begin fsl PARAMETER INSTANCE=my_fsl_outgoing PARAMTER HW_VER = 2.00.a PORT SYS_Rst sys_rst PORT FSL_CLK = sys_clk PORT FSL_S_Clk = fsl_outgoing_s_clk PORT FSL_S_Data = fsl_outgoing_s_data PORT FSL_S_Control = fsl_outgoing_s_control PORT FSL_S_Read = fsl_outgoing_s_read PORT FSL_S_Exists = fsl_outgoing_s_exists end dale.prather@gmail.com wrote: > John, > Thanks. This does help a lot. I appreciate your post. I'm still > slightly confused about this master and slave terminology. Myself and > a couple others have been trying to understand it, but it's pretty > convoluted. Is master always an output from microblaze and slave > always an input to microblaze? > > Also, I'm a little confused as to why when I add an FSL to microblaze, > I get a SFSL and a MFSL. This implies that the FSL is bidirectional > when it's stated in the FSL datasheet that it's a unidirectional bus. > Confusing. I wish they would've used terms other than master and > slave. > > I'm assuming the port map you provided above is from the viewpoint of > ublaze? The FLS0_S_READ and FLS0_S_CLK signals are outputs. My > question is, outputs to where? I don't know why they'd go to the VHDL. > They should go to the FSL, as they are the control signals that pop > off the data into ublaze. > > I'm guessing you're in Austrailia? If that's true you're sleeping and > I hope to here from you tomorrow. > > Regards, > Dale >Article: 99908
Erik Widding wrote:
> It is common occurance in code to have a series of independent "if"
> statements with no correponding "else" all operating on the same set of
> variables. Atleast this is common in code that I have written. In
> VHDL and C this can be a very efficient way to code. In either
> language the last assignment wins. And in many such instances, the
> truth table is then only populated with a very small subset of answers.
Actually, there are a small number of implicants, and a large number of
default zeros.
> The remainder of the table can be assumed to have a value of "don't
> care", in many languages this requires a first (or default) assignment
> to the state of "don't care" that may or may not be overridden.
Not true in C. Assuming a don't care, would allow covering a term which
doesn't have an explict implicant, and potentially change a variable
that was remotely set. That brings us to two separate cases:
1) globals always have a default value of zero, so there is never a
don't care for this case.
2) function variables have an undefined value initially, and it's
considered poor programming practice to leave the variable unassigned
before any reference, as the value will have a nondeterminate state
(possibly it's prior state, prior stack contents, but implementation
dependent).
As such, there isn't any asserted term that can properly be a don't
care by your construction in C, as assignments imply implicants, and
lack of assignments/implicants imply retained state (no modification of
the variable).
The design by Dave Galloway (TMCC's author) models this correctly,
using the ffs_zero_at_powerup model. The simple if and nested if
statements are then reduced as follows:
1) if(c) a = b; populates the truth table for "a" with the function
b & c, where b AND c becomes an implicant for "a".
2) if(c1) {if(c2) a = b;} populates the truth table for "a" with the
function b & c1 & c2, where b AND c1 AND c2 becomes an implicant for
"a".
If there are other assignments to "a", it may have other implicants,
including it's self if there is a reference to "a" before it's first
assignment (resulting in a FF with either a gated clock, or feedback
term).
> When minimizing logic into anything other than a fully populated truth
> table the ability to manipulate the "don't cares" can allow for the
> drastic reduction in logic at mapping. Any first year digital design
> course teaches a technique called "Karnaugh Mapping" as an analysis
> tool and visual means for exploring this.
Very true, except that the C model precludes this. Assuming don't
cares, would "create" assignments where there are not implicants in the
current context.
Article: 99909
Hi,
I'm working with a virtex-ii pro board. I don't have previous embedded
system experience, so I have some wonders about the execution time I
measured. I use XTime_GetTime() function in xtime_l.h to retrieve the
execution time of the part I want to take the measurement. The
following is a simple example I experimented.
// find overhead
XTime_GetTime(&start_time);
XTime_GetTime(&stop_time);
exeTime = stop_time - start_time;
printf("\n%llu cycles\n", exeTime );
XTime_GetTime(&start_time);
printf("\nstart: %llu\n",start_time);
for(i=0; i<100; i++);
XTime_GetTime(&stop_time);
printf("\nstop: %llu\n",stop_time);
exeTime = stop_time - start_time;
printf("\n%llu cycles\n", exeTime );
The overhead I got is 210 cycles. For the loop part, if I include both
printf for start and stop, I got 364740 cycles. If I comment those two
lines out, I got 513 cycles. So it takes 364740-513=364227 cycles just
to run printf("\nstart: %llu\n",start_time) and printf("\nstop:
%llu\n",stop_time) ??? I also did a test that reads and writes a sample
from the audio codec. The read/write execution time I measured is 1692
cycles. All programs are running on the 300MHz PPC processor. Are these
numbers normal to an embedded program? They're just very big to me, so
I have some doubts. I was getting some 10-digit execution time for some
complex part of my program. Say, if the program takes 1,000,000,000
cycles to run, it means it takes (1/300,000,000) * 1,000,000,000 =
3.33(s). If anyone can give me some ideas, I'll really appreciate it.
Thanks.
Article: 99910All- I'm using a BUFGMUX but consistently get no output, even though one clock is always active. I was hoping that if: -the always active clock is on I0 -the possibly active clock is on I1 -the Sel line was tied to a reg held at zero that I would get I0 as output, and later if I1 clock was detected, logic set the reg and utilize I1. But no luck. According to Xilinx doc the BUFGMUX should initialize to I0. I've made sure the register used for the Sel line is always low. I've tried connecting the always active clock to both inputs -- that works. I've read previous posts about BUFGMUX (including Austin and Peter) explaining that the clock being switched away from must be toggling. Is there any other reason why a BUFGMUX would fail to use I0 as output? JeffArticle: 99911
Eli- I'm not sure what synthesizers do with schematic translation -- minimized and optimized, or rendered faithfully with precise control -- but I can tell you a few other reasons why schematic entry other than top level with modules (good documentation practice) is not a good idea. The main one is there is just no support. Try asking Xilinx to help with issues regarding schematic entry and see what happens. Another one is the thing quickly becomes huge and out of control. Page after page and easy to overlook a misconnected line on one of those 32-bit busses or muxes. The third one -- my favorite -- is the 20-something engineers you work with will call you Gramps and ask you where's your DOS editor and Tektronix analog scope for that beast :-) -JeffArticle: 99912
> > One even more basic problem. The minimum input frequency for the DCM is 24 > MHz. > Hi Falk, Not if you only use the CLKFX output. Then the minimum is 1MHz. Cheers, Syms. p.s. A DS2188 might be a cheap and easy way to attenuate your jitter. I've used them in the past.Article: 99913
I want to upgrade my EDK and ISE to 8.1 version from 7.1 versions.I am using linux OS. I want to ask those who have already upgraded to edk 8.1 in linux.Do I need to uninstall the 7.1 version before going ahead with the 8.1 installation or can I just go ahead and install 8.1 and then change the $XILINX and $XILINX_EDK Paths? Thanks, NiteshArticle: 99914
Hi, Does synopsys design compiler perform a TILOS based circuit optimization. TILOS is a iterative circuit sizing tool, published in 1985 by fishburn and dunlop. any information and details about this is requested. thanks, MahalingamArticle: 99915
Mike, Thanks so much for giving me this info. But where to get picoblaze from? Do you have a sample code, which explains how to actually program picoblaze to receive input from RS232. And how about connections between picoblaze and UART, how to do that. Have you got the data, text file FORMAT, that we need to give on Hyperterminal to feed in the input? Please give me pointers or links, or if you can explain more. I am novice in this, but need help. thanks and regards PreetArticle: 99916
A friend of mine looked into using the QuickUSB module for a project, but had to reject it because it radiated noise at too high a level for his application. He was doing some analog signal sampling/generation and the noise from the module would have been a killer. John ProvidenzaArticle: 99917
Thanks so much to all who replied to my previous messages I appreciate your concern. Please help me on this. I have written the code for my encoder below. It is synthesizable and has no errors. What i want to do is after programming the FPGA(Spartan3 starter kit), I want to check the results from the harware. Means using LEDs for 3 bit output and switch for the input. My code also contains the clock signal. IF i lock one switch to Clock and then toggle it's not working and i think it won't. I want to test this code on hardware. Some one suggested Using Picoblaze, RS232,UART connection. I really have no clue of how to do it. Where to get picoblaze, how to program it to take input from RS232, where to get UART models. And how will i be writing the text in hyperterminal to send the data through this port.Will i be actually toggling the switch which i have locked for input. I badly need help on this. thanks and regards Code: module encoder(outp,clk,res,inp); input clk,res,inp; outp[2:0] outp; reg [4:0]ff; always@(posedge clk) begin if(res) ff[4:0]<=5'b0; else begin ff[3:0]<=ff[4:1]; ff[4]<=inp; end end assign outp[0]=ff[4]^ff[2]^ff[0]; assign outp[1]=ff[4]^ff[3]^ff[1]^ff[0]; assign oupt[2]=ff[4]^ff[3]^ff[2]^ff[1]^ff[0]; endmoduleArticle: 99918
fpga_toys@yahoo.com wrote: > Erik Widding wrote: > > The remainder of the table can be assumed to have a value of "don't > > care", in many languages this requires a first (or default) assignment > > to the state of "don't care" that may or may not be overridden. > > Not true in C. Assuming a don't care, would allow covering a term which > doesn't have an explict implicant, and potentially change a variable > that was remotely set. That brings us to two separate cases: > > 1) globals always have a default value of zero, so there is never a > don't care for this case. > > 2) function variables have an undefined value initially, and it's > considered poor programming practice to leave the variable unassigned > before any reference, as the value will have a nondeterminate state > (possibly it's prior state, prior stack contents, but implementation > dependent). > > As such, there isn't any asserted term that can properly be a don't > care by your construction in C, as assignments imply implicants, and > lack of assignments/implicants imply retained state (no modification of > the variable). How do you handle the case when a local variable (very local, as in local to the block) is being used to store a partial calculation? Many coding standards insist that a line of code not wrap (at least as a general rule). The point of this is not all variables have a notion of state (as in a flop), as they are created locally, assigned once and only read once locally. I would assume there are a lot of instances where a local variable is used for the readability of the code, rather than with the intent of creating another stage in a pipeline. How does FpgaC differentiate between variables that are meant to be another stage in a pipeline (i.e. a flop) and those that are merely for convenience (i.e. a combinatorial node)? Many coding standards insist that global variables not be used, except when used as semaphores or in a similarly limited way to share data between two threads. As I understand it the few remaining places where it is considered acceptable to use a lot of global variables is in resource limited (i.e. 8bit micros with little ram) systems. So for the most part I would think the "changed outside of the scope" argument is moot. Most compilers assume that a variable can not be changed outside of the scope unless it is declared VOLATILE. So, I don't buy the argument as anything more than a special case. In the usage of variables with scope no more global than the single sequential path through the a block, is it more important to take the strict ansi-C interpretation that anything declared is implicitly zero, and follow the logic tree through; or is it worth understanding when the logic has nodes that truly have a "don't care" component and optimizing as such? If the possibility to optimize is ignored, I fear you are creating a tool that may have some academic interest, but not widespread practical use. I will be the first to admit that I have not played with FpgaC at all - and have no intention to. But I assume there have to be pragmas to direct the compiler to deal with pipeline and concurrency issues, as there is no support in the language for this. Much of the use of a sequential language for representing sequential logic has to implicitly told to the compiler so that it can understand which variables represent combinatorial nodes, and which represent sequential nodes. Being only C-like and not actually ansi-C, please enlighten me why it is important to hold on to one of the aspects of the language (implicit zeros which is not universal across all types of variables in the language, just in most cases) that kills efficiency when targetting hardware, when so many other aspects have to be bastardized to make the use of this language for this purpose even possible? I ask, these questions because my cursiosity has been piqued - and I obviously clearly don't understand. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 99919
I think this piece of news is relevant with respect to recent discussions: http://www.eetimes.com/news/design/showArticle.jhtml?articleID=184417200Article: 99920
On Thu, 30 Mar 2006 17:04:14 -0600, Jon Elson <jmelson@artsci.wustl.edu> wrote: >chip." He is exactly right. You can arrange all sorts of trees of gates, >but the tools will turn it all into equations, minimize the HELL out of >them, and render that logic. Just try throwing in a string of inverters >to delay an external signal, for instance, and see what happens! To do a delay with a string of buffers, you can either persuade the compiler to not strip the intermediate nets, or, more fun, use gates for the string and connect the other inputs to something that really doesn't matter, but is too complex for the optimizer to understand! Like a string of ANDS, with all the side inputs connected to an i/o pin that has a pullup, so that the optimizer doesn't know you never pull it down. There could be a whole family of "fool the compiler" techniques. JohnArticle: 99921
On 30 Mar 2006 16:18:55 -0800, "Jeff Brower" <jbrower@signalogic.com> wrote: >Eli- > >I'm not sure what synthesizers do with schematic translation -- >minimized and optimized, or rendered faithfully with precise control -- >but I can tell you a few other reasons why schematic entry other than >top level with modules (good documentation practice) is not a good >idea. The main one is there is just no support. Try asking Xilinx to >help with issues regarding schematic entry and see what happens. >Another one is the thing quickly becomes huge and out of control. >Page after page and easy to overlook a misconnected line on one of >those 32-bit busses or muxes. The third one -- my favorite -- is the >20-something engineers you work with will call you Gramps and ask you >where's your DOS editor and Tektronix analog scope for that beast :-) > >-Jeff Except that I can flip through a 20-page schematic and not only understand what it does, I can usually spot hazards and bugs quickly, sometimes in seconds. Nobody can do that with a few thousand lines of uncommented HDL. Parallel beats sequential, which is what FPGAs are all about. And if they call you Gramps, it's easy enough to fire them and hire a fresh batch. JohnArticle: 99922
Error : iMPACT 1208 : -'1' Boundart-Scan chain test failed at bit
position 1
A problem may exist in the hardware configuration.
Check that the cable, scan chain, and the power connections are intact,
that the specifed scan chain configuration matches the actual hardware,
and that the power supply is adequate and delivering the correct
voltage.....
Hi ,
I am newly using the Xilinx Spartan 3 FPGA starter kit, all
these days when I used to switch on the kit I used to see the RED LED's
glow one after the other and was able to see the "SPARTAN 3 STARTER
KIT" running on the SEVEN SEGMENT LED display, I tried to download some
code into the FPGA/ PROM , wanting to see some output, during trying to
do that also the board was displaying the messages but now all of a
sudden the FOGA KIR is not displaying the messages and I am getting the
above error......
Could anybody please tell me what could be the problem......is it that
by any chance my board is dead and my 99$ are burnt :-(((..............
Please help.........
Short of Words,
Regards,
Bakul
Article: 99923
Eric wrote:
> I'm working with a virtex-ii pro board.
...
> The overhead I got is 210 cycles. For the loop part, if I include both
> printf for start and stop, I got 364740 cycles. If I comment those two
> lines out, I got 513 cycles. So it takes 364740-513=364227 cycles just
> to run printf("\nstart: %llu\n",start_time) and printf("\nstop:
> %llu\n",stop_time) ???
Actually, the stop_time printf isn't included since it is after
XTime_GetTime.
The serial io has a busy wait in it. Perhaps it is taking extra time
to write to the serial port.
> I also did a test that reads and writes a sample
> from the audio codec. The read/write execution time I measured is 1692
> cycles. All programs are running on the 300MHz PPC processor. Are these
> numbers normal to an embedded program? They're just very big to me, so
> I have some doubts. I was getting some 10-digit execution time for some
> complex part of my program.
Are you running from sdram? Are caches on?
sdram is very slow and caching can make a huge difference on it.
Are you compiling -O3? Unoptimized code means more slow sdram
accesses.
Alan Nishioka
Article: 99924mahalingamv@gmail.com schrieb: > Hi, > > Does synopsys design compiler perform a TILOS based circuit > optimization. > > TILOS is a iterative circuit sizing tool, published in 1985 by fishburn > and dunlop. > > any information and details about this is requested. > > thanks, > > Mahalingam > Hi Mahalingam, your question is a little off topic for this newsgroup. But anyway... have a look at this page: https://buffy.eecs.berkeley.edu/PHP/resabs/resabs.php?f_year=2005&f_submit=one&f_absid=100834 It's a short example of what TILOS does compared to dc. If you want to find out wether an actual version of dc can do the trick or not, give it a try (or ask the synopsys guys ;-) ) Enter the design and set a constraint on the power consumption of the circuit. See if the optimization results change with lower vaues for the power constraint. Don't forget to check your technical libraries wether they support cells with different drive strenght or not. have a nice synthesis Eilert
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z