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On Wed, 29 Mar 2006 18:09:18 -0800, John Larkin wrote: > On Thu, 30 Mar 2006 01:17:10 GMT, Joerg > >>Hello John, >> >>> We did my original #2 suggestion, a tapped delay line driven from the >>> pin, driving an r-s flipflop. Set the flop if all the taps are 1s, >>> clear it if all are 0s. Sort of a poor man's 1-bit FIR lowpass filter. >>> The delay line is a string of eight buffers, about 10 ns overall. >>> >>> We'd have done Peter's circuit if we'd learned of it sooner. >>> >>> It's interesting that my post evoked two classes of response: >>> >>> 1. It can't be done, don't do it, kluge the boards (also the official >>> Xilinx response!) >>> >>> 2. Yes, and here are my ideas on how you could do it/how I've already >>> done it/interesting asides. >>> >>That probably depends on what kinds of projects the individual responders >>usually work on. In my field (medical) I could lose my shirt if I did the >>digital de-glitcher thing. If it's an application where nothing bad can >>happen when it chokes or where that condition will always be signaled it >>might be different. But I wouldn't do it. >> > If your application is critical, one could argue that you are in fact > obligated to do this to increase clock noise immunity. > > But we're just testing jet engines. > I've heard they can be pretty nasty if they overspeed and blow up. Thanks, RichArticle: 99876
John -- Please, please avoid doing any mission critical or life support design.Article: 99877
I'd like to support full USB 2.0 transfer speeds. Example driver source would be critical in the intrest of saving time. "John_H" <johnhandwork@mail.com> wrote in message news:k8UWf.4376$kg.544@news02.roc.ny... > USB 2.0 at 480 Mbps? 12 Mb/s? > The PLX NetChip 2272 is an okay device for 480 Mbps though I dislike the > asynchronous interface. I don't know if they have driver source > available. http://www.plxtech.com/products/NET2000/default.asp > > I'd love to see a better option! > > "Brendan Illingworth" <billingworth@furaxa.com> wrote in message > news:6tSdnV0slP-AkLHZRVn-rA@comcast.com... >> Hello All, >> >> I am looking for a time efficient means to add USB capability to a >> Virtex-4 LX80. After looking around it seems that there are several >> third party solutions that require minimal number of interface I/Os (a >> byte wide data interface and a three wire serial control interface). >> However, I thought it would be a good idea to see if anyone with >> experience might suggest parts to avoid and parts that are recommended. >> Ideally what I would like to find is a part that requires less than about >> 20 FPGA I/Os to interface to and provides example driver source >> implementing a transfer of a single block of continously addressed >> memory. >> >> Thanks for any suggestions, >> Brendan > >Article: 99878
faraz.khan@nssi.us wrote: > Hi considering me a novice. I have a very basic question. How can i > connect multiple user IPs to a shared memory on FPGA. Step one is to instance the synthesis modules into a schematic or hdl source file and wire them up. -- Mike TreselerArticle: 99879
On 30 Mar 2006 09:32:50 -0800, "mike_la_jolla" <mdini@dinigroup.com>
wrote:
>John -- Please, please avoid doing any mission critical or life support
>design.
And your credentials ?:-)
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Article: 99880I've used the Cypress FX2 in the past. It has a flexible interface that can support byte or word interfaces. They used to have sample driver code, I believe they now supply only a pre-built driver, you may want to check. It's a very flexible part, but with the flexiblity comes the need for additional design work. You might look at ?QuickUSB? that has a canned design with the FX2, but I'm sure if it can handle full data rates sustained. John ProvidenzaArticle: 99881
On 30 Mar 2006 09:17:14 -0800, faraz.khan@nssi.us wrote: >Hi considering me a novice. I have a very basic question. How can i >connect multiple user IPs to a shared memory on FPGA. I am using Xilinx >Virtex 4 FX FPGA and want to have a common memory place on chip where >i can save all the signal comming from out side. This common place will >also be used to share the output signal between the custom IP. I am >planning to use BRAM for this purpose but since BRAM is dual port so i >can have only two of the IP attached to it at any time. Please advice >me since this issue is halting my design process. I also want to attach >the processor to that shared memory so it can also share the signals >with rest of user logic residing on FPGA. I am using on chip processor >PowerPC405. > >Thanks > >Faraz What you need is a mux. A mux is a piece of hardware which take all the outputs from all IPs and forwards only one of them to its output based on a control signal so that you can write that value to the memory. Of course the control signal should be wide enough so that you can indicate all the inputs ie if you have 8 input, you need a 3 bit control signal. You also need to tell each IP block that their output is consumed and you can accomplish that with decoding the control signal and using the decoded values to enable each IP block (or use it as a read signal etc.) HTH.Article: 99882
fpga_toys@yahoo.com wrote: > Phil Tomson wrote: > > What format is the truth table in? (BLIF, PLA, some other internal data > > structure) > > Currently just a 2^n bit table, with a linked list for the associated > var's. > Does this bit table represent two or three states per bit? (i.e. True, False, or True, False, Don't Care) While on a sequential processor it might not make sense to worry about the don't care state and simply enumerate the table, in logic it can make a very big difference. You have probably already thought of this. The use of "bit" just threw up a red-flag for me, as the bit type in C generally has only two states. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 99883
On 3/30/06 9:52 AM, in article 0n6o22lurduasr3836mgrqmi4l27i2eo98@4ax.com, "Jim Thompson" <To-Email-Use-The-Envelope-Icon@My-Web-Site.com> wrote: > On 30 Mar 2006 09:32:50 -0800, "mike_la_jolla" <mdini@dinigroup.com> > wrote: > >> John -- Please, please avoid doing any mission critical or life support >> design. > > And your credentials ?:-) > > ...Jim Thompson Don't answer him. He just likes to see who can piss the farthest.Article: 99884
Brendan Illingworth wrote: > I'd like to support full USB 2.0 transfer speeds. Example driver source > would be critical in the intrest of saving time. What driver you use depends on what USB Device Class you choose for your device. -aArticle: 99885
On Thu, 30 Mar 2006 10:06:12 -0800, Don Bowey <dbowey@comcast.net>
wrote:
>On 3/30/06 9:52 AM, in article 0n6o22lurduasr3836mgrqmi4l27i2eo98@4ax.com,
>"Jim Thompson" <To-Email-Use-The-Envelope-Icon@My-Web-Site.com> wrote:
>
>> On 30 Mar 2006 09:32:50 -0800, "mike_la_jolla" <mdini@dinigroup.com>
>> wrote:
>>
>>> John -- Please, please avoid doing any mission critical or life support
>>> design.
>>
>> And your credentials ?:-)
>>
>> ...Jim Thompson
>
>Don't answer him.
>
>He just likes to see who can piss the farthest.
OK ;-)
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Article: 99886"Angelos" <aamanat@ee.duth.gr> writes: |> Hi all, |> |> I would like to ask if anyone has implemented a physical usb interface in a |> development board of altera that has not mounted a usb inf. |> |> The core for usb1.1 and 2.0 are available but do i need certain physical |> layer to implement usb? |> |> I heared that for low speed i dont need to implement anythin just drive the |> wires into the fpga but for high speed i need to implement the phy intf. If you need a High Speed (480 Mbit/s) USB 2.0 interface, it is probably safest and least trouble to pick an existing integrated PHY such as http://www.smsc.com/main/catalog/gt3200.html MarkusArticle: 99887
Hi, I compiled the GTKWave 1.3.86 for Windows (win32 with Gtk 2.0) and put the files and instructions at http:www.dspia.com/gtkwave.html It has all the DLLs which are needed (I hope). Just unzip-untar it to a directory. Currently it assumes it will run in c:\gtkw which you have to add to your path. If you put it somewhere else, you need to do the following: * add you gtkwave root directory to your path (ie path=c:\gtkw;%path%) * cd gtkw\pango\ * pango-querymodules.exe > ..\etc\pango\pango.modules I have made no changes to any sources. To get it to compile I did the "obvious" thing. Install Mingw, get 1.3.86 sources and add files from Gtk for Win32 collection till it compiles. I hope it is useful to others too. Muzaffer Kal kal at dspia dot com http://www.dspia.com/cur-default.htmlArticle: 99888
Erik Widding wrote: > fpga_toys@yahoo.com wrote: > > Currently just a 2^n bit table, with a linked list for the associated > > var's. > Does this bit table represent two or three states per bit? > (i.e. True, False, or True, False, Don't Care) It's bivalued, since that is the only defined number set for C boolean operations, logicals, and arithmetics used by C. Multivalued sets have little value otherwise for FpgaC. > While on a sequential processor it might not make sense to worry about > the don't care state and simply enumerate the table, in logic it can > make a very big difference. You have probably already thought of this. Because the boolean and arithmentic operations are defined as bivalue operations, nothing else is necessary for FpgaC > The use of "bit" just threw up a red-flag for me, as the bit type in C > generally has only two states. Which, is enough. Even for boolean and arithmetics for other HDL and HLL's RTL generation. Extended sets for simulation, fuzzy logic, tristate busses, and other domains is a completely different problem.Article: 99889
I am having an argument with another guy I work with about the Xilinx tools. He only draws his logic with the schematics and I use Verilog/VHDL. When one enters a design with the schematic entry tool, does the schematic get translated to a generic HDL before begin synthesized? The argument is over the fact that I don't believe schematic entry gets you better control of how your design actually gets implemented in the chip (I think its alot less control than an HDL). My contention is that the schematic you draw isn't always how the design is implemented in the chip. I was was under the assumption that the design gets translated to an HDL anyway before synthesis. Does anyone out their know? -EliArticle: 99890
G=F6ran Bilski wrote: > It depends on how your application execute. > Do a "mb-objdump -S" and look at the code. > What program is initialized into the BRAM in the bitstream? > Do you download your program using XMD and then execute it? > > > G=F6ran I got it to work now, thanks. The problem was the delays between switching diodes on and off were too long, so Chipscope was displaying the waveform of one delay (I was mistaken that the problem ende, when instead the program was in the idle for-loop). That's why I wasn't seeing the instructions for loading values into diode register. Thanks for your help! InesArticle: 99891
On Thu, 30 Mar 2006 14:08:38 -0500, Eli Hughes <emh203@psu.edu> wrote: >I am having an argument with another guy I work with about the Xilinx >tools. He only draws his logic with the schematics and I use Verilog/VHDL. > >When one enters a design with the schematic entry tool, does the >schematic get translated to a generic HDL before begin synthesized? The >argument is over the fact that I don't believe schematic entry gets you >better control of how your design actually gets implemented in the chip >(I think its alot less control than an HDL). My contention is that the >schematic you draw isn't always how the design is implemented in the >chip. I was was under the assumption that the design gets translated to >an HDL anyway before synthesis. There is no translation to an HDL assuming you mean RTL format. The schematic needs to be converted to textual format (most often EDIF) but it is just a structural netlist very much like the output of the synthesis ie LUTs, INIT statements, DFFs, etc only what ever directly can be mapped to the FPGA. So you get quite a bit more control over what actually goes into the design than an RTL which needs to be synthesized.Article: 99892
On 30 Mar 2006 09:32:50 -0800, "mike_la_jolla" <mdini@dinigroup.com> wrote: >John -- Please, please avoid doing any mission critical or life support >design. Why? What's a *rational* reason why we shouldn't use the clock deglitcher? It has made the logic perfectly reliable, it makes sense, it absolutely solves a problem, and it provides a clean, easy, safe field upgrade: the user replaces an eprom, and if it passes its powerup checksum, and then the FPGA configures, it's absolutely fixed. Terms like "unacceptable" and "good engineering practice" and "hardware problem" are just dogma. If we've fixed the clock problem to the point where it has no significant contribution to product MTBF, what's wrong with the fix? Kluging the boards would be a bigger reliability hazard, what with parts and wires hanging off. OK: *rational* reason? JohnArticle: 99893
On Thu, 30 Mar 2006 17:29:58 GMT, Rich Grise <richgrise@example.net> wrote: >On Wed, 29 Mar 2006 18:09:18 -0800, John Larkin wrote: >> On Thu, 30 Mar 2006 01:17:10 GMT, Joerg >> >>>Hello John, >>> >>>> We did my original #2 suggestion, a tapped delay line driven from the >>>> pin, driving an r-s flipflop. Set the flop if all the taps are 1s, >>>> clear it if all are 0s. Sort of a poor man's 1-bit FIR lowpass filter. >>>> The delay line is a string of eight buffers, about 10 ns overall. >>>> >>>> We'd have done Peter's circuit if we'd learned of it sooner. >>>> >>>> It's interesting that my post evoked two classes of response: >>>> >>>> 1. It can't be done, don't do it, kluge the boards (also the official >>>> Xilinx response!) >>>> >>>> 2. Yes, and here are my ideas on how you could do it/how I've already >>>> done it/interesting asides. >>>> >>>That probably depends on what kinds of projects the individual responders >>>usually work on. In my field (medical) I could lose my shirt if I did the >>>digital de-glitcher thing. If it's an application where nothing bad can >>>happen when it chokes or where that condition will always be signaled it >>>might be different. But I wouldn't do it. >>> >> If your application is critical, one could argue that you are in fact >> obligated to do this to increase clock noise immunity. >> >> But we're just testing jet engines. >> > >I've heard they can be pretty nasty if they overspeed and blow up. > >Thanks, >Rich > I saw one partially assembled at the P&W maintanance training facility. It was a 70,000 pound thrust fanjet, with about a 12' diameter front fan. Just outside the scoop is a roughly 2 foot wide, 14' diameter, 4" thick kevlar-epoxy band, nice translucent amber. If the thing throws a blade, it's supposed to catch it. They *do* test this, revving up the engine (I think they spin it with an electric motor) and using explosives to break the blades off the hub. I'd love to see that test. I'm just finishing up a VME tach/overspeed shutdown module for GE. It *will* be responsible for not blowing up engines. JohnArticle: 99894
The criticism I've heard most is the lack of hardware memory management (from the LINUX community on www.niosforum.com) but I honestly I don't know how much of Altera's customer base shares the same point of view. Pressuring Altera for multithreaded support, the expected response would be to implement a slave processor. I like that people are trying to use it as a full blown processor and it is nice to see the same features as a regular processor. DerekArticle: 99895
I have used USB 1 devices from http://www.ftdichip.com/ in the past. In terms of the FTDI PC driver the simplest route was to use their PC driver that makes the USB port look like a COM/serial port. I.e your PC application doesn't need to know anything about USB. At the USB device end the FTDI chips can present a serial or parallel IO inteface that you would attach to your FPGA. This is a very quick way to get USB into your product, but you do take the unit cost hit of the FTDI USB chip. I'm sure the latest FTDI devices are USB 2 compliant, but I don't know if they support USB Hi-Speed(480Mbit/s) or just "USB Full Speed" (approx 8mbit/s). A USB 2 device does not have to support HiSpeed. "I'd like to support full USB 2.0 transfer speeds" - ummm do you want to support USB 2 Full speed = 8mbit/s or do you want to support the max USB 2 speed = Hi Speed = 480 mbit/s. Regards Andrew Andy Peters wrote: > Brendan Illingworth wrote: > > I'd like to support full USB 2.0 transfer speeds. Example driver source > > would be critical in the intrest of saving time. > > What driver you use depends on what USB Device Class you choose for > your device. > > -aArticle: 99896
Joseph H Allen wrote:
> I'm know the rules and take advantage of bug-free synthesis tools. For
> example:
> always @(posedge clk)
> begin
> x <= 1; // x is a flip flop
> q = input + 3; // q is a wire
> if (condition)
> q = q + 1;
> if (other_condition)
> x <= q;
> end
> This Verilog has perfectly defined behavior, but many ASIC designers can't
> deal with it because of their experience with buggy tools (no mixed
> block/unblocking assigns, no non-blocking assignments to the same register).
Yes. This works fine.
If others don't use it, that's to your advantage.
Note if you name the block, you can declare
your wire inside it:
always @(posedge clk)
begin : my_block
reg q; // q is a wire
-- Mike Treseler
Article: 99897Hello John, >> >>That probably depends on what kinds of projects the individual >>responders usually work on. In my field (medical) I could lose my shirt >>if I did the digital de-glitcher thing. If it's an application where >>nothing bad can happen when it chokes or where that condition will >>always be signaled it might be different. But I wouldn't do it. >> > If your application is critical, one could argue that you are in fact > obligated to do this to increase clock noise immunity. > If you have to live with a clock that comes in via a noisy channel, yes. Just not to fix an on-board problem. In medical the lawyers would be all over us if something happens and an expert witness finds out. Regards, Joerg http://www.analogconsultants.comArticle: 99898
fpga_toys@yahoo.com wrote: > Erik Widding wrote: > > fpga_toys@yahoo.com wrote: > > > Currently just a 2^n bit table, with a linked list for the associated > > > var's. > > Does this bit table represent two or three states per bit? > > (i.e. True, False, or True, False, Don't Care) > > It's bivalued, since that is the only defined number set for C boolean > operations, logicals, and arithmetics used by C. Multivalued sets have > little value otherwise for FpgaC. > > > While on a sequential processor it might not make sense to worry about > > the don't care state and simply enumerate the table, in logic it can > > make a very big difference. You have probably already thought of this. > > Because the boolean and arithmentic operations are defined as bivalue > operations, nothing else is necessary for FpgaC > > > The use of "bit" just threw up a red-flag for me, as the bit type in C > > generally has only two states. > > Which, is enough. Even for boolean and arithmetics for other HDL and > HLL's RTL generation. Extended sets for simulation, fuzzy logic, > tristate busses, and other domains is a completely different problem. John, I think I may have done a poor job communicating the issue. So I will offer a little more detail. It is common occurance in code to have a series of independent "if" statements with no correponding "else" all operating on the same set of variables. Atleast this is common in code that I have written. In VHDL and C this can be a very efficient way to code. In either language the last assignment wins. And in many such instances, the truth table is then only populated with a very small subset of answers. The remainder of the table can be assumed to have a value of "don't care", in many languages this requires a first (or default) assignment to the state of "don't care" that may or may not be overridden. When minimizing logic into anything other than a fully populated truth table the ability to manipulate the "don't cares" can allow for the drastic reduction in logic at mapping. Any first year digital design course teaches a technique called "Karnaugh Mapping" as an analysis tool and visual means for exploring this. If a default value is placed into the table, it artificially over specifies the logic, and will result in a suboptimal result. There is no problem with equations of no more than four terms as your basic unit is a 4-lut. But when you start getting into complex state machines with dozens of terms, this can result in being an order of magnitude off in utilization in specific areas of a design. I bring this up now, as the early test cases are going to be simpler, so it may be some time before you see that there is really a problem. So I am not disagreeing with you that FPGAC may not care about this for now. I am suggesting that you should allow for this future optimization that you will almost certainly need, by considering that you should specify your fitter to take as input the additional state of "don't care". All of the work out of Berkely (espresso, etc) supports this addional state as it is crucial to quality of result. This is me trying to constructively offer an example to the earlier suggestion I made that "what you want to do [in the area of reconfigurable computing] is a whole lot more similar to the current use of the devices than you realize." This post is intended to be supportive. If you have taken it any other way, please simply ignore it. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 99899
John Larkin wrote: > On 30 Mar 2006 02:32:08 -0800, bill.sloman@ieee.org wrote: > > >> It's interesting that my post evoked two classes of response: > >> > >> 1. It can't be done, don't do it, kluge the boards (also the official > >> Xilinx response!) > > > >I think I'm in that catagory, though I'd describe my response as saying > >that it shouldn't be done in software - if for no other reason than > >that the dwell time at 1.2V eats into your timing error budget - > > It doesn't. We're running a 300 MHz FPGA at 16 MHz. Pushing the clock > edges a few ns one way or the other doesn't matter. I've heard that one before. > If you reject a concept out of hand, you're not likely to subsequently > contribute interesting ideas on how to implement it. Not knowing the Fpga or what you were doing with it, I was never likely to contribute anything interesting on that front anyway. > >and > >that the time you'd already spent on looking for a software solution > >should have been enough to find one (which turns out to have been > >correct). > > It was. And if we'd waited a few hours, we'd have used Peter Alfke's > circuit, which preserves clock edge timing and is quite a bit more > elegant than our atrocity. Peter is the senior-stateman Xilinx app > engineer (he wrote a lot of their appnotes) and he invented his > deglitch thing on the spot for us. Our "official" Xilinx fae was a #1 > type, "it shouldn't and can't be done." > > I met Peter at the now-departed Foothill Electronic Flea Market, where > we both had our heads inside a big cardboard box of old books. After > that intimacy, we naturally started talking, and he convinced me that > we should dump Actel for Xilinx. He even told me where to get the > student version of the software cheap! He had a great line: "I can > tell by your hair that you'll prefer schematic entry." He seemed to be the top guru on comp.arch.fpga when I last looked. I've referenced him on sci.electronics.design from time to time - Tues, Mar 2 2004 5:55 am would be the most recent one. It looks as if I first ran into him in 1997. > >> 2. Yes, and here are my ideas on how you could do it/how I've already > >> done it/interesting asides. > > > >Granting that I was fixated on the hardware solution, I did suggest how > >you might hack the board, based on a problem that I'd been a party to, > >many years ago. > > The coax hack wouldn't work, for the exact reason we have trouble with > the existing clock net: the xo can't put enough voltage into a 50 ohm > line. Besides, the hack would be hideous. If anything is truly > "unacceptable" around here, it's ugly boards. The VMTX55 coax is remarkably discreet, particularly if you glue it down. You might use some kind of buffer to drive it - whence my transistors. If the Fpga could accept LVDS signal levels, you wouldn't need anything like as much voltage swing and might get away with something really evil, like a resistive divider. -- Bill Sloman, Nijmegen
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