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Marco T. wrote: > Hallo, > I should measure the frequency of an input signal. > Max frequency of signal is 100 KHz. > > I have made a simple system to detect rising edge of input signal using a > flip flop. > It samples the input signal every system clock cycle. > To measure the input frequency I count the number of system clock periods > between two rising edges of input signal. For more precsiion, you can divide the Fu, before doing the time capture. Or, you can set up to capture a wide-timebase counter, and NOT reset the counter between captures - then you have the option to choose Cycles in SW, and the time is done by subtract, and you do not loose any time-ticks, so have best precision. > > To test the system I' using a function generator. > > Reading the data acquired (using a fixed frequency) I have watched that > every 5-10 datas there is an error. > The number aquired is about 50% or 75% less than the others. 50% less is explained by false triggers on the wrong edge, 75% less is harder to explain, unless you are over more than one cycle ? > > Using a pull up resistor will be solved the error? > > Otherwise I need a system that verify glitches? Hardware solution is to add a Schmitt trigger, and maybe also a RC filter. SW patch is to read multiple captures, and reject ones that suddenly 'step' from previous readings. -jgArticle: 100751
It may be $178 from European distribution; the www.em.avnet.com site shows $149. I may have a cookie set that says I'm a US locale. My S3E kits (ordered a while ago) had a few dollars shipping - not much considering the "usual" charges. "Carsten" <xnews1@luna.kyed.com> wrote in message news:v0l7429lmup3425ikl1d713ke1cgsc3n51@4ax.com... > > Guyzz > > I Was just checkking if the S3E was available at the Xilinx Store but > it still isn't. They refer to Avnet , but there it costs $178. > > Those $28 would be the shipping from Xilinx , so i hope Avnet is > shipping for free. > > Else those $28 + maybe more shipping would "hurt" for a private VHDL > learner. > > I am from from Europe , and wonders if the shipping is also more from > Avnet ???. > > Any places in Europe where the S3E kit is available for £149 ??? > > > Regards > CarstenArticle: 100752
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:4443f8f0@clear.net.nz... > You have not asked how to program them yet, which might be > the most important question :) > You will need to generate code, and also get the code into the chips.... > ( which I believe are OTP ) > > -jg Some of the classic parts had the clear window on ceramic parts. But they *all* required the dedicated Altera programmer (or 3rd party programmer with appropriate adapter) and were not in-system programmable. We're talking 27 years ago. There are better options. I imagine you could get people to pay you to take inventory off their hands if they still have some lying around... they're worth *that* much!Article: 100753
> Some of the classic parts had the clear window on ceramic parts. But they > *all* required the dedicated Altera programmer (or 3rd party programmer with > appropriate adapter) and were not in-system programmable. We're talking 27 > years ago. I was going to get some information before I made the leap ... And we are not talking big money here ... something like $20 bucks for all 200 or so chips But you raise a good point ... I need to be sure my device programmer can handle it (I have a BP MICRO and a TOP 2048) ... and that I would not need to invest in any new hardware or software (pal/pld assembler/ compiler) Thanks again for the heads upArticle: 100754
> http://www.altera.com/literature/ds/classic.pdf Thank you very much!Article: 100755
Mike Harrison schrieb: > Doesn't have to be small, just differently targeted - e.g. Digikey, > Mouser. Kolja Sulimma wrote: > Those carry only a portion of the devices, usually stocking them. I need > someone who also orders parts with long lead time for me, but without > whining that I only want 100 parts. Digikey apparently does that for TI these days. When you order samples on the TI web site, they're processed by Digikey. The paperwork all says "TI", but it's from Digikey's address. Presumably TI makes sure that Digikey is able to fill sample orders even for parts Digikey doesn't normally stock. Or maybe TI still does some of their own fulfillment when it's for items Digikey doesn't stock. Since Digikey is already a Xilinx distributor, and since they already do a great job of dealing with small orders, this would seem to be a much more logical arrangement than having Avnet do it. Anyhow, Digikey seems to to at as good or better a job as Avnet at stocking Xilinx parts. If you click on the parts listed in the Xilinx "store" and wind up on the Avnet page, almost everything is listed as "out of stock", and a lot of valid device/package combinations simply aren't listed at all. One gets the impression that Avnet only stocks the Xilinx parts for which they're already getting large customer orders. That's not surprising, and I'm not criticizing them for it, but it's not the ideal modus operandi for an online web store intended to service small orders. On the other hand, I haven't had any trouble buying starter kits and eval boards from Avnet. EricArticle: 100756
Austin Lesea wrote: > engineers for decades have used components "outside" of their stated > specifications. > > The 'penalty' for being caught, is that the manufacturer may state > that the usage is not covered by the specifications, and thus, not > guaranteed. lecroy7200 wrote: > That was my question. Is this the level of support we would expect > from Xilinx? Depends on who "we" are. If you buy $10K of Xilinx parts per year, I expect they're not going to go as far out of their way to support you as if you buy $10M per year. Like any other business, Xilinx has finite resources available to support customers, and has to devote them in such a way as to maximize return. That's part of their fiduciary responsibility to their shareholders. If a small customer wants to deliberately use a part outside its specs, the answer is probably "you're on your own", but if i vary big customer wants it, they can probably get Xilinx to have engineering resources assigned to validating and/or qualifying the part at the desired specs. That said, in my experience Xilinx does a very good job of supporting small customers, within the limits of what can reasonably be expected. EricArticle: 100757
samiam wrote: > I am about to stock up on 200 of these chips ... and would jump at the > opportunity if they are ANYTHING like the 22v10 ... You're about to waste your money, IMNSHO. Especially if you don't already have a universal programmer that can handle them. And waste time having to UV erase them. They're sorta like a PAL between the PAL20xx and PAL22V10. But they're way inferior to something like an XC9500 series CPLD. > Basically I need to stock up on these for my hobby work and I am being > offered an unbelievable price on them. If they're free, they're too expensive. (If a deal seems too good to be true, it probably is.) You can buy a brand-shiny-new Xilinx XC9536 in a PLCC for $3.30, quantity one from Digikey. That has 36 macrocells, and is way better than any of the old EPxxx parts. The XC9536XL part is 3.3V and costs even less. And they're supported with current development software, and are in-circuit programmable (no expensive "universal programmer" or UV erasing necessary). I'm sure Altera must make some nice inexpensive CPLDs these days too. I've got scads of old EPLDs from various vendors, some of which were quite nice parts *BACK THEN*, but I wouldn't dream of using any of them even for hobby work today. Life's too short to spend it fighting obsolete chips to save spending a dollar or two on a better, well- supported modern part. EricArticle: 100758
lecroy7200@chek.com wrote: > > At 9:04 Ian states ".. you will create a 750MHz, ah.." Interrupted by > H.J. > > If they ran it using DDR mode, I would think they would not have made a > point to call out the 750MHz clock. > Thanks for the detailed timeline; although the clock on the nearby slide is labeled '750 MHz LVDS', shortly after that "ah..", H.J. refers to the 750 MHz as an "output rate". Also, there's a link on the video page to the Xcell article: http://www.xilinx.com/publications/xcellonline/xcell_56/xc_pdf/xc_gigasample56.pdf which says: "For a 1.5 GHz sample rate, the conversion data will be output synchronous to a 750 MHz clock. Even at this reduced speed, FPGA memories and latches would not be able to accept this data directly. It is therefore beneficial to make use of a DDR method, where data is presented to the outputs on the both the rising and falling edges of the clock (Figure 4). Although the data rate remains the same for DDR signaling, the clock frequency is halved again to a more manageable 375 MHz" BrianArticle: 100759
Carsten wrote: > I Was just checkking if the S3E was available at the Xilinx Store but > it still isn't. They refer to Avnet , but there it costs $178. > > Those $28 would be the shipping from Xilinx , so i hope Avnet is > shipping for free. I ordered the HW-SPAR3E-SK-US from Avnet on 5-Apr, and received it on 12-Apr. I was charged $149 plus $12.29 sales tax plus $12.82 shipping and handling to get it from Avnet to me via Fedex ground service. I wasn't charged anything for shipping from Xilinx to Avnet; it's not customary for the end purchaser to pay for that. I have no idea what they'll charge for shipping to Europe, but if it's $28 that sounds reasonable. EricArticle: 100760
Steve- > Until the POR is released, all I/Os not actively involved in > configuration are high-impedance. The HSWAP_EN pin controls whether or > not internal pull-ups are applied to these I/Os. When HSWAP_EN = High, > the I/Os are turned off. Also, the pull-ups connect to their > associated power rail so you won't see the effect until VCCO ramps up. Except for the S3 errata about "if HSWAP_EN input is high, pull-up resistors are momentarily enabled on User-I/O at end of Configuration" which I believe only hints at the magnitude of the problem we saw on Spartan 3s in mid-2005. On one board with ACQ revision XC3S1500-676, the I/O pins are forced high enough to produce a 1.5V output on lines with 1k pull-down resistors, and this condition lasted more than 100 msec prior to DONE assertion. On boards with revision ECQ and later parts, we don't have the problem so it looks like it has definitely been fixed. But this brings up a question we've had about S3s for a long time: what is the actual pull-up R value? I had heard from our local FAE that the pull-ups are not true Rs, but a "pseudo-transistor" method is used. Thanks. -JeffArticle: 100761
Steve- Sorry, I got corrected here... those revisions should be AFQ (exhibits pre-DONE outputs) and EGQ (no pre-DONE outputs). -JeffArticle: 100762
There is nothing "pseudo" about the pull-up transistor that functions as a pull-up resistor. Almost all so-called resistors on modern CMOS chips are really transistors (p-channel for pull-up), with their geometries chosen appropriately for the desired impedance (or resistance if you will). On-chip resistors are extremely unpopular... Peter AlfkeArticle: 100763
Marco T. wrote: > Hallo, > I should measure the frequency of an input signal. > Max frequency of signal is 100 KHz. [... snip ...] There is a frequency coutner reference design for Spartan-3E Starter Kit board. http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm#frequency_counter I'm not sure how low in frequency that you want to go, but it does measure from ~50 kHz to 100s of MHz. It also uses the PicoBlaze 8-bit embedded controller macro. [ADV]: Spartan-3E Starter Kit board http://www.xilinx.com/s3estarter [ADV]: PicoBlaze Controller http://www.xilinx.com/picoblaze --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 100764
Jeff Brower wrote: > Steve- > > > Until the POR is released, all I/Os not actively involved in > > configuration are high-impedance. The HSWAP_EN pin controls whether or > > not internal pull-ups are applied to these I/Os. When HSWAP_EN = High, > > the I/Os are turned off. Also, the pull-ups connect to their > > associated power rail so you won't see the effect until VCCO ramps up. > > Except for the S3 errata about "if HSWAP_EN input is high, pull-up > resistors are momentarily enabled on User-I/O at end of Configuration" > which I believe only hints at the magnitude of the problem we saw on > Spartan 3s in mid-2005. On one board with ACQ revision XC3S1500-676, > the I/O pins are forced high enough to produce a 1.5V output on lines > with 1k pull-down resistors, and this condition lasted more than 100 > msec prior to DONE assertion. Spartan-3 pull-up and pull-down resistors are much stronger than in previous FPGA families. In previous families, they were on the order of 20-50k ohms. > > On boards with revision ECQ and later parts, we don't have the problem > so it looks like it has definitely been fixed. >From the XC3S1500 errata notice ... http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=-1210888 ... it appears that the "pull-ups active during end of configuration" issue was fixed on parts marked with either "AGQ" or "EGQ". In other words, essentially anything built with the "GQ" process/fab code. The errata also has diagrams indicating how to determine which device you have. The "EGQ" is the current silicon. Table 3 in the errata notice describes which issues were in the early and later silicon revisions. > But this brings up a question we've had about S3s for a long time: > what is the actual pull-up R value? I had heard from our local FAE > that the pull-ups are not true Rs, but a "pseudo-transistor" method is > used. The equivalent resistance is actually specified in the data sheet. See Table 32 on page 56 in specific. http://www.xilinx.com/bvdocs/publications/ds099.pdf The actual measurement is a current, which equates to a resistance. The "resistor" is as Peter described in ... http://groups.google.com/group/comp.arch.fpga/tree/browse_frm/thread/b8a43f2bf79e9491/97ca8a520cfd0b3b?rnum=1&hl=en&_done=%2Fgroup%2Fcomp.arch.fpga%2Fbrowse_frm%2Fthread%2Fb8a43f2bf79e9491%2F6d8f92cbcdcf403f%3Flnk%3Draot%26hl%3Den%26#doc_422b86b865e6c456 For example, the equivalent pull-up "resistor" when powering a bank for 3.3V, is between 1.27k and 4.11k ohms. The equivalent pull-down "resistor" is between 1.75k and 9.35k ohms. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 100765
> If the fanout of the select is your biggest problem, don't "buffer"
> those signals but replicate the registers. You need to talk the
> synthesizer into leaving the replicated logic in your design; in
> SynplifyPro I'd use the syn_preserve directive to keep those replicated
> registers in my design.
So what you are suggesting is duplicate the registers in the code
and tell the synthesizer not to optimize it. Is there any way we can
force the synthesizer to do both.
> If you can pipeline your 50:1 mux you can keep the performance and the
> simple mux structure rather than time-multiplexing a multiplex which...
> shouldn't produce any net benefit.
This is not possible as i am not allowed to introduce any pipeline
stages.
Article: 100766> > Thanks for the detailed timeline; although the clock on the nearby > slide is labeled '750 MHz LVDS', shortly after that "ah..", H.J. > refers to the 750 MHz as an "output rate". > > Also, there's a link on the video page to the Xcell article: > http://www.xilinx.com/publications/xcellonline/xcell_56/xc_pdf/xc_gigasample56.pdf > > which says: > "For a 1.5 GHz sample rate, the conversion data will be output > synchronous to a 750 MHz clock. Even at this reduced speed, > FPGA memories and latches would not be able to accept this data > directly. It is therefore beneficial to make use of a DDR method, where > data is presented to the outputs on the both the rising and falling > edges of the clock (Figure 4). Talking with National, they stated that when running the Virtex 4 at 750MHz that they saw about a 20 deg. C rise. Other than this they saw no problems. They saw no reason to run the part in this mode and switched. It sounds like the board still supports both modes. I guess the video was right, but they had a change in heart.Article: 100767
All-
Inside an always block, I have to search a bitfield in an array of
registers and note it's position in a table. So I did this:
for (i=0; i<32; i++) begin
for (j=0; j<32; j++) begin
if (a[j][4:0] == i)
marker[i][j] = 1'b1;
else
marker[i][j] = 1'b0;
end
end
but XST appears to be doing something different with the integer
comparison than what I'm expecting, possibly sign-extending both sides
to 32-bits. Is there a way to "typecast" an index? Is something like
this a valid approach:
if ( {0, a[j][4:0]} == i ) ...
Thanks.
-Jeff
Article: 100768We never had problems ordering from NuHorizons, either from their web site or from the local rep. We typicaly order SP3 in quantity of 160 every 3-4 months but ordered less (50) for our first prototype batches. We also order other parts from them in similar quantities. Just like any other distributor, you sometime have to wait for the parts to be in stock but so far we never had to wait more than 6 weeks for SP3s. One thing with NuHorizons, they do charge a minimum for shipping that is quite high if you order only 1-10 parts. Patrick Robin http://atelierrobin.netArticle: 100769
Hi, I have been unable to find any info/guidelines for PCB placement of the DCI reference resistors. I.e. the resistors that attach to VRN and VRP. My instinct says decoupling capacitors highest priority (closest to FPGA package), DCI resistors next priority, and everything else lowest priority. How senstive to noise are the VRP/VRN inputs? FPGA is XC3S200-4FT256 and I'm using 49R9 DCI reference resistors. Regards AndrewArticle: 100770
Quartus SignalTap (and ISE equivalent ChipScope) are a truly awesome
tools, however I ran into something strange.
As part of my design I interface an SRAM (this is the Nios Dev kit,
Cyclone Ed.), and thus have a net like
module main(...
inout wire [31:0] fse_d,
output reg sram_oe_n,
...
reg [31:0] fse_d_out;
assign fse_d = sram_oe_n ? fse_d_out : 32'hZZZZZZZZ;
....
but in the captured data fse_d is shown changing one cycle after
fse_d_out. Is this delay an expected bus turn around associated with a
tristate bus?
Just to be sure I understood this correctly, I added an
wire [7:0] fse_d_out_plus_1 = fse_d_out + 1;
and it does show up as expected, synchronous with fse_d_out, in the trace.
BTW everything, including SignalTap, is synchronized to the same 200 MHz
clock synthesized with a PLL.
Thanks
Article: 100771Tommy Thorn wrote: > but in the captured data fse_d is shown changing one cycle after > fse_d_out. Is this delay an expected bus turn around associated with > a tristate bus? When's sram_oe_n changing? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 100772
Many Thanks to Everyone! MarcoArticle: 100773
Hello, I want to attach an FPGA to a micro controller and therefore I'm looking for methods how to do this. Is there more than memory mapped, any where an overview? Bye TomArticle: 100774
Thomas Reinemann wrote: > Hello, I want to attach an FPGA to a micro controller and therefore > I'm looking for methods how to do this. Is there more than memory > mapped, any where an overview? That depends totally on the function that the FPGA will be performing, and also to some extent the micro that you're using! More info please! Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
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