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I found this was clock source issue, the PLL for mmu clock (on the FPGA
board) would appeared clock glitch in low frequency (12 MHz~ 30MHz) .
As I used a simple crcuit for verifying as below,
#############################################
always @(negedge rst_n or posedge clk_in)
if ( !rst_n ) begin
toggle_signal <=1'b0;
end else begin
toggle_signal <=~ toggle_signal;
end
#############################################
I found the toggle_signal also changed in falling edge, and check the
pll source in logic
analyzer, found there was glitch occured.
Share some experience with you all.
Article: 100701Hi Jacques, i totaly agree with you. sorry my english is too poor, i can't write all i think !... effectively, there is a minimum order on Avnet France too .. and they don't sell directly with a credit card ... if i want some parts for my personnal use.. i can't now ! :( only digikey ... if anybody know how create & manage a petition ... let's go ! thank's philippe <jaxato@gmail.com> a écrit dans le message de news: 1145194584.152053.110350@g10g2000cwb.googlegroups.com... Hi Philippe, I am totally for that. Like im sure if we could get like 10,000s names, then we would have achieve something. I was thinking about how they took the decision of removing the online shop. Just recently, I noticed that they added the PROM section to the online shop. This lend me to believe that at one point, they were actually promoting and saw a future for online shopping, but something happened that made them took a 180 degrees U turn. I wouldnt be surprised if in late March 2006, the big bosses of Xilinx and Avnet had lunch in one of these fancy and they decided: Hey let's do something really bad, let's take out the online shop. And I am pretty sure that it was instigated by Avnet. Yesterday, I was checking out their shipping policy and the way they do business for international customers. Avnet ask that you purchase a minimum order of $500, if you are from outside the states or canada. Cmon people, you would get 50 x XC3S100 for that price and this isnt prototyping anymore. Then, when I think that Xilinx advertise on their site, in big, brite and bold: "World´s Lowest Cost FPGAs - now available in prototyping quanties from Avnet"... ironical isnt it, makes me wonder where we are heading. Lets face it, we have a problem here and we should find a solution, and quick. Now, Peter and al, you should advise us of the possible moves that we've got in order to replace or convice your bosses of getting back our dear online shop. >From a previously happy canadian customer. JacquesArticle: 100702
"Hans" <hans64@ht-lab.com> wrote in message news:F5p0g.114$iB1.53@newsfe7-win.ntli.net... > "Ron Baker, Pluralitas!" <stoshu@bellsouth.net.pa> wrote in message > news:tPk0g.4939$3W1.1547@tornado.socal.rr.com... >>> >>> I am not sure why you say systemc is lower level. >> >> You raise an interesting point. Systemc is basically >> an extension of c++. > > It is more than an extension to C++, it includes a cycles based simulator > and VCD dumping support. > >> C++ is a software language >> and not even a high level software language per >> the traditional description. > > IMHO C++ is a high level language, why do you think it isn't? First considering C: http://www.advogato.org/article/759.html "Is C a "high-level" language? Most would say not" http://en.wikipedia.org/wiki/High-level_language "Many programmers today might refer to C as low-level, as it still allows memory to be accessed by address, and provides direct access to the assembly level." http://en.wikipedia.org/wiki/C_programming_language "C is sometimes referred to (and not always pejoratively) as "high-level assembly" or "portable assembly". It is also sometimes referred to as a mid-level language." And it could be argued that C++ is high level. It's kinda moot. > >> (C has been described >> as 'portable assembler'.) When one writes in >> Systemc much of what one is writing are things that >> I recognize as being internal to traditional simulators >> such as Modelsim and nc-verilog. >> In those senses SystemC is low level. > > Check out the appendix in the OSCI SystemC userguide, if you want you can > use HDL style programming for SystemC. > >> >> Being low level like that it is less constrained >> and allows more abstract/behavioral coding. >> Abstract/behavioral coding can be considered >> high level. >> >>> I have the opposite >>> impression. Also there are systemc synthesizers. >> >> Interesting. Can you name some? > > What about Catapult-C, Agility, Forthe? Cool. Thanks. > >> I asked the prof about that and he gave no >> indication that there were such. > > And he is a "prof" in.............:-) > >> I can imagine that there would be synthesizers >> for SystemC but I would expect they would >> be distinctly limited in the range of possible contructs >> that can be synthesized. > > Check out the (not yet ratified) synthesisable SystemC subset. I've done some more googling and have found some things on that. > >> >>> It's also quite a bit >>> faster to simulate. >> >> Interesting. In my minimal experience so far >> it seems slower to compile but faster >> to run. And now that I think about it, run time >> is more critical. >> >>> As someone who writes C++ models using a >>> self-developed fixed-point class library, I welcome systemc. >> >> Interesting. >> >> Another thought that comes to mind is regarding >> graphical debugging tools. With a traditional >> HDL and simulator one can probe and graphically display >> internal signals. I haven't seen that capability with >> SystemC. > > Check out Modelsim, you get nearly the same capability as the supported > HDL languages, in addition you can display transactors in the next > upcoming 6.2 release. I assume NCSim and others will or have the same > capability. Interesting. Sure, that makes sense. The versions of Modelsim I have access to don't support SystemC but it only makes sense that newer versions would. Then that makes me wonder if you loose the simulation speed advantage of SystemC when you use it with a graphical simulator. (But maybe I'm wrong about SystemC being faster. http://en.wikipedia.org/wiki/SystemC says: "The performance of this simulation kernel is not to be compared with that of commercial VHDL/Verilog simulators at the present.") > >> What I've seen so far is like the earliest >> crude HDL simulators that only had text based output. >> If you've got a complete, working, self-checking testbench >> that's just fine. All it has to do is print 'Pass' or 'Fail'. >> But in order to produce a testbench a graphical display >> of internal signals is essential. > > Even the free OSCI simulator support VCD dumping, run your simulation, log > the signals then use free GTKView or Dinotrace to display them. Interesting. Yes, I will look into the VCD. > > SystemC is not perfect (check out the error messages, what a pain!) but > unless Accellera start making noises about SystemVHDL/HypherVHDL or > whatever they call it SystemC is very suitable for testbenches and high > level modeling. Mixing HDL and SystemC is very easy (at least in Modelsim) > and will give you goodies like constraint random/transaction level > modelling and a dead easy C interface :-) > > Hans > www.ht-lab.com Cool. Thanks for your comments. I checked out your web page too. Pretty good. -- rbArticle: 100703
Hello all, I take one of the ports as type Boolean in a VHDL module using Xilinx ISE. The code synthesizes and would also translate and map, but for post PAR simulation, Modelsim is sullen on type mismatch between component and entity for concerned Boolean port. It seems that VITAL simprim libraries do not support Boolean ports. Please share your experience. Regards, YZArticle: 100704
There is a "dirty trick" that allows you to live with a glitch on the falling clock edge, when you really want to trigger only on the rising clock edge: Take the clock input, invert it, and use it then as Count Enable on your counter. That disbles the counter while the clock is High, plus a little bit beyond, and thus masks the double transition of the falling clock edge. You may have to add some delay to the Count Enable input. This is a BandAid, the proper solution is to terminate the clock line, so that you do not get the glitch. Peter Alfke, Xilinx Applictions. Occasionally also helping an Altera user in distress...Article: 100705
All-
I cannot seem to coax XST to infer a distributed RAM -- I believe it
should find a simple, single-port, asynchronous read instance, but I
continue to get the dreaded rejection notice "N flip-flops were
inferred for signal <mem>. You may be trying to describe a RAM in a way
that is incompatible with block and distributed RAM resources available
on Xilinx devices..."
I have included a simplified version of my code below.
Is the word "assign" necessary for output? I would think not since
the output is still continuous / combinatorial.
If anyone has suggestions for key syntax that I'm missing...
-Jeff
reg [1:0] index;
reg [3:0] mem [3:0]; /* declare RAM to hold series of 4-pin IO array
values */
integer i, j;
always @(posedge clk) begin /* store mem values */
if (reset)
index = 0;
else
index = index + 1;
for (i=0; i<4; i=i+1)
mem[i][index] <= IO_array[i];
end
/* use mem values */
always @( id[0], id[1], id[2], id[3],
mem[0], mem[1], mem[2], mem[3],
st_num,
mem_index
) begin
for (i=0; i<4; i=i+1) begin
for (j=0; j<4; j=j+1) begin
table[i][j] = st_num ? mem[id[i]][mem_index] :
mem[id[i]][mem_index];
end
end
end
Article: 100706"PC" <philippe.chagny**NO-SPAM**@free.fr> schrieb im Newsbeitrag news:44427e87$0$487$626a54ce@news.free.fr... > Hi Jacques, > > i totaly agree with you. > sorry my english is too poor, i can't write all i think !... > > effectively, there is a minimum order on Avnet France too .. > and they don't sell directly with a credit card ... > if i want some parts for my personnal use.. i can't now ! :( > only digikey ... > > if anybody know how create & manage a petition ... > let's go ! > > thank's > philippe Hi Jacques&Philippe et all, it may be surprising but the amount of responses/votes would not matter at all. A simple plea at c.a.f. to restore silicon devices into Xilinx online shop would likely receive 10 to 100 responses. However this number should actually deserve as more reason for Xilinx for concerne than a 10,000 votes thing. Because those missing votes are dont care, no interest, switching to competitor, etc. Digikey should not be considered as any choice (getting Xilinx silicon) - Digikey is great to occasionally check overall thumb guess component pricing and availability. It is ok to buy from digikey for small series, but then all components should be purchased for the full production span as any components that used to be available on Digikey may disappear anytime without notice. I had a project that was covered almost 100% from components available at Digikey, at the time it was ready for production most of those parts from the BOM where dropped by Digikey. The matter of instant sample/proto quantity component online ordering is VERY important, and it is long recognized by almost all vendors. Either you can order free samples or buy small quantities online. Getting samples for proto or evualuation fast without hassle is important. If you have to deal with large distributor to get the sample, then you loose both time and mental health. National has for most products with special '24hrs' sample option (well I guess for N.A. only but still) - they recognize that the speed (read immediate shipment) of samples can the factor that makes the difference. If I can buy 10 pieces online with shipment confirmation being sent within 24hours I can safely start a design and have pilot series all finished within 2 weeks from the idea to final product prototypes. If the part is not in stock by digikey and you need to start talking to Avnet you might be still be talking to them after two weeks. And that could be another desing loss for Xilinx. A desing loss for a project/product that could have large yearly volumes later. The ability to do initial evaluation-testing, pilot series quickly does matter. Antti PS Xilinx is sure not the only one with issues getting parts and pricing. While talking to Actel disti, haha the best price estimate for 1 off PA3E (with ARM) license was 100,000 USD !!! They refused to give any pricing, all they told me that the arm enabled option extra price for the silicon is 1$ USD in quantities of 100.000 and that the license price is scaled down for smaller orders. (This would come to 100,000 USD price for single qty) Talking to other disti and Actel FAE was better, the arm enabled (its only a security key inside the Actel silicon) adds 120USD to the component price for quantities below 10 (and not 100,000). So smallest PA3E with arm enabled (that it the AES key) costs 150USD (not 20 as without that AES key). Actel is pushing heavy on their ARM enabled FPGAs but OTOH they really do not want any customers with less than 100k volumes to actually use the ARM enabled silicon. Sure this Actel case is extreme example of stupidity and Xilinx is not getting even near to this. But if other are doing bad, doesnt meant that Xilinx should follow and reduce their flexibility of the component availability by removing the silicon devices from online shop. Xilinx is pushing towards "Make it your ASIC" that is low cost markets, and for those well you never know when a project that starts small grows really big. Or if an occasional hobby user playing with Spartan3 figures out some high volume consumer product. If that hobby user doesnt get that spartan (becuase now way to buy it) he will also never desing any high volume thing that is based on the Xilinx silicon.Article: 100707
Hi Antti, For the small story, the 10,000 signatures petition was said because of this: Here in north america, we had a TV show which was cancelled for some time (family guy) and after some lobbying from the fan base (10,000 names), it was said and is now aired again on TV. Just to tell you that it indeed might work. On the other hand, the chances are slim as some people at X might loose their faces... how do you think the people at Avnet would take it, if you said something one day, did it and came back on your words another day. It will be a hard decision for them, the high authority at X, and I think that their decision, unfortunately, is one which is definitive. My point now is to work toward a practical solution with the smart guys at Xilinx. I am just realistic and the chances to see back our dear online shop is very small. We need now a reliable and stable, prototype or small volume or qty, call it any name, supplier that can provide us, anywhere in the world, with any Xilinx Spartan3 FPGA chips or at least, the range that the Xilinx online shop use to have, and that at a reasonable price. As this is a call, make it also for Spartan3E and Spartan4. When this will be done, then it will stand up for their motto: "Make it your ASIC" or "Generation Spartan3E", but til then, these same words say: We are people who will definitely look at our own interests without caring for our fan base. Cheers JacquesArticle: 100708
and we can suggest that they accept Paypal !.. we can dream ;) <jaxato@gmail.com> a écrit dans le message de news:1145130612.059195.298690@i40g2000cwc.googlegroups.com... > Hi everyone, > > As I was buying some components from the Xilinx online store this > morning, I noticed that they no longer support silicon device anymore. > It seems that it is now AVNET that is taking care of distributing > Xilinx FPGA online. The worse thing is that the price is more > expensive, and they do not have all the parts that Xilinx use to offer > (the part I am looking for specially). > Now i've got a few questions for the Xilinx people out there. Is it > really true or if it not, then what is the updated link for your online > section. > > Many thanks > Jacques >Article: 100709
maybe someone can do a complaign "letter" and everybody send it to an xilinx customer email ..? they must not forget that many home users, are work users .. i do the choice at my work of wich FPGA i want use .. ( even if i know that i'm not the bigger customer ! ) regard's philippe "Labo.EKO" <labo.eko***nospam***@free.fr> a écrit dans le message de news:4442aadd$0$22761$626a54ce@news.free.fr... > > > and we can suggest that they accept Paypal !.. > we can dream ;) > > > > <jaxato@gmail.com> a écrit dans le message de > news:1145130612.059195.298690@i40g2000cwc.googlegroups.com... > > Hi everyone, > > > > As I was buying some components from the Xilinx online store this > > morning, I noticed that they no longer support silicon device anymore. > > It seems that it is now AVNET that is taking care of distributing > > Xilinx FPGA online. The worse thing is that the price is more > > expensive, and they do not have all the parts that Xilinx use to offer > > (the part I am looking for specially). > > Now i've got a few questions for the Xilinx people out there. Is it > > really true or if it not, then what is the updated link for your online > > section. > > > > Many thanks > > Jacques > > > >Article: 100710
"Labo.EKO" <labo.eko***nospam***@free.fr> schrieb im Newsbeitrag news:4442abea$0$16082$626a54ce@news.free.fr... > maybe someone can do a complaign "letter" and everybody send it to an > xilinx > customer email ..? > > they must not forget that many home users, are work users .. > i do the choice at my work of wich FPGA i want use .. > ( even if i know that i'm not the bigger customer ! ) > > > regard's > philippe > it would not help or do any good :( AnttiArticle: 100711
Do not give up! I'll soon find out whether I can have a bit of influence... Peter AlfkeArticle: 100712
I have an embedded project (MicroBlaze) that is currently using external oscillator to drive a DCM. The clkfx output of that DCM is used to drive all of the logic in the system. The parts that our company makes (Transceivers) have reference clock outputs that we want to use to clock some logic in the system. We have two "flavors" of parts that out current hardware needs to support. The problem is that one part outputs a 38.4 MHz clock, and the other outputs a 26 MHz clock. The 38.4 MHz clock can be used at 1x speed. We "talk" to out parts via a 3 wire serial protocol that is rated at 19.2 MHz top speed. This works nicely with the 38.4 clock since the flops driving the external protocol output 19.2 MHz, or slower. The part that ouputs the 26MHz clock has the same 3 wire serial interface (the protocol is different) but it is rated at 26 MHz top speed. So the logic that drives the interface needs to be 52MHz to reach this output speed. So basically what we need to do is pick either a 1x version of the input clock (38.4MHz) or a 2x version (to bump the 26MHz to 52MHz). I implemented a mux connected to the OPB. A software write will select which output of the DCM to use. My concern is with the input frequency parameter of the DCM. Does this parameter make or break the core? The input frequency to the DCM will either be 38.4MHz or 26MHz. But I want to use the same DCM for both freqs. Is this OK? I can easily try it, but wanted to ask here to see what folks had to say. I can also use two different DCM's and switch between the two if need be. Thanks!Article: 100713
morpheus <saurster@gmail.com> wrote: >Hi, >Does anyone have an idea if there is a free ARM emulator out there. We >have GHS in house...but the s'ware guys don't have an extra license for >me...huffffff >Anyways, I am designing a cpld which is memory mapped with a PXA 255 >and I need to prove out memory map architecture....I know I can >simulate but I derive more pleasure by checking chip selects for >peripherals on the scope....delight!!.. >Anyways, and help/input will be appreciated. >Thanks >MORPHEUS Maybe this works? http://www.freebsd.org/cgi/url.cgi?ports/emulators/skyeye/pkg-descrArticle: 100714
Jeff Brower wrote:
> All-
>
> I cannot seem to coax XST to infer a distributed RAM -- I believe it
> should find a simple, single-port, asynchronous read instance, but I
> continue to get the dreaded rejection notice "N flip-flops were
> inferred for signal <mem>. You may be trying to describe a RAM in a way
> that is incompatible with block and distributed RAM resources available
> on Xilinx devices..."
>> If anyone has suggestions for key syntax that I'm missing...
>
> -Jeff
>
> reg [1:0] index;
> reg [3:0] mem [3:0]; /* declare RAM to hold series of 4-pin IO array
> values */
> integer i, j;
>
> always @(posedge clk) begin /* store mem values */
>
> if (reset)
> index = 0;
> else
> index = index + 1;
>
> for (i=0; i<4; i=i+1)
> mem[i][index] <= IO_array[i];
> end
> end
Jeff, I'm not a Verilog guy, but my first suggestion is that your index
order is reversed. With a memory array, the index nearest the
identifier is the address, while the outer index addresses the bits of
the vectors in the array.
You may also be able to simplify things by skipping the bit iterations
altogether and writing something like:
always @(posedge clk) begin /* store mem values */
if (reset)
index = 0;
else
index = index + 1;
mem[index] <= IO_array;
end
(only showing write function for brevity)
The code you wrote was iterating over all addresses in the array in a
single cycle, which a memory cannot do, so you get a lot of
registers....
Article: 100715Yes, it would be great to have temac used by either lwip or Xilnet. As of now, we cant use the hard-core MAC just because of this reason. SenArticle: 100716
I see the pci-express starter kit HW-S3PCIE-DK (at http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-S3PCIE-DK) will have a Spartan 3e version due in "april". But I'm not sure it will be the 1600 version when it does come out. At $350 it is indeed a steal, and outperforming a Pentium 4 by 100 times wets my whistle. Is this what you're talking about? Implementing part of my algorithm in this hardware effectively removes several factors from my run time complexity, woohoo! FYI, my neural network theory revolves around several "feature detectors" (the reference vectors) competing to recognize various locality-sensitive-hashes (where collisions imply nearness). Thus the fundamental principle of competition between feature detectors could become testable at the scale of the brain. The algorithm extends to optical character recognition, speech recognition, and language understanding because constructs in these domains can all be translated into the same language; locality sensitive hashes (though it may take a million bits, which the brain has no problem with). Though I'll probably wait some months to use the fpga so that I can finish my dissertation, it will be nice to make claims as to the real-world speedups that can be expected from the massively parrallel characteristics of the brain derived algorithm. Thanks for your help, let me know if there is a product you think is better suited, AndrewFArticle: 100717
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1145227094.372948.32810@t31g2000cwb.googlegroups.com... > Do not give up! > I'll soon find out whether I can have a bit of influence... > Peter Alfke > :) no! if you did read my other reply then well I tired to give you as much ammo as I could. I really do think that immediate direct no-hassle sample/small qty silicon device ordering system is a very important 'decision factor' when choosing silicon vendor. At the times when Xilinx online shop did carry silicon devices I quite often loggen in to calculate BOM pricing for several different project. None of them is completed but the next one could have been. AnttiArticle: 100718
Hi all,
I am working on a model which is basically a four bit 50 to 1
mux. There is four such blocks. To save area i am trying to time
multiplex the muxing that is only twi such blocks are created and the
data is latched with high and low levels of the clock. But the delay in
the mux block is such a large value which prevents the time
multiplexing of the signal. Applied "From to " constrain to the input
and output signals of the mux block but the PAR tool reported it as
ignored. It displplayed N/A at the requested and available time for
that group. Why it is like that.
In the timing analyser tool when a request is placed to measure
the delay between the input and output groups is placed it gave no
result. But when the delaye between invidual elements where requested
it gave result. is it necessary to specify timing constrain for each
element.
Is there any other methods by which we can reduce the muxing time.
The inputs of the mux blocks comes from FFs and the output goes to
latch which is controlled by high and low time of clock.
From the timing report it is found that the fanout for the
selection pins of the decoder is very high (50). And this gives the max
delay. Is there any way to tell the synthesizer to insert buffer to
reduce this high fanout. For the mux i am using indexing method like
out = in[sel];
I am stuck with this problem. Also i have little experiance with
the timng analysis. Please help me on this issue. I am working with
Virtex 2 and Xilinx ISE 7.1.
Thanks and regards
Sumesh V S
Article: 100719Hi I am looking at ways to configure a Virtex II Pro Device. I want to add some Flash memory for use with the PPC Core and was wondering if I could store the config data in some of it? If I can how would I go about interfacing to it. Thanks JonArticle: 100720
Peter Alfke schrieb: > Do not give up! > I'll soon find out whether I can have a bit of influence... > Peter Alfke Having a Xilinx online Store is a good option, but if Xilinx does not want to handle the logistics for that themselves there is another option. Xilinx could acquire small distributors in addition to Avnet/Silica. Silica told me outright in the face that they do not like to handle small customers like me, so why force them to do that? A small distributor with less company overhead often can service small customers a lot better than the huge players. Kolja SulimmaArticle: 100721
On Mon, 17 Apr 2006 12:03:56 +0200, Kolja Sulimma <news@sulimma.de> wrote: >Peter Alfke schrieb: >> Do not give up! >> I'll soon find out whether I can have a bit of influence... >> Peter Alfke > >Having a Xilinx online Store is a good option, but if Xilinx >does not want to handle the logistics for that themselves there >is another option. >Xilinx could acquire small distributors in addition to Avnet/Silica. >Silica told me outright in the face that they do not like to handle >small customers like me, so why force them to do that? > >A small distributor with less company overhead often can service small >customers a lot better than the huge players. > Doesn't have to be small, just differently targeted - e.g. Digikey, Mouser.Article: 100722
Mike Harrison schrieb: > Doesn't have to be small, just differently targeted - e.g. Digikey, Mouser. Those carry only a portion of the devices, usually stocking them. I need someone who also orders parts with long lead time for me, but without whining that I only want 100 parts. Kolja SulimmaArticle: 100723
Brian, I agree with what you wrote, however the video actually shows the 750MHz LVDS output and they talk about it running at this speed. So, I assume that they are running SDR with DES. Did you watch the video, or do you have some insider information on the project? ThanksArticle: 100724
I think I wrote DES in that last note, which would have been incorrect. Austin, Thanks for the input. Do you know if the parts are indeed running at the 750MHz as stated in the video? Talking with Altera they also claim the part was running in DDR mode, again not what the video shows. I have tried to contact National about the design, but no luck yet. "It won't be 45/55% like the spec sheet says, but it will still have a perfectly good pulse there. Obviously National is using this. Since they are using it, that makes Xilinx kind of responsible for some support of this application. " I am not sure what the arrangement would be that Xilinx would be responsible for what I would consider a bad design (assuming they really are running the part at 750MHz). If Xilinx does plan to support higher clock rates, what does this mean to me as a designer? Are there any application notes that talk about overclocking the Virtex 4? Just an FYI, if I try to do this same thing with the Stratix II and Quartus, the tool will spit out an error. I spoke with Altera about this and they made the comment that they do not allow the parts to be over driven.
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