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Hi - On 12 Apr 2006 17:44:50 -0700, "JustJohn" <john.l.smith@titan.com> wrote: >Roger Bourne wrote: >> Hmmm.... >> >> Timing constraints ? Are *.ucf files created for a *typical* FPGA >> design ? >> I cannot seem to >> recall if timing constraints (*.ucf file) are user-entered OR IF >> timing-constraints entry is typically ignored and the fpga typically >> generates it for the user. >> (...I am in the process of going over the help files as I am typing >> this post...) >> Please advise >> -Roger > >Here's an old "buried gem" on the Xilinx website: >ftp://ftp.xilinx.com/pub/documentation/M1/timingcsts1.5.zip There's another presentation, this one for 6.1i, that's more extensive: ftp://ftp.xilinx.com/pub/documentation/misc/timingcsts6i.pdf This is the single best description of Xilinx timing constraints that I've seen. Bob Perlman Cambrian Design WorksArticle: 100601
burn.sir@gmail.com wrote:
> Having seen way too much spam on this newsgroup lately, I have come
> with a possible solution that just might work.
If you think it is worth your time to flame
a spammer, please do it on his turf, not in the newsgroups.
This thread is already close to the recent spam postings in bandwidth.
> Add a section to FPGA FAQ where the known names on the newsgroup will
> list the companies they recommend (plus some explanation). Next time
> someone spams the list about "high quality PCB", or what the hell it
> is, we post a polite response saying that no one should support spammer
I appreciate your intent, but this is as off-topic as the spam.
> We could also add another section about newsgroup netiquette, 3leet
> English and what we think about doing other peoples homework. This is
> of course not as big problem as spammer, but it is still a little bit
> annoying sometimes.
The target group for your advice does not read
this newsgroup regularly. Those of us who do read,
may post a pointer for interesting on-topic faqs
but ignore the rest without judgment.
-- Mike Treseler
Article: 100602"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag news:zWf%f.5617$kg.104@news02.roc.ny... > "Antti Lukats" <antti@openchip.org> wrote in message > news:e1jrgd$59j$1@online.de... > <snip> >> whatever you are looking for you have out-smarted me! what is that magic >> thing that is one everones desks and what could allow SPI programming ?? >> >> anyway nomatter what it is, as I have said its its very likely NO NO >> NORWAY. >> >> >> Antti > > > The magic thing I have is the target FPGA in a system that has a processor > with our own OS drivers with ethernet and USB connectivity that are live > before the FPGA is ever programmed. I couldn't reconfigure the FPGA's SPI > configuration memory on everybody's desk without external tools (JTAG, > ByteBlaster, Parallel Cabe IV) if the FPGA were the only smarts on the > board. > gosh, writing SPI flash is 26 lines of C-source code, are you really SOO lazy that you are looking into possibilities to do it without doing any programming ?? anttiArticle: 100603
Thanks Andraka and Munaut...Article: 100604
Hi I am designing a PCB with a Virtex II Pro and some DDR memory so need to use a controlled impedance board. I am going to use an 8 layer board. My question is do I need to specify to the PCB manufacturer the various thickness of each layer and the gaps or is there a standard that they will use. Cheers JonArticle: 100605
'Controlled impedance' means just that, you (the engineer) specify the stackup so that the impedance meets the requirements for your design. Leaving it to the PCB manufacturer means that you're not controlling it but willing to accept whatever they may happen to make. KJ "maxascent" <maxascent@yahoo.co.uk> wrote in message news:66SdnZGmQa9ouKPZRVn_vA@giganews.com... > Hi > > I am designing a PCB with a Virtex II Pro and some DDR memory so need to > use a controlled impedance board. I am going to use an 8 layer board. My > question is do I need to specify to the PCB manufacturer the various > thickness of each layer and the gaps or is there a standard that they will > use. > > Cheers > > Jon > >Article: 100606
Hi. I fanally could test with an intel box and it works the same. As I don't have a PCI-analyzer, I'm thinking in the possibily of making some tests with a logic analyzer. That's not that much urgent, since I'm changing the system to USB, and I'll need to shorten the desing time due to this PCI problem. Anyqay, I'd need to try to solve this to assure maintance of the machines that are in field. Thanks a lot for the help. Ricardo Ricardo escreveu: > Hi. > > I have a PCI board developed and I have little acess to the FPGA PCI > core, since it was not developed in house. I can say it makes no burst > accesses. My proble is that I used to have a reasonable speed with these > boards with athlon/semprom boards, regardless of chipset. After the > chipsets/processors changed to socket 754 and 939 (and got > HyperTransport, but I don't know whether it's related) i got a 20% speed > drop, a little too much. With the nForce4 chipset I may get to the same > speed as before, but I can't achieve it with a stable bandwidth. I don't > have any intel boxex around to test with it. > Does anyone has any clue on what's going on (even better, a solution)? > > Thanks, > RicardoArticle: 100607
I understand what you are saying but is there any industry standard values that are used. If I were to use these then I can adjust my track size to get the impedance I need. Cheers JonArticle: 100608
Thanks to all for the response. I have a Vertex II device and prototype board and not the Vertex II Pro. I suspected that it was not available on the Vertex II device (nonPro versiont) but thought I'd ask anyway. ScottArticle: 100609
maxascent wrote: > Hi > > I am designing a PCB with a Virtex II Pro and some DDR memory so need to > use a controlled impedance board. I am going to use an 8 layer board. My > question is do I need to specify to the PCB manufacturer the various > thickness of each layer and the gaps or is there a standard that they will > use. Contact the PCB manufacturer and tell them the stackup (for example, signal, GND, 3.3V, signal), tell them the impedance that you want and have them tell you the design rules (for example, 5 mil lines and 5 mil spaces). Controlled impedance is a combination of line width and spacing, dielectric thickness and dielectric constant. The board manufacturer knows what dielectrics are available to them, so they can advise what rules to use for their dielectrics. --- Joe Samson Pixel VelocityArticle: 100610
maxascent wrote: > I understand what you are saying but is there any industry standard values > that are used. If I were to use these then I can adjust my track size to > get the impedance I need. Yes, ask your manufacturer. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 100611
Antti Lukats wrote: > > gosh, writing SPI flash is 26 lines of C-source code, are you really SOO > lazy that you are looking into possibilities to do it without doing any > programming ?? > > antti I'm a hardware guy, not software. I can write disposable software but not code for our product. In our company, the software responsibility for drivers resides with software professionals responsible for maintaining and troubleshooting the production code. Similar provisions were made by hardware for direct programming of a different configuration memory configuration but the software folks never had the time or inclination to write 26 lines of code because of schedule and priorities rather than laziness. By taking on the task myself in hardware (Steve Knapp's pointer to a PicoBlaze solution might take care of me) I don't have to rely on those who don't understand the convenience of having a clean system to update the configuration memory.Article: 100612
maxascent wrote: > Hi > > I am designing a PCB with a Virtex II Pro and some DDR memory so need to > use a controlled impedance board. I am going to use an 8 layer board. My > question is do I need to specify to the PCB manufacturer the various > thickness of each layer and the gaps or is there a standard that they will > use. > > Cheers > > Jon Our typical flow is: 1) propose stackup, 2) ask vendor for comments, 3) if it's not laughable results from the new guy, evaluate the vendor's tweaks to the stackup, 4) lay out with the requisite line widths. There is no standard, only required dielectric thicknesses for your line widths or vice-versa. If you specify impedances, they will tweak the line widths for the dielectrics they use by adding test coupons for TDR measurements to guarantee production within your tolerance.Article: 100613
Eric Smith wrote: > > It appears that the mating connector would be the Hirose > FX2-100S-1.27DS, but I haven't confirmed this. If so, it's available > from Digikey for $7.07 quantity one. > > I think I might add two 270-ohm resistors to the starter kit, between > two FPGA pins and the "reserved" pins 2 and 6 of the PS/2 connector. > This would allow using both a mouse and keybaord at the same time, > with a common laptop "PS/2 splitter cable". I haven't yet chosen > which FPGA pins to use. A wire-wrap section would be nice, as would some standard header strips. About the only other thing I can think of readily would be some pads for installing a standard AC97 audio codec and amplifier. Oh, a buddy of mine has been lamenting the fact that EVERY board he has looked at only has 1 PS/2 connector - which means at least one peripheral must be USB - or you strap another PS/2 connector somewhere on the board. Might be handy to have an extra. > I hope that Digilent will offer a version of this board with an > XC3S1600E chip in the near future. :-) I sent an email to Digilent a month ago when the board finally started showing up in the Avnet store asking that very question. Apparently, the boards with the 1200E/1600E option won't be exactly the same as the starter kit - but they should be available by June. I hope by "different" they didn't mean less RAM or FLASH, though. I have the Altera DE2, which has a EP2C35. Looking at the datasheet, the 2C35 appears to be roughly to the Xilinx XS31200E. Unfortunately, the board only has 8MB of SDR SDRAM and 512KB of SRAM. It does have a 4MB Flash at least. I may "upgrade" (sidegrade?) to the Digilent board if the price difference isn't too great.Article: 100614
Thank you guys. The documents referenced above were very helpful -RogerArticle: 100615
shereen.ahmed schrieb: > 1- why the best code are the random codes ? I think it is because optimum noise performance is obtained from a 1N753A Zener diode: http://www.elecdesign.com/Articles/Index.cfm?AD=1&ArticleID=6326 Kolja SulimmaArticle: 100616
the picoblaze solution DOES INCLUDE software so dont get rid of the software anyway! using no software but plain FPGA hardware (no softcore processor!) for SPI flash programming is really not reasonable. So whatever you do you end up w=EDth some piece of software be it in the host computer or inside the FPGA AnttiArticle: 100617
The biggest issues I've had with this is board capability detection. I have some boards that are supposed to run PCI64 @ 66MHz. However, in some motherboards they are detected as 32bit wide at 66MHz or 64 bit wide at 33MHz. In both those cases I lose 20-30% of the speed. There should be a way to determine which mode your board is running in, or if all else fails scope the clock pin and REQ64/RST signals at boot.Article: 100618
Antti wrote: > the picoblaze solution DOES INCLUDE software so dont get rid of the > software anyway! > > using no software but plain FPGA hardware (no softcore processor!) for > SPI flash programming is really not reasonable. So whatever you do you > end up wíth some piece of software be it in the host computer or > inside the FPGA What John meant was not as much 'no software' as 'no external(other person's) software' - it's a demarkation issue, more than a technical one. -jgArticle: 100619
"KJ" <kkjennings@sbcglobal.net> wrote in message news:lSp%f.58590$F_3.44450@newssvr29.news.prodigy.net... > 'Controlled impedance' means just that, you (the engineer) specify the > stackup so that the impedance meets the requirements for your design. > Leaving it to the PCB manufacturer means that you're not controlling it but > willing to accept whatever they may happen to make. > In most cases board manufacturers have much better abilities to control impedance than board designers. I usually would run Polar impedance calculator to make sure my design is feasible but would leave actual precise control to the board house. In some cases where it matters (RF) I would add some extra constraints such as, for example, dielectric thickness should be at least 10 mil. The line widths don't have to be exact in the design. The board house will fix them. Interestingly, our board house doesn't charge extra if they need to decrease the line width to below 4 mil for the impedance control purposes, but they do charge if the lines are below 4 mil in the original design! /MikhailArticle: 100620
> Eric Smith wrote: > > > > It appears that the mating connector would be the Hirose > > FX2-100S-1.27DS, but I haven't confirmed this. If so, it's available > > from Digikey for $7.07 quantity one. This looks correct - of course there are a lot of options for cables/connectors - you can also check out hirose's site at http://www.hirose-connectors.com/ (type FX2 in the search). A wire-wrap daughter board (to plug in to the 100 pin connector), and a codec daughter board (perhaps to plug in to one of the 6-pin connectors) are both really good suggestions for Digilent - you might shoot them an email. If there was reasonable interest in these, they might seriously consider adding both of these to their daughter and peripheral board offerings. The pin out to both of these connectors are standardized between the Spartan-3E Starter Kit, and other Digilent boards, so those new daughter boards would be compatible with many other Digilent development boards. Speaking of this, check out their VDEC1 board - it's a $69 video decoder board that will plug in to the the S3E Starter Kit's 100-pin connector... http://www.digilentinc.com/Products/Detail.cfm?Prod=VDEC1&Nav1=Products&Nav2=Accessory -Scott S.Article: 100621
"maxascent" <maxascent@yahoo.co.uk> wrote in message news:66SdnZGmQa9ouKPZRVn_vA@giganews.com... > Hi > > I am designing a PCB with a Virtex II Pro and some DDR memory so need to > use a controlled impedance board. I am going to use an 8 layer board. My > question is do I need to specify to the PCB manufacturer the various > thickness of each layer and the gaps or is there a standard that they will > use. There is no standard, but most of the boards use FR4 material with the dielectric constant of about 4.3. It works out that a 5 mil track with 5 mil separation from a plane (assuming the second plane is at least 15 mil away) gives you approximately 50 Ohm impedance. How many layers of your stackup are planes? Generally speaking a 8-layer board is not very convenient for impedance control. To make it easy you need to have planes next to your top and bottom layers as well as the planes separating each two internal signal layers. Consider 10 layers instead: 1. Top 2. Plane 3. In1 4. In2 5. Plane 6. Plane 7. In3 8. In4 9. Plane 10. Bottom Note that there is an issue of copper balance, i.e. the stackup needs to be symmetrical to prevent board warpage. /MikhailArticle: 100622
Hi all, I was wondering if anyone used RGMII on the V4 hard TEMAC? The reason I am asking is because this mode is not supported if the core instantiated in the EDK, but nothing seems to prevent from using it if the core is instantiated with the VHDL wrapper found in the Core Generator... Thanks, /MikhailArticle: 100623
MM wrote: > Hi all, > > I was wondering if anyone used RGMII on the V4 hard TEMAC? The reason I am > asking is because this mode is not supported if the core instantiated in the > EDK, but nothing seems to prevent from using it if the core is instantiated > with the VHDL wrapper found in the Core Generator... > > > Thanks, > /Mikhail > > I have a webcase open on this issue right now. I want to use PLB_TEMAC with RGMII, but that combination is currently not supported. I will update the group when I get an answer. --- Joe Samson Pixel VelocityArticle: 100624
I was watching Avnets' sponcered video with Robert Pease and Howard Johnson where National had a board with a ADC08D1500 dual ADC tied directly into a Virtex 4. The videos, datasheets, etc may be found at: http://www.national.com/xilinx/ The LVDS clock coming from the ADC is 750MHz. They route this clock directly to the Virtex 4. When I look at the specs. for the Virtex 4, this would seem to be way outside of what it is rated for. My question is this, did National do some neat trick to make this work, or did they just exceed the specs of the device knowing it was not a production unit and did not really worry about it? Or did I miss something? Also, if anyone purchased the eval. board, I would be interested in hearing if U5 was populated with the LMH6550 or some other part. Thanks
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