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Hi Simon,
the simple answer is : No.
More complex: What do you want it do do?
To me the code looks like a complicated shift register with a priority
encoded output generation.
Question: Do you want to build a shift register?
Do you want a priority encoder?
The pitfall in your code may be that you are using multiple ifs in a
single clocked process and work with signals.
Signal values are only updated at the end of the process, So when you
set local_signal <= '1'in your first if that value is not immediately
visible to the next if. It becomes visible at the next rising clock
edge.
But if that is what you want, it's ok.
Is your behavioral simulation working correctly?
Have you made a timing simulation too?
have a nice synthesis
Eilert
Article: 100876I am doing some research on the reliability of microcontrollers software in comparison to hardware description languages for PLDs (CPLD/FPGA). Another interesting point is whether there are general benefits of one hardware regarding reliability, e.g. in an automotive environment. I read about certification problems if a SRAM based FPGA is programmed every system start and that Flash or Fuse based systems are preferable. I also read that CPLDs (Flash) in general are more robust than FPGAs. Can you confirm/confute this? Thanks for your help. FalkArticle: 100877
Syms, The strange behaviour that I am experiencing is in 'real-hardware' I am monitoring this behaviour from two different aspects: 1) The effects that it has on the rest of my design 2) A built in test function that essentially consists of counters distributed throughout the code and a method of recording the values of the counters and presenting the information (through the use of register access and a processor) The inputs to the code are synchronous to the clock. SimonArticle: 100878
Hi, radarman schrieb: > or the FPGA itself crap out - both designs will fail. If this is a > space application, where you may have to deal with SEU events (single > event upsets) or worse - consider that a single bit change to the FPGA [..] > If you really want to get retentive, you can do what NASA does (or used > to do). Implement the function independently three different times to > the same spec - then load the three implementations on to three > separate parts. This way, the odds of all three failing at the same > time are exceedingly low, and you can tolerate a lot more. In space applicatione it is common practice to use radiation tolerant technologies (TMR) for registers only. Of course you avoid single source of failures on system level (eg. two redundant bus structures). I never heard of anybody using 3 devices in parallel to achieve robustness against radiation in space. You had a hard argue to get a customer accepting reconfigurable FPGAs in environment with high SEU probabillity like satellites especially if you need a high reliability. But a fuse based fpga is (nearly) immune against permanent changes due to radiation and therefore state of the art. > life-safety (or space qualified) critical - use three parts and > implement a voting scheme. If it's not - just do the design once, in a > single FPGA. As long as you have done the correct job in design, odds > are fairly good that both will fail in the same manner, at > approximately the same time, anyway. (this is what happened to a > particularly unlucky Arianne rocket - look it up) Just for curiosity: What fault in an Arianne are you talking about? bye ThomasArticle: 100879
Eilert, The main purpose of this code is to recognise when 'input_signal' is high and then set 'output_signal' high and then wait for 'output_complete_signal' to be high before setting 'output_signal' low. The complexity comes into it where 'input_signal' is accompanies by a data signal and depedant on that data one of many 'output_signals' are set high and a corresponding 'output_complete_signal' is monitored instead. However, the structure of the code is the same, just expanded. Answer, I don't want a 'shift-register' and am not familiar with the functionality of a 'priorty-encoder'. The behaviour that you described is exactly how I intended it to behave. The behavioural simulation operates correctly, I have not done a timing simulation (and cannot for other reasons). Regards, SimonArticle: 100880
Hello, I have a microblaze system containing an OPB_SPI core. It used to work without adding special timing constraints for this core. It seems that I have a timing problem now that my FPGA is getting full. The data coming from the SPI core is now shifted by one bit. I have noticed that the SPI_OPB uses a seperate clock, constraining this clock used to help but I think that I should add more constraints. Has anybody had a similar problem? The xilinx site gives no info on the required timing constraints for this core. thanks and best regards, Karel DArticle: 100881
Hello Marco & Vladimir Unfortunately we need TCP/IP in our products, so we need to use the TCP/IP stack and prefereably without any cost. In the relating thing to the speed of transmission on gigabit ethernet, we have reached more than 900 MB/s with the ML403 development board and a cathegory 6 crossover cable with the GSRD reference system, who use the Treck TCP/IP stack with Jumbo frames. Without Jumbo frames the transmission speed falls to 250 MB/s. Our specifications must reach at least 350 MB/s. Another problem is the size of the design. The GSRD systems occupies the 79% of the Virtex4FX12 (in the ML403 board). The best option is to use the next FPGA, the Virtex4FX20, but the ISE WebPack, don't sinthetize this chip. The cost of the product it's growing up!! The last option that I'm evaluating is the UltraController II. I have sinthetize the XAPP807 reference design, a Gigabit webserver. The used resources are minimal (two FIFOs, 20 slices and 18 LUTs) but I have several doubts yet. The UltraController II use the PPC405 as the engine to control the temac (Exclusively?). I'm investigating about to expand the design to use the PPC405 for others parrallel issues but the work flow is different like the EDK's flow and there is no access to the PLB or OPB buses. Maybe the GSRD team can make a smaller gigabit design? I wait that!Article: 100882
<simon.stockton@baesystems.com> wrote in message news:1145466216.810985.131360@t31g2000cwb.googlegroups.com... > Thanks for your response, > > This code snippet is actually a structural representation of my actual > code (which is much more complex). I am experiencing some strange > behaviour where although 'input_signal' is only held high for one clock > cycle (by another process, but using the same clock) the > 'output_signal' is asserted twice, or so it appears. I was wondering if > the structure of my code (and my coding style) would cause this > situation to occur. It only appears to present itself on > 'real-hardware' in the 'simulator' I cannot repeat the strange > behaviour. When 'reality' differs from simulation with the symptoms you've described it's usually a timing problem of some sort so double check the timing reports out of the fitter and make sure that it agrees with you that the inputs to the process (reset, input_signal and output_complete_signal ) really are synchronized to 'clock'. Although you're using 'reset' as an asynchronous input to clear your outputs the timing of reset still needs to be synchronized to clock. Ask yourself what happens when 'reset' switches from '1' to '0' 'too close' to the rising edge of 'clock'. If you violate timing then you really don't know what the outputs are going to go to and since what you have is basically a form of a state machine you're probably hosed. If 'reset' really is asynchronous then sync it up first before using it in any clocked process. The actual 'form' of how you write the code is not the problem. The posts about the structure of the 'if' statements will likely improve the quality and maintainability of the code but it will not change functionally how simulation or reality behave since it is a 'coding style' issue. KJArticle: 100883
Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote: > The Spartan-3 resistor values turned out a bit stronger than originally > expected during design. The Spartan-3E resistors values are weaker, > but still strong enough to be useful. Early FPGA families has > resistors up around 20K to 50K, too weak to be useful. Thanks for the info. I don't understand why you say a 50K PU is too weak to be useful. That is more the range that I expect from an internal PU. I am working the Spartan 3 configuration sequence and have been getting a lot of coments from one person in particular about my pull up/down resistors being too weak. He has made a lot of unsubstantiated claims about a previous design not working until various PU/PD resistors being replaced with 0 ohm jumpers. I see now that there may be some truth to this. I have been searching the data sheet for all info on internal PU/PD and it is not easy to find. It is rather scattered about and takes a lot of searching. At first I didn't think any of the configuration pins had PUs, but I saw the notation in Table 6 that the values of resistance applied to User I/Os, Dual Purpose and Dedicated pins. So I searched the document for pull-up and eventually found them all... I think. Here is what I think I have found... HSWAP_EN - PU PROG_B - PU during configuration, PU optional based on ProgPin config option DONE - bit stream configurable for open drain or totem-pole, optional PU in User mode or external PU required M0,M1,M2 - I am very confused about this one. Here is what it says in the detailed pin description... "In user mode, after configuration successfully completes, any levels applied to these input are ignored. Each of the bitstream generator options M0Pin, M1Pin, and M2Pin determines whether a pull-up resistor, pull-down resistor, or no resistor is present on its respective mode pin, M0, M1, or M2." The mode pins have to be held in the appropriate state before any of the bit stream can be loaded. So external PU/PDs are required. Further the pins are ignored except for the rising edge of INIT_B. Then what purpose does it serve to provide PU or PD after configuration? I am a bit confused about the setting of the Mode pins. There appears to be a mode for JTAG configuration and in one place it says the JTAG port can not be used until the INIT_B pins rises. But in another place the data sheet says "The JTAG port is always active and available before, during, and after FPGA configuration." If this is true, do the Mode pins need to be set to 101 to configure the part using JTAG? I suppose it could be that the JTAG port is available for other things like boundary scan, but not configuration unless the correct setting is applied to the Mode pins. Do I need to provide for different settings for JTAG configuration and Slave Parallel configuration? That would be two resistors I need to change...Article: 100884
Hello, I'm currently building a system with one microblaze and two masters opb component, But in order to set up priority in my C code, how do i know the master id of a master component. Thank you ChristopheArticle: 100885
Falk Salewski wrote:
> I am doing some research on the reliability of microcontrollers software in
> comparison to hardware description languages for PLDs (CPLD/FPGA).
I expect that the statistics needed to prove anything
will be hard to find.
> Another interesting point is whether there are general benefits of one
> hardware regarding reliability, e.g. in an automotive environment.
Reliability is a system issue.
The concern is performance degradation with time.
Stressors includes vibration, thermal cycling
power supply variations, and variations of
the sequence and phasing of asynchronous inputs.
Both fpgas and microcontrollers could fail
in the face of any of these.
> I read about certification problems if a SRAM based FPGA is programmed every
> system start and that Flash or Fuse based systems are preferable.
Certification requirements
one of many system specifications.
Most systems use flash of some sort
to initialize RAM of some sort in the
face of the Stressors listed above.
> I also
> read that CPLDs (Flash) in general are more robust than FPGAs.
> Can you confirm/confute this?
You need facts, not opinions to confirm such a statement.
-- Mike Treseler
Article: 100886Thansks,I want to know what speed the Clock you list above can reach? 50Mhz?I care the sklew when routing!Article: 100887
Even with rad-hard chips, you still have potential SEU issues. I worked on an unnamed satellite where we had to deal with this. We chose to use a single part, in this case, a rad-hard Actel fuse-link part, and use TMR (triple module redundancy) on the I/O, and internally for the logic - but we did it for power reasons. In this case, though, a failure could generally be tolerated (and corrected) remotely with no real safety consideration. At worst, we would lose utility for a brief time. That, for me, is the primary factor. If a complete failure can be tolerated, it's generally acceptable to use a single part and replicate the design - but with safety critical, it's another story. I worked for a while at a nuclear power plant, and every critical system has at least one backup, and in some cases, two backups. Clearly, not a situation where you can tolerate a complete failure gracefully. The Arianne problem I was referring to was the Arianne 5, the first of which went off course and was destroyed due to a fault in it's inertial navigation system software. http://sunnyday.mit.edu/accidents/Ariane5accidentreport.htmlArticle: 100888
Superman <> writes: >i have created my *.Xdl file and i have and i am actually trying to >move the design to a new location. btw i am using a VIRTEXII FPGA. > >the xdl file read as follows: >inst "XLXI_1/counter_out1<3>" "SLICE",placed R2C1 SLICE_X1Y77, > >so this inst is at row 2 and column 1, i just tried to move to a new >location like say same row i.e. row 2 but column 30, and i saved it >and tried to convert it back to a *.ncd file. > Erm.... >NOW, i am getting some errors while converting back. At the command >promt i typed xdl -xdl2ncd <designfile>.xdl <design file>.ncd > >Is this rite??????? > Yes. >was my changing the places of the inst wrong??? How do we modify the >placement...do i have to change the slice location too ... > I believe so, and you'll need to modify all the routing as well (unless it is just a placed design) >please help me ....i am in dire need to move the design to a new >location by modifying the XDL file. > I think you'd be better off using Floorplanner to move stuff around and create UCF constraints for it... If you really need to move stuff around in XDL you'll need to learn all the low-level guts of the FPGA - have a play around with FPGA editor to see how much stuff there is in there! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conektArticle: 100889
Hello all,
I was experimenting a design with V4 lx60. Synthesizer is
synplify 8.0 and xilinx ISE7.1 for PAR. Two clocks to the design clk
and ckl4x. But in the pacakage pin assignment tool lot of signals are
listed under the global resource. Locked clk and clk4x to global clk
IO. But at the maping stage the MAP is telling to LOCK the clock
resources which i think is this extra created global signals. Why the
synthesizer is creating extra signals which behaves like clocks.
Also if i apply a timing constrain to the internal signal this
problem will not be there at the mapping stage. But the PAR will never
complete. After about 6 hrs work it says that the design is unroutable.
Is this because of this extra global signals.
But if i use lx200 instead lx60 there is no problem in the above
two step and MAP and PAR completes successfully. How can i eliminate
creation of such global clocks by synthsizer.
regards
Sumesh V S
Article: 100890The Xilinx Online Store just started showing "In Stock" availability for all 4 power-optioned Spartan3E Starter Kit boards at $149.Article: 100891
rickman wrote: > Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote: > > The Spartan-3 resistor values turned out a bit stronger than originally > > expected during design. The Spartan-3E resistors values are weaker, > > but still strong enough to be useful. Early FPGA families has > > resistors up around 20K to 50K, too weak to be useful. > > Thanks for the info. I don't understand why you say a 50K PU is too > weak to be useful. That is more the range that I expect from an > internal PU. I am working the Spartan 3 configuration sequence and > have been getting a lot of coments from one person in particular about > my pull up/down resistors being too weak. He has made a lot of > unsubstantiated claims about a previous design not working until > various PU/PD resistors being replaced with 0 ohm jumpers. I see now > that there may be some truth to this. > > I have been searching the data sheet for all info on internal PU/PD and > it is not easy to find. It is rather scattered about and takes a lot > of searching. At first I didn't think any of the configuration pins > had PUs, but I saw the notation in Table 6 that the values of > resistance applied to User I/Os, Dual Purpose and Dedicated pins. So I > searched the document for pull-up and eventually found them all... I > think. > > Here is what I think I have found... > > HSWAP_EN - PU > > PROG_B - PU during configuration, PU optional based on ProgPin config > option > > DONE - bit stream configurable for open drain or totem-pole, optional > PU in User mode or external PU required > > M0,M1,M2 - I am very confused about this one. Here is what it says > in the detailed pin description... > "In user mode, after configuration successfully completes, any levels > applied to these input are ignored. Each of the bitstream generator > options M0Pin, M1Pin, and M2Pin determines whether a pull-up resistor, > pull-down resistor, or no resistor is present on its respective mode > pin, M0, M1, or M2." > > The mode pins have to be held in the appropriate state before any of > the bit stream can be loaded. So external PU/PDs are required. > Further the pins are ignored except for the rising edge of INIT_B. > Then what purpose does it serve to provide PU or PD after > configuration? > > I am a bit confused about the setting of the Mode pins. There appears > to be a mode for JTAG configuration and in one place it says the JTAG > port can not be used until the INIT_B pins rises. But in another place > the data sheet says "The JTAG port is always active and available > before, during, and after FPGA configuration." If this is true, do the > Mode pins need to be set to 101 to configure the part using JTAG? I > suppose it could be that the JTAG port is available for other things > like boundary scan, but not configuration unless the correct setting is > applied to the Mode pins. Do I need to provide for different settings > for JTAG configuration and Slave Parallel configuration? That would be > two resistors I need to change... I don't know whether to feel stupid or to feel Xilinx is stupid. I found an answer record that answers the part about the Mode pins having pullups. I could not find anywhere in the data sheet about the mode pins having pullups. But the answer record says the Mode pins are all pulled up to 2.5 volts by the equivalent of a 1.15 kohm resistor, worst case. This means you need no larger than about 470 ohms for your pull downs!!! Does the data sheet say these pins are pulled up and I missed it? I actually did a search on "pull-up" (which is how Xilinx seems to term them) and did not find any mention of a pullups on the mode pins. The pin definition, where this info certainly should be, makes no mention of this. I think Xilinx really dropped the ball on this one!Article: 100892
vssumesh wrote:
> How can i eliminate
> creation of such global clocks by synthsizer.
Not using the global clock resources
wastes gates and makes it very difficult
to meet hold requirements. That's why
your constrained design won't route.
Check the utilization and static timing reports
and look at the rtl viewer. Consider
a single clock design.
-- Mike Treseler
Article: 100893Does anybody know if the Xilinx PCI Express cores from Xilinx can run w/ Icarus Verilog? I can't seem to get access to an eval copy to find out for myself. The link to the .tar.gz (and the .zip) seem dead for me. Nor can I find out if I can use it with WebPACK or I need the full ISE to access the actual Verilog. The last full ISE I have is 6.2, but I can obviously get at WebPACK releases. Does WebPACK have the CORE generators I'd need? - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 100894
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:4apho3Fu8qd5U1@individual.net... > Falk Salewski wrote: >> I am doing some research on the reliability of microcontrollers software >> in comparison to hardware description languages for PLDs (CPLD/FPGA). > > I expect that the statistics needed to prove anything > will be hard to find. > >> Another interesting point is whether there are general benefits of one >> hardware regarding reliability, e.g. in an automotive environment. > > Reliability is a system issue. > The concern is performance degradation with time. > Stressors includes vibration, thermal cycling > power supply variations, and variations of > the sequence and phasing of asynchronous inputs. > Both fpgas and microcontrollers could fail > in the face of any of these. > >> I read about certification problems if a SRAM based FPGA is programmed >> every system start and that Flash or Fuse based systems are preferable. > > Certification requirements > one of many system specifications. > Most systems use flash of some sort > to initialize RAM of some sort in the > face of the Stressors listed above. > >> I also read that CPLDs (Flash) in general are more robust than FPGAs. >> Can you confirm/confute this? > > You need facts, not opinions to confirm such a statement. > > -- Mike Treseler Not sure what Xilinx have to offer but certainly Altera Cyclone and Stratix FPGA parts have a built in CRC check which is run continuously via an internal clock at up to 100MHz. When the FPGA boots it is loaded with configuration and a configuration CRC calculated externally. The FPGA continuously calculates a CRC from its internal config RAM contents and if (never known it) it disagrees with the pre-programmed CRC the chip reboots. On a Stratix part I am using on a military project the reboot takes <40ms. The parts when in this configuration are deemed by the military to be as reliable as a CPLD. SlurpArticle: 100895
Hello all, I would like some feeback : I am planning to make a design in FPGA that has 4 2nd-order cascaded IIR filters. Now the question/feedback/advice which I am seeking is the following: To what resolution can I have the input and output databuses of the IIRs ? Assume there is nothing else but the IIRs in the FPGA P.S the FPGA is spartan 3 (400k gates) I made a rough estimate : I would be needing ~800-1000FFs (there is atotal of 8k) ~14 16-bit adders (do not know the total) ~8 18x18 dedicated multipliers (there is a total of 16) and a whole bunch of muxes. I estimate about ~2000 4:1 muxes/demuxes The above bunch of logic is for 4 2nd order IIRs 16 bit input databus for each IIR 16 bit output databus for each IIR 64 bit feedfwd & feedbck coeeficients for each IIR An input DC gain of 2^12 for each IIR One, and only one, 96 bit adder responsible for all the sums One, and only one, 27x64 bit multiplier responsible for all the multiplication The adder and the multipler will function at a much higher frequency than the sample rate, hence permitting them to do all the operations for all the IIRs, Sample rate is 1MHz. I am assuming that the sample rate can be multiplied up by a factor of at least of 50. 50 would give at LEAST 1cycles/operation. There are 20 sums and 20 multiplication to be done per sample period. Hence, I arrived to the conclusion that such a digital filter design will take me ~25% of the space of the FPGA. Does this sound accurate ? However I do not know how to account for routing overhead. I would appreciate previous projects citiings and how much % of the FPGA they occupied. Thx in advance -RogerArticle: 100896
Hi, I would like to share with you my an experience with error generation when inconsistant Xilinx Navigator 8.1.02i settings were made. 1. My project has two Virtex II-1500 chips in a design. The code for both chips were compiled correctly with version 7.1.4i. 2. It is the first time to compile with 8.1.02i. 3. Chip A design was successfully compiled. 4. Chip B design generated 34 errors due to trimming of some key signals. Those signals couldn't be trimmed for a correct design. After efforts of several hours were made, I finally identified the error reason: Inconsistant parameter settings caused the errors and unnecessary trimming. 1. For synthesis property/synthesis options: "Keep Hierachy", "No" is selected 2. For "Implement Design"/Property/Translate Property "Preserve Hierachy on Sub Module", Yes is selected. When compiling, signals beloging to interface between sub module and main module were trimmed and 34 Map errors were generated. The following are two error information: ERROR:MapLib:661 - LUT4 symbol "_n218330" (output signal=nREQ64_O_On) has input signal "nREQ64Pass_SDRAM<0>" which will be trimmed. See the trim report for details about why the input signal will become undriven. ERROR:MapLib:661 - LUT4 symbol "M_T_StateA/_n000919" (output signal=M_T_StateA/_n0009) has input signal "nREQ_O_R" which will be trimmed. See the trim report for details about why the input signal will become undriven. After no is selected with selection "Preserve Hierachy on Sub Module", compilation went smoothly and successfully. I think further Xilinx versions should prohibit second option to be selected when first one is selected to prevent similar error situations from happening. WengArticle: 100897
"Roger Bourne" <rover8898@hotmail.com> wrote in message news:1145558140.602899.117160@t31g2000cwb.googlegroups.com... > Hello all, > > I would like some feeback : > > I am planning to make a design in FPGA that has 4 2nd-order cascaded > IIR filters. > Now the question/feedback/advice which I am seeking is the following: > > To what resolution can I have the input and output databuses of the > IIRs ? > Assume there is nothing else but the IIRs in the FPGA > > P.S the FPGA is spartan 3 (400k gates) > > I made a rough estimate : > I would be needing ~800-1000FFs (there is atotal of 8k) > ~14 16-bit adders (do not know the total) > ~8 18x18 dedicated multipliers (there is a total of 16) > and a whole bunch of muxes. I estimate about ~2000 4:1 muxes/demuxes > > The above bunch of logic is for > 4 2nd order IIRs > 16 bit input databus for each IIR > 16 bit output databus for each IIR > 64 bit feedfwd & feedbck coeeficients for each IIR > An input DC gain of 2^12 for each IIR > One, and only one, 96 bit adder responsible for all the sums > One, and only one, 27x64 bit multiplier responsible for all the > multiplication > The adder and the multipler will function at a much higher frequency > than the sample rate, hence permitting them to do all the operations > for all the IIRs, > Sample rate is 1MHz. I am assuming that the sample rate can be > multiplied up by a factor of at least of 50. 50 would give at LEAST > 1cycles/operation. There are 20 sums and 20 multiplication to be done > per sample period. > > Hence, I arrived to the conclusion that such a digital filter design > will take me ~25% of the space of the FPGA. Does this sound accurate ? > However I do not know how to account for routing overhead. > > I would appreciate previous projects citiings and how much % of the > FPGA they occupied. > > Thx in advance > -Roger You could reduce your resource requirements significantly by implementing a multi-channel, multi-stage mechanism that manipulates your data and coefficients through one BlockRAM - eliminating most of the multiplexers - and pipelines some of the operations such as the multiply to use fewer resources overall. For these kinds of things, a little pseudocode and a spreadsheet can help to visualize how to break up the problem and verify the soultion. Are you looking specifically for a tiny solution?Article: 100898
Thats seems reasonable in terms of HW resources but I would throw in a guard of atleast another 50% till you have done an actual synthesis with P/R. For most data paths even hand placed, I usually see 1/3 of the resources can't be used, conflicts of placement etc. . So fo N known flops used, add atleast another 20% which can't be used. For your really wide 96bit adders and 64bit mult you want to pipeline those and that adds many flops. YMMV John Jakson transputer guyArticle: 100899
Dioptre schrieb: > Question: Is it possible / feasible / easy to implement a design on an > FPGA such that > two or more circuits are guaranteed not to share any part of the FPGA > hardware? While it is conceivable, that for some extreme circuits an implementation that shares ressources, none of the currenct optimization techniques can find such an implementation. No local transformation can achieve it and there are no implications between the two parts. You can be pretty sure that there will be no shared logic. On the practical side you can use the modular design flow to create a netlist for one of the parts and instantiate it twice. Additionally you can apply non overlapping area constraints to the circuits. Kolja Sulimma
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