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Falk Salewski wrote: >I am doing some research on the reliability of microcontrollers software in >comparison to hardware description languages for PLDs (CPLD/FPGA). > >Another interesting point is whether there are general benefits of one >hardware regarding reliability, e.g. in an automotive environment. > > > >I read about certification problems if a SRAM based FPGA is programmed every >system start and that Flash or Fuse based systems are preferable. I also >read that CPLDs (Flash) in general are more robust than FPGAs. > >Can you confirm/confute this? > > I know one instance where your last sentence is false. I use both Xilinx CPLD's and FPGA's in a particular project, all 5 V parts, so XC95xx and original Spartan. After having some devices popped in the field, I dug through all the data at Xilinx until I found a well-hidden document on the ESD tolerance. I forget the exact numbers, but the ESD withstand on the XC95xx CPLD parts was WOEFULLY low, and half that of the FPGA. As these parts were in parallel on the same data bus, field experience pretty much agreed with the comparison, at least. Some improvements in the ground bonding has helped, but certain users still blow out the CPLDs on occasion. I've only had one or two Spartans get blown in that whole time. JonArticle: 100901
You should be able to run 200 MHz, but make sure that the clock multiplexer is confined to a small area. And then use Global Clock lines... Peter AlfkeArticle: 100902
radarman wrote: >The Arianne problem I was referring to was the Arianne 5, the first of >which went off course and was destroyed due to a fault in it's inertial >navigation system software. > >http://sunnyday.mit.edu/accidents/Ariane5accidentreport.html > > > Wow, that was a fascinating read! Thanks, JonArticle: 100903
bjzhangwn wrote: > Thansks,I want to know what speed the Clock you list above can reach? > 50Mhz?I care the sklew when routing! 50MHz is easy...it has a half period of 10ns, and I think it's very hard to get a net delay differential that large in today's parts. I said be careful about the delay on "Use_Clk_x" before, I meant the difference in delay between Use_Clk_x and Clk_x at the FF and at the LUT that does the multiplexing. Take a good close look at the circuit, understand it, I can't give you everything. That said, you may want to implement it by instantiating the FF's and the LUT that does the multiplexing, and then applying LOCs or RLOCs to them, instead of inferring the devices as in the code snippet I gave. That way, you can be sure the FFs are close to the LUT. Finally, to be absolutely sure, you can verify with a post route back-annotated timing simulation. But this is probably overkill for 50MHz. I'll let you tell me what speed clock _you_ can reach.Article: 100904
Rick- If it's any consolation, we went through S3 pull-up/pull-down hell last summer. We ended up putting a few additional values on the board that we thought the S3 should have been able to handle internally. We also found significant variation between S3 devices. We also found issues with multi-FPGA configuration from platform Flash vs. temperature that required some undocumented FPGA-related board mods that my company won't disclose, as it took us nearly 6 weeks to get it nailed down. But with that said, I have to add the S3 is otherwise an outstanding device. Everything we want to do so far in logic we've been able to find the way. We even ported a chunk of TI/Telogy code they were using on Altera Flex devices (on a yr 2002 reference design), and with minor mods it runs perfectly. TI/Telogy guys, who normally stick to Altera like glue, seem to be impressed. -JeffArticle: 100905
Hi, "(this is what happened to a particularly unlucky Arianne rocket - look it up) " Can you show the information resource in web? Thank you. WengArticle: 100906
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1145575248.465495.215300@t31g2000cwb.googlegroups.com... > Hi, > "(this is what happened to a particularly unlucky Arianne rocket - look > it up) " > > Can you show the information resource in web? > > Thank you. > > Weng --------------------------------------------- Maybe you just didn't get that far in the posts: --------------------------------------------- radarman" <jshamlet@gmail.com> wrote in message news:1145542254.303537.102360@t31g2000cwb.googlegroups.com... > http://sunnyday.mit.edu/accidents/Ariane5accidentreport.htmlArticle: 100907
Hi, I'm interested in doing some experiments requiring a rather large number of Atmel At94k40 chips (or, in a pinch, At40k40), but not enough to be able to afford a board assembly run. At minimum 10 devices, perhaps up to 50 or so depending on how much it all costs. At the moment we're looking for a reasonably cheap source of boards with the largest-size (__k40) device soldered down and access to some reasonable subset of the pins. Basically everything else is flexible. The device itself (unsoldered) is only $50 on Digi-Key, but the only board I can find that includes this chip (the STK94) costs $500! The STK594 (note the "5") meets all my criteria, and can be used without the STK500 motherboard. The only problem is that it uses the __k10 device which is only 25% of the size of the __k40, so we'd need four times as many boards (at least!). Any ideas? - aArticle: 100908
Where I work, we aren't allowed to directly connect FPGA or CPLD pins directly to external connectors, save for on-board test points (like Mictor connectors). Everything goes through external buffers or registers. Yes, it does add latency, but it does protect hard-to-replace BGA's from damage. Of course, I work on military hardware, and reliability is a major factor. While most things are replaced at LRU (chassis) level, there are some systems where the customer is allowed to replace individual boards. Usually, this happens in a customer repair facility, and is done by military technicians, but still - it pays to go the extra mile. The other factor is that every board costs so much, that they are almost never thrown away, and instead reworked. It is much simpler to replace a buffer chip than a BGA. It is more expensive, but if you are worried about damaging boards with ESD or want to hot-slot safely, it's worth it. BTW - we use SRAM based FPGA's for everything except space applications. There, we use fusible-link devices from Actel or ASICs. A typical system will load dynamically over VME or PCI from a host controller, rather than local configuration memories - but that really shouldn't be a factor. (we do it to simplify inventory issues where a board may be sold to different customers) We do occasionally need a PAL or CPLD to implement something that just needs to be off-chip. A good example is controlling the PCI/VME based FPGA configuration process. (specifically, we use them as SVF players) We generally use flash-based devices for that, since they generally only need to be updated once - and speed isn't usually a concern. As far as I can tell, the SRAM FPGA's have been working just fine across a very wide spectrum of environmental conditions for a long time. Their reliability is actually quite good.Article: 100909
I am using global resources for two clocks. But dont want global resource for newly created signals which PAR considers as clocks. Looked at the warning messages in the map stage it reports that "Clock net -Signal Name- is sourced by combinatorial logic. This is not a good design. try to use CE of FFs......" But the referred signal is actually a gate signal to latch(LD). Why this gate signals are treated as clock nets. And from the device utilisation summary its found that 100% of the 32 BUFGs and all the DCM are used though i am using only two clocks. I strongly belive that the increased clock nets is causing problem with PAR. Also there is lot of other latches in my design but those enables are not treated as clock nets. Is there any way to force the PAR to consider these signlas as ordinary signals. Please suggest me way out. Thanks and regards Sumesh V SArticle: 100910
Hi, I am new to designing with FPGAs. I have an enable_output pin in my FPGA which if deasserted will make the o/p data pins(32 pins) to Hi-Z state. I would like to know how to make these o/p pins as Hi-Z by using the control input (i.e) enable_output. I using Verilog and Synplify Pro for synthesis and Xilinx ISE7.1 for PAR. Thanks & Regards, Srini.Article: 100911
Stephen Williams wrote: > > > Does anybody know if the Xilinx PCI Express cores from Xilinx can > run w/ Icarus Verilog? I can't seem to get access to an eval copy > to find out for myself. The link to the .tar.gz (and the .zip) seem > dead for me. > > Nor can I find out if I can use it with WebPACK or I need the full > ISE to access the actual Verilog. The last full ISE I have is 6.2, > but I can obviously get at WebPACK releases. Does WebPACK have the > CORE generators I'd need? > - -- > Steve Williams "The woods are lovely, dark and deep. > steve at icarus.com But I have promises to keep, > http://www.icarus.com and lines to code before I sleep, > http://www.picturel.com And lines to code before I sleep." "Xilinx provides you with the ability to evaluate the functionality of PCI Express 1, 4 & 8 Lane Endpoint cores using MTI precompiled functional simulation models." You don't get access to the Verilog. And it's unclear if you get the RTL for the purchased version either. (One didn't for the PCI core.) You can understand that Xilinx would lock it to their part.Article: 100912
vssumesh wrote:
> "Clock net -Signal Name- is sourced by combinatorial logic. This is not
> a good design. try to use CE of FFs......"
> But the referred signal is actually a gate signal to latch(LD). Why
> this gate signals are treated as clock nets.
To reduce skew.
> Also there is lot of other latches in my design but those enables are
> not treated as clock nets.
Eliminate the latches from your design to solve the problem.
-- Mike Treseler
Article: 100913
ghelbig@lycos.com wrote:
> You don't get access to the Verilog. And it's unclear if you get the
> RTL for the purchased version either. (One didn't for the PCI core.)
RTL costs extra.
-- Mike Treseler
Article: 100914> > "Clock net -Signal Name- is sourced by combinatorial logic. This is not >> a good design. try to use CE of FFs......" >> But the referred signal is actually a gate signal to latch(LD). Why >> this gate signals are treated as clock nets. >To reduce skew. And how can we eliminate taking enable as clock signals. And to eliminate latches is not possible as it is part of the design....Article: 100915
Hi, radarman schrieb: > Even with rad-hard chips, you still have potential SEU issues. I worked > on an unnamed satellite where we had to deal with this. We chose to use > a single part, in this case, a rad-hard Actel fuse-link part, and use > TMR (triple module redundancy) on the I/O, and internally for the logic I consider TMR on registers as good enough and never used TMR on internal modules before. For extreme requirements our company changes to very hard technologies. A Fpga is good enough to have only a few failure in time (due to radiation) on normal GEO orbit. If that's not enough (e.g. for military satellites), you need to switch to very hard Asic technologies. But a simple technology used for commercial A problem left for TMR on modul level or even system level is the voter that decides wheter your result is good or wrong. > a while at a nuclear power plant, and every critical system has at > least one backup, and in some cases, two backups. Clearly, not a > situation where you can tolerate a complete failure gracefully. Depending on your system design you may still accept a temporary device malfunction :). I agree you need to be sure no SEU could lead to a problem in a nuclear power plant and three devices could be one sollution to ensure this. > The Arianne problem I was referring to was the Arianne 5, the first of > which went off course and was destroyed due to a fault in it's inertial > navigation system software. *g* I just missunderstood the point you had with your example. After rereading your first post it was clear you mean this good example why heritage is never a replacement for a system test. bye ThomasArticle: 100916
Whenever I try to change something in a DCM, a non-reversible error appears in DRC. All the unused pins on the DCM is somehow enabled (becomes cyan), and the DRC complains about some pins having no driver. Also, trying to edit diff outputs causes non-reversible problems. I can not find anything about these issues. Any clues?Article: 100917
Hi,
I'm trying to create an array of Virtex-II BlockRam instances in
verilog using
RAMB16_S36_S36 BRAM[ram_modules-1:0] (.ADDRA(ADDRA), .ADDRB(ADDRB),
..., .DOPA(), .DOPB());
This works perfectly fine, even when I add parameters like:
RAMB16_S36_S36 #(.WRITE_MODE_A("READ_FIRST")) BRAM[ram_modules-1:0]
(.ADDRA(ADDRA), ...
However, when I add the initialization parameters, it doesn't work:
RAMB16_S36_S36 #(.WRITE_MODE_A("READ_FIRST"), .INIT_A(36'h012345678))
BRAM[ram_modules-1:0] (.ADDRA(ADDRA), ...
Compiling is ok, but trying to simulate gives one of these for each
module in the array:
# ELAB2: Warning: ELAB2_0048 increment.v (22): Actual value is
incompatible with formal "INIT_A" (mixed simulation) - actual value
will be skipped.
in Aldec Active-HDL.
I've tried a bunch of different ways to get this to work.
Initialization using the defparam statements with just one BRAM
instance works fine (but not on an array, at least that I can figure
out). I guess I could just unroll the whole thing by hand, but by now,
I'm interested in just figuring out what's going on and how to make it
work.
Anyone else run into this or have any ideas?
Much thanks
-Allan
Article: 100918"srini" <g.shrinivasan@gmail.com> writes: > Hi, > I am new to designing with FPGAs. I have an enable_output pin in my > FPGA which if deasserted will make the o/p data pins(32 pins) to Hi-Z > state. I would like to know how to make these o/p pins as Hi-Z by using > the control input (i.e) enable_output. I using Verilog and Synplify Pro > for synthesis and Xilinx ISE7.1 for PAR. > It's straightforward in VHDL: buspins <= value when OE = '1' lese (others => 'Z'); I guess in verilog it's something like: assign buspins = (OE) ? drive : 32'bz; but I'm not a verilog expert. I'm sure the Synplify help tells you all about inferring tristate pins, but I can't find it myself :-( Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conektArticle: 100919
I hav the follwoing simple code which does left shifting operation. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity counter is port ( q: inout STD_LOGIC_VECTOR (3 downto 0); clock: in STD_LOGIC; reset: in STD_LOGIC; en: in STD_LOGIC ); end counter; architecture counter of counter is signal count:std_logic_vector(3 downto 0):="0000"; begin process(clock,reset) begin if reset='0' then count<="0000"; elsif(clock='1') then if en='1' then l1: for i in 1 to 3 loop count(i)<=q(i-1); end loop l1; count(0)<='0'; else count<=q; end if; end if; q<=count; -- The q value is not getting updated with the count value. end process; end counter; The problem with this code is that the q(port) value is not getting updated with count value,though count gets updated.I did single step execution,i see the statement q<=count being executed.I used the tool Active HDL 4.2.PLEASE HELP....Article: 100920
We think we have got to the bottom of the issues that some of you had with Opencore PCI designs had with our Raggedstone1 board. FAQ page has answers here http://www.enterpoint.co.uk/moelbryn/raggedstone1_faq.html . John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low cost Spartan-3 PCI Board. http://www.enterpoint.co.ukArticle: 100921
Thanks for your reply!We also had problems with CPLDs dying according to probably to high voltages (lab course with students). We are using Spartan FPGAs in combination with busswitches as interface circuits now and have no problems any more. However, if you are using many I/O lines this additional protection needs some PCB space... seems like an advantage to microcontrollers. We let students work with Atmel ATmega16 and none of them died during the last year. And they did a lot to them... Regards Falk "radarman" <jshamlet@gmail.com> schrieb im Newsbeitrag news:1145585901.442569.73850@t31g2000cwb.googlegroups.com... > Where I work, we aren't allowed to directly connect FPGA or CPLD pins > directly to external connectors, save for on-board test points (like > Mictor connectors). Everything goes through external buffers or > registers. Yes, it does add latency, but it does protect > hard-to-replace BGA's from damage. > > Of course, I work on military hardware, and reliability is a major > factor. While most things are replaced at LRU (chassis) level, there > are some systems where the customer is allowed to replace individual > boards. Usually, this happens in a customer repair facility, and is > done by military technicians, but still - it pays to go the extra mile. > > The other factor is that every board costs so much, that they are > almost never thrown away, and instead reworked. It is much simpler to > replace a buffer chip than a BGA. > > It is more expensive, but if you are worried about damaging boards with > ESD or want to hot-slot safely, it's worth it. > > BTW - we use SRAM based FPGA's for everything except space > applications. There, we use fusible-link devices from Actel or ASICs. A > typical system will load dynamically over VME or PCI from a host > controller, rather than local configuration memories - but that really > shouldn't be a factor. (we do it to simplify inventory issues where a > board may be sold to different customers) > > We do occasionally need a PAL or CPLD to implement something that just > needs to be off-chip. A good example is controlling the PCI/VME based > FPGA configuration process. (specifically, we use them as SVF players) > We generally use flash-based devices for that, since they generally > only need to be updated once - and speed isn't usually a concern. > > As far as I can tell, the SRAM FPGA's have been working just fine > across a very wide spectrum of environmental conditions for a long > time. Their reliability is actually quite good. >Article: 100922
David Qui=F1ones wrote: > Hello Marco & Vladimir > > Unfortunately we need TCP/IP in our products, so we need to use the TCP/I= P stack and prefereably without any cost. In the relating thing to the spee= d of transmission on gigabit ethernet, we have reached more than 900 MB/s w= ith the ML403 development board and a cathegory 6 crossover cable with the = GSRD reference system, who use the Treck TCP/IP stack with Jumbo frames. Wi= thout Jumbo frames the transmission speed falls to 250 MB/s. Our specificat= ions must reach at least 350 MB/s. > > Another problem is the size of the design. The GSRD systems occupies the = 79% of the Virtex4FX12 (in the ML403 board). The best option is to use the = next FPGA, the Virtex4FX20, but the ISE WebPack, don't sinthetize this chip= . The cost of the product it's growing up!! > > The last option that I'm evaluating is the UltraController II. I have sin= thetize the XAPP807 reference design, a Gigabit webserver. The used resourc= es are minimal (two FIFOs, 20 slices and 18 LUTs) but I have several doubts= yet. The UltraController II use the PPC405 as the engine to control the te= mac (Exclusively?). I'm investigating about to expand the design to use the= PPC405 for others parrallel issues but the work flow is different like the= EDK's flow and there is no access to the PLB or OPB buses. > > Maybe the GSRD team can make a smaller gigabit design? I wait that! I would't touch UltraController II if I were you. UCII has a very poor performance due to tiny FIFO's (about 100Mbit/s according to XAPP807 datasheet), so it won't satisfy your needs. Cheers, GuruArticle: 100923
Hi, Instead of declaring count as signal , you declare it as variable and check out. I think it should work. Normally the signal gets updated at the end of the process. The use of variable is best suited for your case. Regards, SrikanthArticle: 100924
hi everybody, I am in the last year of communications department, faculty of Engineering, and I need help for my graduation project. The final stage is to interface the Spartan-3 to a USB Bluetooth dongle to support wireless voice and/or data communications modulated with DSSS (IS-95 CDMA). I need to interface the USB dongle to the PS/2 port of Spartan-3 using a PS/2-to-USB converter. I have tried to find data sheets and timing diagrams of a USB dongle in order to understand how it works but found nothing. Can anyone help? Thanks
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Compare FPGA features and resources
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