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Hi,
You're right. I never connected to outside world with the FSL bus
defined internally. I connect MicroBlaze signals directly to outside.
I will inform the team about this.
In this case, I would solve this by creating a dummy peripheral which
just tunnels the FSL signals through to the outside world.
The .mpd file would look like something like this:
BEGIN FSL_TUNNEL_TO_OUTSIDE
OPTION IPTYPE=PERIPHERAL
OPTION IMP_NETLIST=TRUE
# Define bus interface
BUS_INTERFACE BUS=MFSL, BUS_STD=FSL, BUS_TYPE=UNDEF
BUS_INTERFACE BUS=SFSL, BUS_STD=FSL, BUS_TYPE=UNDEF
# FSL slave port
PORT FSL_S_CLK = FSL_S_Clk, DIR=in, BUS=SFSL
PORT FSL_S_READ = FSL_S_Read, DIR=in, BUS=SFSL
PORT FSL_S_DATA = FSL_S_Data, DIR=out, VEC=[0:31], BUS=SFSL
PORT FSL_S_CONTROL = FSL_S_Control, DIR=out, BUS=SFSL
PORT FSL_S_EXISTS = FSL_S_Exists, DIR=out, BUS=SFSL
# FSL master port
PORT FSL_M_CLK = FSL_M_Clk, DIR = out, BUS = MFSL
PORT FSL_M_WRITE = FSL_M_Write, DIR = out, BUS = MFSL
PORT FSL_M_DATA = FSL_M_Data, DIR = out, VEC = [0:31], BUS = MFSL
PORT FSL_M_CONTROL = FSL_M_Control, DIR = out, BUS = MFSL
PORT FSL_M_FULL = FSL_M_Full, DIR = in, BUS = MFSL
# FSL master signals coming in from outside
PORT EXT_FSL_M_CLK = "", DIR=in
PORT EXT_FSL_M_WRITE = "", DIR=in
PORT EXT_FSL_M_DATA = "", DIR=out
PORT EXT_FSL_M_CONTROL = "", DIR=out
PORT EXT_FSL_M_FULL = "", DIR=out
# FSL slave signals going out to the outside
PORT EXT_FSL_S_CLK = "", DIR=out
PORT EXT_FSL_S_READ = "", DIR=out
PORT EXT_FSL_S_DATA = "", DIR=in
PORT EXT_FSL_S_CONTROL = "", DIR=in
PORT EXT_FSL_S_EXISTS = "", DIR=in
END
The VHDL code will look like this:
library ieee;
use ieee.std_logic_1164.all;
entity fsl_tunnel_to_outside is
port (
-- FSL master signals
FSL_M_Clk : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Write : out std_logic;
FSL_M_Full : in std_logic;
-- FSL slave signals
FSL_S_Clk : in std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
-- FSL master signals coming in from outside
EXT_FSL_M_CLK : in std_logic;
EXT_FSL_M_WRITE : in std_logic;
EXT_FSL_M_DATA : in std_logic_vector(0 to 31);
EXT_FSL_M_CONTROL : in std_logic;
EXT_FSL_M_FULL : out std_logic;
-- FSL slave signals going out to the outside
EXT_FSL_S_CLK : out std_logic;
EXT_FSL_S_READ : out std_logic;
EXT_FSL_S_DATA : out std_logic_vector(0 to 31);
EXT_FSL_S_CONTROL : out std_logic;
EXT_FSL_S_EXISTS : in std_logic
);
end entity fsl_tunnel_to_outside;
architecture IMP of fsl_tunnel_to_outside is
begin -- architecture IMP
FSL_M_Clk <= EXT_FSL_M_CLK;
FSL_M_Data <= EXT_FSL_M_DATA;
FSL_M_Control <= EXT_FSL_M_CONTROL;
FSL_M_Write <= EXT_FSL_M_WRITE;
EXT_FSL_M_FULL <= FSL_M_FULL;
EXT_FSL_S_CLK <= FSL_S_Clk;
EXT_FSL_S_CONTROL <= FSL_S_Control;
EXT_FSL_S_DATA <= FSL_S_Data;
EXT_FSL_S_READ <= FSL_S_Read;
FSL_S_Exists <= EXT_FSL_S_EXISTS;
end architecture IMP;
In the system.mhs you can do this now if you want a both incoming and
outgoing FSL bus
BEGIN fsl_v20
PARAMETER INSTANCE = my_fsl_incoming
PARAMETER HW_VER = 2.00.a
PARAMETER C_USE_CONTROL = 0
PORT SYS_Rst = sys_rst_s
PORT FSL_CLK = dcm_clk_s
END
BEGIN fsl_v20
PARAMETER INSTANCE = my_fsl_outgoing
PARAMETER HW_VER = 2.00.a
PARAMETER C_USE_CONTROL = 0
PORT SYS_Rst = sys_rst_s
PORT FSL_CLK = dcm_clk_s
END
BEGIN fsl_tunnel_to_outside
PARAMETER INSTANCE = fsl_tunnel_to_outside_0
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE MFSL = my_fsl_incoming
BUS_INTERFACE SFSL = my_fsl_outgoing
PORT EXT_FSL_M_Clk = EXT_FSL0_M_Clk
PORT EXT_FSL_M_Data = EXT_FSL0_M_Data
PORT EXT_FSL_M_Write = EXT_FSL0_M_Write
PORT EXT_FSL_M_Control = EXT_FSL0_M_Control
PORT EXT_FSL_M_Full = EXT_FSL0_M_Full
PORT EXT_FSL_S_Clk = EXT_FSL0_S_Clk
PORT EXT_FSL_S_Data = EXT_FSL0_S_Data
PORT EXT_FSL_S_Read = EXT_FSL0_S_Read
PORT EXT_FSL_S_Control = EXT_FSL0_S_Control
PORT EXT_FSL_S_Exists = EXT_FSL0_S_Exists
Article: 100351Personally I don't have a high opinion of the IPIF approach. To convert from to OPB to yet another bus to use with your logic does not make logical sense to me. However the Xilinx process does have the singular advantage of generating a driver as part of the automatic process. It would be worth considering do your own interface. If you do pick up the IBM spec it does look daunting but in reality all the FPGA implementations we have seen don't use anything like all the possible signalling. Signals to be concerned with are Abus, Dbus, Select, Xferack, timeout, retry, transfer error. Sometime you can get away without the last three. In combined master and slave modules you usually get an input version of any given the signal that come back from an "OR" array and an output version that feeds the "OR" array. When inactive signals should sit at '0' in order not to affect array output and an active output will then direct impress it's value onto the "or" output. There are gating signals for address and data but you can roll that into outputs by ensuring '0's when inactive. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan-3 Development Board. http://www.enterpoint.co.uk "Guru" <ales.gorkic@email.si> wrote in message news:1144360449.098556.126630@z34g2000cwc.googlegroups.com... > Hi everyone, > > I am trying to write obout 66MB/s of data to DDR memory (which is > connected to OPB bus) conneted to Virtex4FX12. For that purpose I tried > to build an OPB peripheral with master support using EDK's > Import/Create peripheral wizard. The slave registers work OK, but > master support doesn't work as it should. If DMA is enabled in IPIF > then local master access doesn't work at all. With no DMA local master > works but there is no way to control source and destination address > increment (IP2BUS or IP2IP). The most problematic is that IPIF address > increment doesn't work properly (sequence is reg0,reg0,reg1,reg2...). > That "first increment" problem appears also at DMA transfer grater than > 8 words. I am getting really desperate on this issue :( > > Does anyone has any solution for my troubles - maybe different approach > or maybe a reference design to learn from. > > Cheers, Guru >Article: 100352
I have seen that note as well, but I don't understand it. Can someone explain what "Payload compatible only" means?Article: 100353
Marco T. wrote: > Hallo, > I have contacted GRSD team, the Xilinx developers of ll_temac, ll_gemac and > multiport memory controller about porting LwIP to ll_temac. > They told me that if there is enough demand, they do it, so if someone is > interested can post here. > Then if we reach sufficient demand I'll contact GRSD team. > > -- > Many Thanks > Marco Toschi Marco, I want it too! I would also like to have a decent reference design for Virtex-4FX12 (ML403) which we all know it has lots of good hardware included (PPC and EMAC hardware cores), but the problem is size (since FX12 is the smallest of FX series). The new reference design should include: compact (one core if possible) and lightweight hard TEMAC core (probably Local Link - LL) with sizable FIFOs (to tune the core according to required performance and available BRAM) and open source lwIP stack (to avoid licensing). I hope that we get enough interest in this topic, Ales Gorkic, alias GuruArticle: 100354
Helmut Thanks for the reply. Are you implying from your answer 2 that it is permissable to invert USRCLK instead of USRCLK2 thus still conforming to the "Each edge of the slower clock must align with the falling edge of the faster clock" but not "Since clk0 is needed for feedback, it can be used instead of clk180 to clock USRCLK2 of the transceiver with the use of the transceiver's local inverter, saving a global buffer (BUFG)."? SimonArticle: 100355
Hi Manu, All of my test were performed at 100 MHz OPB_Clk. Lowering the the bus speed could maybe help. With ChipScope OPB/IBA I found out that IPIF Master Burst transfer is really slow - requiring at least 5 OPB_Clk cycles for ONE word (80MB/s). Since I have only one DDR on-board which contains also the PPC program lowering bus speed is out of the question (not enough bandwidth). The on-board (on Virtex4 MiniModuel) DDR is 16 bit wide which is impossible to connect to PLB for higher bandwidth. Regarding IPIF in EDK 8.1: Create/Import peripheral wizard generates the same source as in version 7.1. I tried to update the IPIF to newer version (opb_ipif_v2_06_a) but the problems remains. Cheers, GuruArticle: 100356
sachink321@gmail.com wrote: >How do i know how many cylinders, drives and sectors >a particularr compact flash has?????? >i have a 256mb sandisk compact flash The concept of CHS is since long outdated. But.. It depends in what context you use it. If it's an old machine with x86-BIOS you usually enter <cylinders> heads=63 sectors=255 There are three translation modes for x86-BIOS calls (INT 13h) to physical sectors CHS, LBA, and Large. Try to use LBA if that won't work use Large or as last resort CHS mode. If you build a system that is free from x86 baggage then LBA is the mode to use. Furhter reading: * http://averstak.tripod.com/fatdox/physical.htm * http://www.boot-us.com/gloss11.htm 640k ram & 512M hdd ought to be enough for anyone.. :)Article: 100357
Hello David, You don't need to use Jumbo frames to utilize whole power of Gigabit Ethernet. With Virtex4 EMACs we got more than 120MB/s data throughput with plain Ethernet frames. And PC was able to handle this data stream without any problems. We built the streaming hardware within Virtex4FX20 and developed custom protocol driver for MS Widows Ethernet stack. During testing phase we got no errors/retries. With TCP/IP stack you will get less data bandwidth, since each frame will need to have TCP/IP header, but I still think it will not worse to move to Jumbo solution. With best regards, Vladimir S. Mirgorodsky David wrote: > Hi > > I'm evaluating one Gigabit Ethernet design who use the hard Temac embedde= d in the Virtex-4 FX (ML403 evaluation board) for fast image transmision. > > The GSRD reference design (xapp546) is my best option, but have a 79% of = occupied slices and I need more space for more components and the Treck TCP= /IP used is a evaluation versi=F3n. It exist the option of the TEMAC UltraC= ontroller-II but it seem that the PowerPC processor of the Virtex-4 can't b= e used for others issues and I don't know if the uIP TCP/IP stack used in t= his design supports Jumbo frames like Treck stack. This jumbo frames are ne= eded for maximum performance at gigabit ethernet. > > Somebody have a easy solution to this problem? Another design? >=20 > Thank you very much.Article: 100358
Hi John, I thougt about doing it from scratch. It looks this is my only option. I downloaded IBM's OPB specifications and they do look daunting (about 100 pages!). In my opinion best thing to do is to implement peripheral with simple OPB master only capability (for data streaming) and DCR based control/status registers (for better response and ease of use) as suggested by IBM's CoreConnect. The only problem that bothers me is: how to start? I there any available source to start from? Otherwise It could take months just to figure out how to make a working peripheral. Cheers, GuruArticle: 100359
"Guru" <ales.gorkic@email.si> wrote in message news:1144398077.349775.302060@i40g2000cwc.googlegroups.com... > > Marco T. wrote: >> Hallo, >> I have contacted GRSD team, the Xilinx developers of ll_temac, ll_gemac >> and >> multiport memory controller about porting LwIP to ll_temac. >> They told me that if there is enough demand, they do it, so if someone is >> interested can post here. >> Then if we reach sufficient demand I'll contact GRSD team. >> >> -- >> Many Thanks >> Marco Toschi > > Marco, I want it too! > > I would also like to have a decent reference design for Virtex-4FX12 > (ML403) which we all know it has lots of good hardware included (PPC > and EMAC hardware cores), but the problem is size (since FX12 is the > smallest of FX series). The new reference design should include: > compact (one core if possible) and lightweight hard TEMAC core > (probably Local Link - LL) with sizable FIFOs (to tune the core > according to required performance and available BRAM) and open source > lwIP stack (to avoid licensing). > > I hope that we get enough interest in this topic, > > Ales Gorkic, alias Guru > Hello, I opened a webcase about it. Only plb_temac will support lwip and we can use it when edk sp2 will be released. Now GSRD team has developed a MPMC 2 which is very customizable. As soon as sp2 will be released I will test a system based on plb_temac and mpmc 2 controller. MarcoArticle: 100360
is anyone know what is means of this error please! thanks advance! C:\copy_project\exemple5\top_ise\toto2>map processor_stub.ngd Release 8.1.03i - Map I.27 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Using target part "4vfx12ff668-10". Mapping design into LUTs... ERROR:MapLib:711 - A Modular Design has been detected. Map has detected an expanded block processor_i/plb_bram_if_cntlr_1 that is not a Module with AREA_GROUP AG_processor_i/plb_bram_if_cntlr_1. This is not a recommended practice. Please refer to the Modular Design chapter in the Development System Reference Guide for more information. Design Summary -------------- Number of errors : 1 Number of warnings : 4 C:\copy_project\exemple5\top_ise\toto2>ngdbuild -modular initial -p xc4vfx12ff668-10 -uc processor_s tub.ucf processor_stub Release 8.1.03i - ngdbuild I.27 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -modular initial -p xc4vfx12ff668-10 -uc processor_stub.ucf processor_stub Reading NGO file 'C:/copy_project/exemple5/top_ise/toto2/processor_stub.ngc' ... Loading design module "C:\copy_project\exemple5\top_ise\toto2/ppc405_0_wrapper.ngc"... Loading design module "C:\copy_project\exemple5\top_ise\toto2/jtagppc_0_wrapper.ngc"... Loading design module "C:\copy_project\exemple5\top_ise\toto2/reset_block_wrapper.ngc"... Loading design module "C:\copy_project\exemple5\top_ise\toto2/plb_wrapper.ngc"... Loading design module "C:\copy_project\exemple5\top_ise\toto2/opb_wrapper.ngc"... Loading design module "C:\copy_project\exemple5\top_ise\toto2/plb2opb_wrapper.ngc"... Loading design module "C:\copy_project\exemple5\top_ise\toto2/rs232_wrapper.ngc"... Loading design module "C:\copy_project\exemple5\top_ise\toto2/flash_2mx16_wrapper.ngc"... Loading design module "C:\copy_project\exemple5\top_ise\toto2/plb_bram_if_cntlr_1_wrapper.ngc"... Loading design module "C:\copy_project\exemple5\top_ise\toto2/plb_bram_if_cntlr_1_bram_wrapper.ngc"... Loading design module "C:\copy_project\exemple5\top_ise\toto2/flash_2mx16_util_bus_split_0_wrapper.ngc "... Loading design module "C:\copy_project\exemple5\top_ise\toto2/dcm_0_wrapper.ngc"... Applying constraints in "processor_stub.ucf" to the design... Checking timing specifications ... INFO:XdmHelpers:851 - TNM "sys_clk_pin", used in period specification "TS_sys_clk_pin", was traced into DCM_ADV instance "processor_i/dcm_0/dcm_0/DCM_ADV_INST". The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLK0: TS_processor_i_dcm_0_dcm_0_CLK0_BUF=PERIOD processor_i_dcm_0_dcm_0_CLK0_BUF TS_sys_clk_pin*1.000000 HIGH 50.000000% Checking expanded design ... WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_ADDR_S_H_REG0' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_CS_REG1' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_CS_REG2' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_CS_REG3' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_CE_REG0' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_RDCE_REG0' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_WRCE_REG0' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_CE_REG1' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_RDCE_REG1' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_WRCE_REG1' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_CE_REG2' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_RDCE_REG2' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_WRCE_REG2' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_CE_REG3' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_RDCE_REG3' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/flash_2mx16/flash_2mx16/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/ I_BKEND_WRCE_REG3' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTAC HMENT/I_ADDRESS_COUNTER/I_SIZE_S_H_REG0' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTAC HMENT/I_ADDRESS_COUNTER/I_SIZE_S_H_REG1' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTAC HMENT/I_DECODER/I_ADDR_S_H_REG0' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTAC HMENT/I_DECODER/I_ADDR_S_H_REG1' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTAC HMENT/I_DECODER/I_ADDR_S_H_REG2' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTAC HMENT/I_DECODER/I_BKEND_CE_REG0' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTAC HMENT/I_DECODER/I_BKEND_RDCE_REG0' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTAC HMENT/I_DECODER/I_BKEND_WRCE_REG0' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTAC HMENT/I_DECODER/I_CS_SIZE_REG0' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTAC HMENT/I_DECODER/I_CS_SIZE_REG1' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'processor_i/plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTAC HMENT/I_DECODER/I_CS_SIZE_REG2' has unconnected output pin WARNING:NgdBuild:885 - logical block 'module_reconfig' with type 'mode_reconfig' is unexpanded and will be presumed to be a module. NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 28 Writing NGD file "processor_stub.ngd" ... Writing NGDBUILD log file "processor_stub.bld"... NGDBUILD done. C:\copy_project\exemple5\top_ise\toto2>map processor_stub.ngd Release 8.1.03i - Map I.27 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Using target part "4vfx12ff668-10". Mapping design into LUTs... ERROR:MapLib:711 - A Modular Design has been detected. Map has detected an expanded block processor_i/plb_bram_if_cntlr_1_bram that is not a Module with AREA_GROUP GRP0. This is not a recommended practice. Please refer to the Modular Design chapter in the Development System Reference Guide for more information. Design Summary -------------- Number of errors : 1 Number of warnings : 3 C:\copy_project\exemple5\top_ise\toto2>Article: 100361
On 7 Apr 2006 02:09:57 -0700, "Guru" <ales.gorkic@email.si> wrote: >Hi John, > >I thougt about doing it from scratch. It looks this is my only option. >I downloaded IBM's OPB specifications and they do look daunting (about >100 pages!). In my opinion best thing to do is to implement peripheral >with simple OPB master only capability (for data streaming) and DCR >based control/status registers (for better response and ease of use) as >suggested by IBM's CoreConnect. >The only problem that bothers me is: how to start? I there any >available source to start from? Otherwise It could take months just to >figure out how to make a working peripheral. > >Cheers, Guru I am going on holidays right now, and have little time, but I will try to give you a little help. I have designed three OPB peripherals with slave and master interface (no DCR, as they are intended for microblaze), and they really work fine and are easy to design. The master part must be designed as follows: * for transactions limited to one OPB access: when needing to make a transaction, raise M_request. when MOPB_MGrant received, raise M_select and lower M_request. M_select sould be lowered after receiving xferack, errack, timeout or retry. Treat results as necessary (that is your personal option). *for various succesive transactions Same as before, but raising M_bus_lock after MOPB_MGrant and until one-before-last transaction xferAck. All this is easily derived form IBM "On-Chip peripheral bus", chapter 5.1 OPB Bus arbitration protocol, pages 32 to 34. Best regards, Zara PS Dont hesitate to ask anything else, but I will not be available until after Easter holidays, on April 17thArticle: 100362
I have put an example of a slave only on our website techitips page http://www.enterpoint.co.uk/techitips/techitips.html. It is a dual port ram in VHDL wired one side onto the OPB. I believe this is a working one that I grabbed but I have not checked so any problems let me know. John Adair Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 Development Board. http://www.enterpoint.co.uk "Guru" <ales.gorkic@email.si> wrote in message news:1144400997.182833.33850@i39g2000cwa.googlegroups.com... > Hi John, > > I thougt about doing it from scratch. It looks this is my only option. > I downloaded IBM's OPB specifications and they do look daunting (about > 100 pages!). In my opinion best thing to do is to implement peripheral > with simple OPB master only capability (for data streaming) and DCR > based control/status registers (for better response and ease of use) as > suggested by IBM's CoreConnect. > The only problem that bothers me is: how to start? I there any > available source to start from? Otherwise It could take months just to > figure out how to make a working peripheral. > > Cheers, Guru >Article: 100363
Thnx John and Zara I will take Johns VHDL as an example for building OPB master only (or master/slave) peripheral. Does anybody knows anything about DCR bus? Would I benefit a lot using it? Cheers, GuruArticle: 100364
Hi I am trying to implement a shared memory interface between PPC and FPGA fabric. I am using EDK to create a dual port RAM and connect it to a DSOCM controller. I have been able to write to BlockRAM from my application code. My question is that how do I connect the other port of the BRAM to my FPGA design? Should the HDL module be added as a core from the " import peripheral" utility? If so, then which bus should it connect to? Thanks AmitArticle: 100365
Rohit Tandon wrote:
[...]
> Thanks to both of you for your quick replies. Actually I was using
> output of one stage of the shift register in the logic elsewhere in the
> design, when I modified it, XST was infering a SRL (without the need
> for XST SRL tool option).
>
> I was wondering if a similar solution can be applied to another problem
> where I need to just add some 2-cycles of delay to a 4-bit register.
> For instance if I have something like this:
>
> reg [3:0] reg_in ;
> reg [3:0] reg_out ;
> reg [3:0] reg_r1 ;
>
> always @ (posedge clk)
> begin
> {reg_out, reg_r1} <= {reg_r1, reg_in} ;
> end
>
> Can this logic be modified to make use of SRLs or do I need to
> invariably implement it via flops.
Howdy Rohit,
Unless it is somehow broken in the version of XST that you are using,
it should be possible with the correct syntax. You'll have to look it
up the SRL template for Verilog in XST. A complete WAG: maybe start by
breaking the reg_out portion of your statement to a separate line.
Have fun,
Marc
Article: 100366Guru wrote: > Thnx John and Zara > > I will take Johns VHDL as an example for building OPB master only (or > master/slave) peripheral. > Does anybody knows anything about DCR bus? > Would I benefit a lot using it? > > Cheers, Guru > DCR is for control reg, not data flow.Article: 100367
> .. and another testing use, is to use the pin to bring out an > internal signal, for probing. > - ie I'd add a resistor _and_ a probe pad. > [ you also then side-step his input, as now your use is > clearly not in that appnote :) ] I've just noticed this thread. When I worked for Nortel in Belfast the manufacturing guys didn't like it if _any_ non power pins were hard assigned to power or ground as it stopped them using the flying probe tester to test boards after manufacture. Do you know who's going to be building/testing your boards 5 years down the line? As the others have said using resistors adds a bit of flexibility during debug and allows a much easier cut and strap to fix things if you ever make a schematic mistake (not that any of us ever do!). Nial ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 561 6291 42/2 Hardengreen Business Park Fax: +44 131 561 6327 Dalkeith, Midlothian EH22 3NU www.nialstewartdevelopments.co.ukArticle: 100368
what is architectural diffrence between block ram & distributed ram?Article: 100369
sachink321@gmail.com wrote: > Environment in which system works: > > Microblaze softcore processor on spartan 3 fpga board > compact flash, acting as a mass storage. > > How to access the compact flash in embedded applications > write to and read from the compact flash? how to access the FAT table? > to which sector i need to write, which address? > > which mode of addressing is easy way out > CHS or LBA?? > > I got no clue how to access, it would be great help if i could > understand in and out of doing tht becoz i need to write a code in C > > Thanks in advance > http://www.compactflash.org/faqs/faq.htm You can register for free and download the CF3 spec from there. If you are just using the CF for mass storage that does not have to be read by a PC, then you needn't format it with a PC file structure. In that case it is simply a matter of converting your address to a sector and offset into the sector. There is a bit less bookkeeping if you use LBA, but either one is relatively easy.Article: 100370
sachink321@gmail.com wrote: > How do i know how many cylinders, drives and sectors > a particularr compact flash has?????? > > i have a 256mb sandisk compact flash > Issue the identify command to the card and parse the sector worth of data that it returns. It's all in there.Article: 100371
Errrr... When I typed the previous post, I did not have access to the project navigator software... So... > I had tried that before but I was confused as the STARTUP_SPARTAN3 > module had both GSRin and GSRout pins. I had assumed that the module > was only for simulation purposes. > ( At least I think it was the STARTUP_SPARTAN3 module. There were only > 2 modules that had began with the wotd "startup", and I had tried them > both. They were identical.) Today, (that I have access to the projects navigator software) I took a closer look at both modules that began with the word "startup". I realized that both modules are in fact NOT the same. I was able to locate the 3 pin STARTUP_SPARTAN3 module. ( I was previously selecting the STARBUF_SPARTAN3 module. Spelling is too similar). Thank you for your help. -RogerArticle: 100372
Steve Knapp wrote:
>
> The BGA packages have superior signal integrity.
>
Well, the existing VQ100's aren't all that horrible; and if you
can make this or the next generation available in a ground paddle QFP
or QFN, the VQ100 size packages might even be better than the CP132's.
Toss in 2.5V-or-less I/O banks with better performance, and there'll
be chocolate cake all 'round.
>
> The different SSO numbers on the quad-flat packages are
> purposely lower due to their merely average signal integrity.
>
Well, those mysterious "fours" seem to have reappeared across
the board again for the S3E differential drivers in VQ/PQ packages,
with the spiffy well-balanced current mode drivers once again
inconsistently assigned the same limit as have the older voltage
mode, psuedo-differential, CMOS-with-resistors BLVDS outputs.
Those mystery fours also do not show the expected improvement in the
smaller VQ package as do both the single ended standards and the latest
Spartan-3 SSO limits for their current mode differential drivers.
In Spartan-3, the datasheet differential SSO's underwent the
following series of gyrations:
- DS099-3 (v1.1) July 11, 2003
- no SSO lmits in datasheet
- DS099-3 (v1.3) March 4, 2004
- blank SSO table column for PQ/VQ packages
- blank SSO for all differential standards, PQ/VQ/BGA
- DS099-3 (v1.4) August 24, 2004
- deleted SSO table column for VQ/PQ packages
- all differential drivers, of any type, in BGA, have a listed
SSO limit of 4
- LVDS_25_DCI input SSO limit of 4 in BGA
- DS099-3 (v1.5) December 17, 2004
- reappearance of VQ/PQ packages, with mysterious 4's across
the board for the balanced current mode drivers for VQ/PQ/BGA
- VQ/PQ limit of 1 or 2 for BLVDS/PECL
- LVDS_25_DCI input SSO limit of 4
- DS099-3 (v1.6) August 19, 2005
- has more reasonable numbers for some of the current mode
drivers, with better numbers for the smallest package
as would be expected
- VQ/PQ limit of 1 or 2 for BLVDS/PECL
- LVDS_25_DCI input SSO limits have vanished
- DS099-3 (v2.0) April 3, 2006
- and even as we speak, your latest S3 datasheet has again
improved the current mode driver SSO limits for the ones
formerly stuck at '4'
>
>Also, SSOs are only for outputs. You can have as many LVDS inputs
>that will fit in an I/O bank.
>
For S3, Austin Lesea has indicated [2] that the LVDS_25_DCI numbers
in the S3 datasheet SSO tables were there to handle the DCI terminator
current; however, those DCI "fours" were removed in later SSO tables.
I'd avoid using many parallel DCI inputs in the same VQ/PQ bank [1,3]
without first having some measurements of the internal DCI startup
VCCO rail collapse.
Thankfully, S3E now has those approximately 120 ohm DT terminations.
Brian
[1] http://groups.google.com/group/comp.arch.fpga/msg/1ddb0bd333382d06
[2] http://groups.google.com/group/comp.arch.fpga/msg/52a0a4a0dbe79ebe
[3] http://groups.google.com/group/comp.arch.fpga/msg/428d53c767e64c9a
Article: 100373
Hi Rohit,
"Rohit Tandon" <rohit2000s@gmail.com> wrote in message
news:1144331753.867112.287130@e56g2000cwe.googlegroups.com...
>
> I was wondering if a similar solution can be applied to another problem
> where I need to just add some 2-cycles of delay to a 4-bit register.
> For instance if I have something like this:
>
> reg [3:0] reg_in ;
> reg [3:0] reg_out ;
> reg [3:0] reg_r1 ;
>
> always @ (posedge clk)
> begin
> {reg_out, reg_r1} <= {reg_r1, reg_in} ;
> end
>
> Can this logic be modified to make use of SRLs or do I need to
> invariably implement it via flops.
I'm no Verilog expert, but that looks like it should work without
modification. Certainly there should be no need for the delay-line signals
to have related names or be in elements of the same array for the tool to
detect a shift register.
However, you may find that XST will not bother to use SRL16s for such a
short delay line. In that case you might find you need to instantiate them
if you really really want them.
Cheers,
-Ben-
Article: 100374thanks for the info. Cheers Paul Eli Hughes wrote: > I have used this test with Kinston RAM (512MB) that I bought from the > digilent website. I remeber that I had to get some settings correct in > the constraints file and the mhs file before RAM would work correctly. > IF I remember correctly, the phase shift on the DCM for the DDR had to > be changed. Here are my settings: > > #INST "dcm_1/dcm_1/DCM_INST" CLKOUT_PHASE_SHIFT = "FIXED"; > #INST "dcm_1/dcm_1/DCM_INST" PHASE_SHIFT = "60"; > > > BEGIN plb_ddr > PARAMETER INSTANCE = DDR_512MB_64Mx64_rank2_row13_col10_cl2_5 > PARAMETER HW_VER = 1.11.a > PARAMETER C_PLB_CLK_PERIOD_PS = 10000 > PARAMETER C_NUM_BANKS_MEM = 2 > PARAMETER C_NUM_CLK_PAIRS = 4 > PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1 > PARAMETER C_REG_DIMM = 0 > PARAMETER C_DDR_TMRD = 20000 > PARAMETER C_DDR_TWR = 20000 > PARAMETER C_DDR_TRAS = 60000 > PARAMETER C_DDR_TRC = 90000 > PARAMETER C_DDR_TRFC = 100000 > PARAMETER C_DDR_TRCD = 30000 > PARAMETER C_DDR_TRRD = 20000 > PARAMETER C_DDR_TRP = 30000 > PARAMETER C_DDR_TREFC = 70300000 > PARAMETER C_DDR_AWIDTH = 13 > PARAMETER C_DDR_COL_AWIDTH = 10 > PARAMETER C_DDR_BANK_AWIDTH = 2 > PARAMETER C_DDR_DWIDTH = 64 > PARAMETER C_DDR_CAS_LAT = 3 > PARAMETER C_MEM0_BASEADDR = 0x00000000 > PARAMETER C_MEM0_HIGHADDR = 0x0fffffff > PARAMETER C_MEM1_BASEADDR = 0xe0000000 > PARAMETER C_MEM1_HIGHADDR = 0xefffffff > BUS_INTERFACE SPLB = plb > PORT PLB_Clk = sys_clk_s > PORT DDR_Addr = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr > PORT DDR_BankAddr = > fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr > PORT DDR_CASn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn > PORT DDR_CKE = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE > PORT DDR_CSn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn > PORT DDR_RASn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn > PORT DDR_WEn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn > PORT DDR_DM = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM > PORT DDR_DQS = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS > PORT DDR_DQ = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ > PORT DDR_Clk = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk > & ddr_clk_feedback_out_s > PORT DDR_Clkn = > fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn & 0b0 > PORT Clk90_in = clk_90_s > PORT Clk90_in_n = clk_90_n_s > PORT PLB_Clk_n = sys_clk_n_s > PORT DDR_Clk90_in = ddr_clk_90_s > PORT DDR_Clk90_in_n = ddr_clk_90_n_s > END > > > > > > Paul Lee wrote: > > hi, > > > > I just carried out BIST test on the XUPV2P board and I have been > > running the memory test several times and still getting the same > > failure. > > > > The DDR used for test is a 512 Mb. > > Has anyone experience this problem or could the test been designed to > > test a 256 Mb instead of 512 Mb ? > > > > Cheers > > > > Paul > > > > > > DDR SDRAM Test: Rank 0 > > ---------------------- > > Running Data Walking 1's Test... SUCCESS! > > Running Data Walking 0's Test... SUCCESS! > > Running Address Walking 1's Test... SUCCESS! > > Running Address Walking 0's Test... SUCCESS! > > Running Device Pattern 1 Test... FAILED! > > Address: 0x03FFEB70, Expected: 0x00000000007FFD6F, Actual: > > 0x00000000FF7FFD6F > > > > DDR SDRAM Test: Rank 1 > > ---------------------- > > Running Data Walking 1's Test... SUCCESS! > > Running Data Walking 0's Test... SUCCESS! > > Running Address Walking 1's Test... SUCCESS! > > Running Address Walking 0's Test... SUCCESS! > > Running Device Pattern 1 Test... FAILED! > > Address: 0x17FFEB70, Expected: 0x0000000000FFFD6F, Actual: > > 0x00000000FFFFFD6F > >
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