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"John_H" <johnhandwork@mail.com> wrote in message news:xCgfg.13419$U_2.899@trnddc05... > > If your clock is 20 MHz, doing the 115/31 might be reasonable but it > sure isn't single-clock friendly! > > Another consideration: does this value get used somewhere that you can > algebraically manipulate the values so a /31 or /sqrt(21) can be "pulled > in" to other number manipulation? > > PLEASE consider the multiplier. My clock is only 3.92MHz, and i design in a 0.15um process, timing won't be an issue here. Yeah, 1/31 can be factored into other number multiplications, but again, it will affect precision there. It's all a matter of compromise between different choice. Thank you for the ideas.Article: 103376
"Kolja Sulimma" <news@sulimma.de> wrote in message > > Note that a division or multiplication by a power of 2 is free in > hardware. Also note, that multiplication by a constant is a lot cheaper > and faster than general multiplication. > > Lets see: > > (X*59)/16 = (X*64 - X*4-X)/16 > > So X*59/16 uses only two adders. > > (X*119)/32 = (X*128-X*8-X)/32 > Two adders, even more precision. > > Y= X*4 + X*32 > (X*15195)/4096 = X*16*1024 - Y*32 - Y > Three adders. Very high precision: > > I doubt you can beat this with any other approach. > > Kolja Sulimma Yeah, in the implementation, this technique is used for all my multipliers, since I have another set of scaling as well, like 17/sqrt(10), 17/sqrt(20), etc. I will make use of this saving. Thank you for your input.Article: 103377
I think your problem inherently cannot be solved if you assume that A and B can start rising at any time, and that input thresholds and through-delays can vary by small amounts, as thy inevitably will. If you reduce your requirements to an unambiguous output, even if it is the "wrong" one (whatever wrong means when things happen essentially simultaneously) then the problem reminds me of metastability resolution, which will usually occur in a short time (although theoretically -but only theoretically- unbounded). The faster the circuitry, the smaller your "no-man's land" of uncertainty, and the faster the resolutio. I would, therefore, go with the fastest LUT-based FPGA. You can imagine which one I have in mind. So: theoretically it's unsolvable, but you can get very close with modern circuits... Peter Alfke, speculating at home. ================================= Adam Megacz wrote: > I've been having a really hard time coming up with a design for a > robust clockless arbiter in an FPGA, and was wondering if anybody here > can provide input. By robust, I mean that it works correctly with > probability=1 and its output never glitches, but may take an unbounded > amount of time to resolve. > > Charles Seitz describes a solution in custom VLSI on page 260 of Mead > and Conway's _Introduction to VLSI Systems_, but this assumes you have > control over gate threshholds and can make some of them substantially > higher than others. > > The basic component that causes problems is the "interlock", a module > with two inputs A,B and two outputs X,Y. > > +---------------+ > A -----> | | -----> X > | Interlock | > B -----> | | -----> Y > +---------------+ > > All signals start low. If A+ (A rises) before B+, then X+. If B+ > before A+, then Y+. Once one of the outputs rises, the other one will > not rise until the device is reset (assume some sort of reset signal). > The important part here is that the interlock can take as long as it > likes to raise one of the outputs, but it must raise exactly one of > them, and cannot lower it once raised (ie no glitching). > > I'm working with Atmel FPGAs, but advice based on other devices would > be just as helpful. I thought of using the "internal feedback line" > to feed one of the 3-LUT's outputs back into one of its inputs as half > of an interlock -- the state of the feedback line being used to > determine if signal A+ has already arrived. But the problem is that > you might have A+ arrive, which causes the output of the 3-LUT to > transition, but then B+ might arrive *before* the LUT's output > transition arrives back at the third input to the LUT. > > Any pointers? I've come across a rather depressing paper concluding > that this isn't possible on the (extremely old) XC4000, but I'm sort > of hoping against hope that things may have changed: > > http://www.iccd-conference.org/proceedings/1998/90990360.pdf > > This paper claims to have a solution, but doesn't go into detail, so I > suspect that they may be overlooking something. > > http://citeseer.ist.psu.edu/maheswaran94hazardfree.html > > Thanks for any pointers... > > - a > > -- > PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380Article: 103378
Derek Simmons wrote: > I have had experience managing workgroups of engineers working with MS > VisualStudio. The project was started with SourceSafe but we switched > to CVS. We gained availability - people from off site could access the > CVS source trees more easily. But what we lost was convenience and easy > of use of being able to check in changes from within VisualStudio. And, > I couldn't determine if it was unfamiliarity with a new tool, but when > we switched to CVS, conflict resolution became an issue. CVS is getting very long in the tooth. At some point I recommend you try Subversion; it makes distributed development very smooth, including conflict resolution. There is also a VS plugin (AnkhSVN, http://ankhsvn.tigris.org/), as well as a very slick Explorer plugin (TortoiseSVN, http://tortoisesvn.tigris.org/). > > I have bid on projects that I have had in mind to have 4 to 8 engineers > working on designs. What I have been on the look out for is workgroup > software that integrates with the development environment so that > engineers can stay focused on what they are working on and not > distracted by resolving conflicts. I realize a lot of this has to do > with who is working with what files. To summarize, I'm looking for > something that I cost justify that it will increase employee > efficiency. > > Is Altera or any body that Altera has a partnership with working on a > workgroup development tools that integrate into QuartusII and SOPC > Builder?Article: 103379
Mike Treseler wrote: > kevinwolfe@gmail.com wrote: > > Our group is using Subversion. What > > I am hoping to do is to incorporate the Subversion-stored revision > > number into the actual design (working on an FPGA). I would love to > > grab the design's Rev. #, store it as a constant in some register map, > > which is readable by another system (i.e. seamless, automatic firmware > > version control). > > Maybe subversion fills in revision headers like CVS. > Have a tcl or bash script grab > the revision header line, say > -- $Revision: 1.42 $ > and convert it to a vhdl package file > with a vector constant, say > constant revision_c : byte_t := x"8e"; > that becomes readback data. It doesn't; this is a deliberate design decision. However, there are several ways of finding revision data from the command line[1] (or makefile). The main gotcha here is that your build might quite easily be from a 'mixed revision' working copy, if you have selectively updated it. [1] see the Subversion book http://svnbook.red-bean.com/nightly/en/svn.ref.html#svn.ref.svn or built-in help for command summaries. > > -- Mike TreselerArticle: 103380
If best precision is what you need, just add more bits. Multiply by 237/64, 475/128, 950/256 or 1899/512. H.Article: 103381
"Antti" <Antti.Lukats@xilant.com> wrote in message news:1148992171.933618.57260@j55g2000cwa.googlegroups.com... > well what you have done already is an IP core, > so what is what you actually want todo? > > a <= b or c; > > the above as example is an IP core, in the matter of fact I have sold > such a IP core ! > > Antti > How do you create a targetted netlist version?Article: 103382
Mr. Ken schrieb: > Yeah, in the implementation, this technique is used for all my multipliers, > since I have another > set of scaling as well, like 17/sqrt(10), 17/sqrt(20), etc. I will make use > of this saving. If you multiply the same X by different scales, you can share intermediate results between the constant coefficient multipliers. Kolja SulimmaArticle: 103383
"Kolja Sulimma" <news@sulimma.de> wrote in message news:447e8b09$0$4502$9b4e6d93@newsread2.arcor-online.net... > Mr. Ken schrieb: > > > Yeah, in the implementation, this technique is used for all my multipliers, > > since I have another > > set of scaling as well, like 17/sqrt(10), 17/sqrt(20), etc. I will make use > > of this saving. > > If you multiply the same X by different scales, you can share > intermediate results between the constant coefficient multipliers. > > Kolja Sulimma True. Intermediate results will be shared. After studying the following document, I realized that dividing by constant can be implemented by same technique. http://www.hackersdelight.org/divcMore.pdfArticle: 103384
Hi, in a test implementation (ISE 8.1) of a Picoblaze core in a XC4VFX12-10 device the maximum frequency is about 110 MHz (55MIPS). In the Picoblaze product brief (http://www.xilinx.com/bvdocs/ipcenter/data_sheet/picoblaze_productbrief.pdf) the performance is 102 MIPS -> 204MHz. Anybody has an idea how to increase the maximum frequency on our Picoblaze test implementation? Is there any reference implementation for the V4 FX12 available? Many thanks, AlexanderArticle: 103385
Alexander Werger wrote: > Hi, > in a test implementation (ISE 8.1) of a Picoblaze core in a XC4VFX12-10 > device the maximum frequency is about 110 MHz (55MIPS). > In the Picoblaze product brief > (http://www.xilinx.com/bvdocs/ipcenter/data_sheet/picoblaze_productbrief.pdf) > the performance is 102 MIPS -> 204MHz. > Anybody has an idea how to increase the maximum frequency on our Picoblaze > test implementation? Is there any reference implementation for the V4 FX12 > available? > > Many thanks, > Alexander Hi Alex, you can also try to use the picoblaze C compiler on www.poderico.co.uk FrancescoArticle: 103386
Hey Tim, thank you for the part number! A think that is the alternative we could go for if we find no "built-in" MAC address. This question we have to clarify with Memec directly first. Greets Henryk Tim schrieb: > Antti wrote > > "Tim" schrieb > >> > >> AFAIR one of the Dallas 1-wire chips supplies a valid MAC address if you > >> have a spare pin and some glue to add one to your board. > >> > > if you refer to onewire unique ID then this is not valid MAC address > > > > you can use onewire memory to store a valid MAC but you must > > then yourself obtain the MAC and write it to memory location > > I'm not an expert, but Maxim/Dallas advertise the DS2502-E48 as providing a > unique and valid MAC address. I suppose they could be wrong.Article: 103387
Peter Alfke schrieb: > The faster the circuitry, the smaller your "no-man's land" of > uncertainty, and the faster the resolutio. I would, therefore, go with > the fastest LUT-based FPGA. You can imagine which one I have in mind. 22V10 ?? SCNR ;-) Regards FalkArticle: 103388
Alexander Werger schrieb: > Hi, > in a test implementation (ISE 8.1) of a Picoblaze core in a XC4VFX12-10 > device the maximum frequency is about 110 MHz (55MIPS). > In the Picoblaze product brief > (http://www.xilinx.com/bvdocs/ipcenter/data_sheet/picoblaze_productbrief.pdf) > the performance is 102 MIPS -> 204MHz. > Anybody has an idea how to increase the maximum frequency on our Picoblaze > test implementation? Is there any reference implementation for the V4 FX12 Register the IO-bus. If you dont need access to BRAM via the IO bus, this will increase clock speed significantly. I remember Picoblaze reacing ~ 80 MHz in Spartan-3. Regards FalkArticle: 103389
hello guys.. i was trying to generate a ddr sdram controller using the mig tool of xilinx But my problem is the tool saying my pin assignment(ucf written looking to the board scematic) are wrong.when i tried to verify using the verify your ucf tab from Mig. >From the board shematic i can see 10 banks but in the mig tool there is only 9 banks is there is any problem in the mig pin assignments thanks in advanceArticle: 103390
Hello guys.. Please anyone help me get a ddr sdram controller for the v4lx60 board. Is the Mig tool is enough. thanks in advanceArticle: 103391
"water7" <krbyxtrm@gmail.com> wrote in message news:1149029612.426459.236830@g10g2000cwb.googlegroups.com... > hi, what is the difference for designing a PCI card for a desktop > motherboard and with a Single Board Computer(SBC)? should a PCI card > designed for Desktop PC work on SBC's? > -k- Yes, as long as you can physically plug it in and it matches the interface voltage. Most SBCs I've seen come in PC104+ format. I've used an adaptor in one project that allows a standard form PCI card to be plugged in, I've also developed a PC104+ board that an SBC plugged on to. Nial.Article: 103392
Hi, I'm having an abundance of Xilinx MapLib:661 errors. e.g: ERROR:MapLib:661 - LUT4_L symbol "signal" has input signal "signal" which will be trimmed. There aren't any suggestions in the Xilinx Answers database (at least not listed with that error code). Looking through c.a.fpga, a few people have asked questions about why this is happening and how to fix it (or workaround it), but there weren't any responses, but hopefully someone who had the problem before solved it and is now reading this... The error seems to change depending on different permuations of "Trim Unconnected Signals", "Preserve Hierarchy on Sub Module" and a few other options, but I can't get it to go away. I'm guessing this is a Xilinx mapper bug, and have filed a web case, but I'm not expecting much via that channel, sadly. Cheers, JonArticle: 103393
I have used it before and it seems to work fine running at 2.5 GBPS via VXS backplane. Roger wrote: > I'm planning on using the TXPOLARITY and RXPOLARITY attributes in the RIOs > on a Virtex-II Pro device (via Aurora cores) to swap the function of the N > and P lines in order to help improve the path of PCB tracks to an edge > connector. > > Has anyone used this polarity swapping capability before? Does it work OK? > Are there any "undocumented features" or pitfalls that I should know about > before designing the board in this way? > > TIA, > > Rog.Article: 103394
There are a few tweeks that we have done previously in Spartan-3 architecture and from my memory we got 30-50% increase. Basically there are some hacks arround the code memory that can give this improvement if Ken Chapman hasn't put these in since last time I looked. It may be possible to the same in V4 but I have not tried yet. If I get around to it I will put it with our other PicoBlaze material on out TechiTips website page http://www.enterpoint.co.uk/techitips/techitips.html. John Adair Enterpoint Ltd. - Home of Hollybush1. The PC104+ FPGA Development Board. http://www.enterpoint.co.uk "Alexander Werger" <awerger@web.de> wrote in message news:e5m52t$b0i$02$1@news.t-online.com... > Hi, > in a test implementation (ISE 8.1) of a Picoblaze core in a XC4VFX12-10 > device the maximum frequency is about 110 MHz (55MIPS). > In the Picoblaze product brief > (http://www.xilinx.com/bvdocs/ipcenter/data_sheet/picoblaze_productbrief.pdf) > the performance is 102 MIPS -> 204MHz. > Anybody has an idea how to increase the maximum frequency on our > Picoblaze test implementation? Is there any reference implementation for > the V4 FX12 available? > > Many thanks, > Alexander > > > > > >Article: 103395
No, please don't be shy. Anyone can make any sort of stupid error and this is a very likely one. Right now I don't have access to everything in this process. I designed the board, someone else wrote the software and a third party (group actually) generated the bit stream. It is entirely possible that we have multiple or no swaps of the bit order in the data between the design and the FPGA. But if that were the case, I believe we would see an error flagged by the INIT_B pin. Greg Neff wrote: > On 31 May 2006 05:39:42 -0700, "rickman" <spamgoeshere4@yahoo.com> > wrote: > > >I'm having trouble configuring a Spartan 3 in parallel slave mode. The > >mode pins are set with M0 tied to GND and M1,M2 left pulled up > >internally to 2.5 volts. I verified these voltages with a meter. > > > >I am driving PROG_B low for a few microsecs then high. The DONE and > >INIT_B signals go low and INIT_B goes high again. I set RDWR_B low and > >start clocking data in by setting CS_B low and using the WR_N signal > >from the DSP to clock CCLK on the trailing edge. I have looked at all > >of these signals with the scope and they look clean and have good > >timing. But no matter how much data we clock into the Spartan 3, we > >never see either INIT_B go low or DONE go high. DONE has a 10 kohm > >pullup resistor to 2.5 volts and a buffer converts this signal to 3.3 > >volts for the DSP. > > > >I do see something odd on the BUSY pin. It goes high for some 800 ns. > >The data sheet says I don't even have to monitor this pin if I keep the > >CCLK rate below 50 MHz. We are clocking data into the part at less > >than 10 MHz. > > > >Any idea what could be wrong? > > We use this mode and it works fine. > > At the risk of asking a stupid question (please don't take it the > wrong way) did you remember that the confriguration data port signal > names use IBM nomenclature? In other words, D0 is the most signficant > bit... > > ================================ > > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.comArticle: 103396
m_oylulan@hotmail.com wrote: > Hello, > > I am trying to program an RC-100 demo board, which contains a > Spartan-II chip. The board is supposed to send three logic outputs to > external devices through I/O pins provided on an expansion header. I am > pretty sure I've coded the program correctly (only to the extent that > it works as intended in simulation), but when I probe the I/O pins with > a scope all I'm getting is what I assume is mains pick-up (50 Hz > ~5Vpk-pk). > > My probes have been calibrated; the probe and scope have adequate > bandwidth (greater than 5x the signal bandwidth), and I get the same > result whether I use the 'Auto-scale' function or manually set the > 'Volts' and 'Time' division scales to the capture the expected > waveforms. In the event that the source of the problem isn't my code, > does anyone have any suggestions as to what I might be doing wrong? > > Thanks, > mees Thanks for all the advice above. Gabor was right about the grounding issue, although while now I am not picking up the mains singal, I'm still not seeing the signals I need (scope doesn't pick up anything but a noisy signal). I've tried Leon's suggestion of just writing a simple program sending out a square wave and still no luck (although the code is written in Handel-C not VHDL... I don't know the VHDL language, and thought Handel-C would be easier to get a quicker design since C was more familiar). Finally, in answer to Ben's question, yes, I had assigned the data to specific pins and the scope doesn't see anything (even with proper grounding). MeesArticle: 103397
is anyone knew the new version of HWICAP "opb_hwicap_v1_00_c" for virtex-4?? thanks in advance!!!!Article: 103398
zhangxun0501@gmail.com schrieb: > is anyone knew the new version of HWICAP "opb_hwicap_v1_00_c" for > virtex-4?? > > thanks in advance!!!! next servicepack maybe AnttiArticle: 103399
For VHDL: If you need multiple-clock "subroutines", the separate "black box" approach previously mentioned is the way to go. This may be a separate process in the same entity/arch, or may be a separate entity/arch alltogether. If you need to collect common single-clock-cycle behaviors, declaring functions and procedures to encapsulate that functionality works very well. Synthesis tools do not like subprograms with wait statements or clock edge clauses, thus the single-clock-cycle requirement. Andy Jones Ron wrote: > CMOS wrote: > > is there a standard way to combine state machines > > There have been a couple of occasions when I have used nested case > statements, but it gets messy real fast. > > Ron
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