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So I should copy and paste the templates from the doc into my verilog file? -Nevo "Ben Jackson" <ben@ben.com> wrote in message news:slrneckt00.14lv.ben@saturn.home.ben.com... > On 2006-07-28, Nevo <nevo_n@hotmail.com> wrote: >> >> How do I instantiate library objects that are "inferred rather than >> instantiated" in my project using HDL? > > You use an HDL template that the synthesizer recognizes. If you Google > xst.pdf you will find the templates you need.Article: 105726
When you say it doesn't work, what exactly do you mean? Have you tried simulating it? /MikhailArticle: 105727
Nevo wrote: > So I should copy and paste the templates from the doc into my verilog file? Use "Edit->Language Templates..." in ISE and then right mouse click on the template you want to use and then clicking on "Use in file", which copies it for you. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 105728
Brian McFarland wrote:
> Nevo wrote:
> > Nevo wrote:
> > > As a complete newbie to Verilog and FPGA's, this statement in Xilinx's
> > > documentation has me confused.
> > >
> > > How do I instantiate library objects that are "inferred rather than
> > > instantiated" in my project using HDL? I can add an instance with a
> > > schematic but I don't know what this inference means to include this in
> > > my Verilog files.
> > >
> > > Thanks!
> >
> > Let me try this again in English... :)
> >
> > How do I include library parts that are "inferred rather than
> > instantiated" in a project when I'm creating the project in Verilog?
> > For instance, if I want a D4_16E (a 4-bit one-of-sixteen decoder) in my
> > project, how would I do that?
>
> Do you have a good verilog language reference in print form? If not,
> you should probably invest in one, as the majority of the online ones
> are incomplete. I've used this one:
> http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Verilog/Verilog.htm a
> couple times.
>
> I think this page:
> http://www.doulos.com/knowhow/verilog_designers_guide/a_design_hierarchy/
> will answer your question, but doesn't cover the topic in much depth.
>
> Also, don't post verilog questions in comp.arch.fpga unless the are
> directly related to synthesis on an FPGA. While most of the people
> here know verilog and/or VHDL, you should still go to comp.lang.verilog
> if it's nothing but a simple language question. Some people get very
> hostile if you post in the wrong group. Most just ignore you.
This particular question directly relates to synthesis - so I think it
made it to the proper group.
As for the question itself, you need to look at the blocks in the XST
documentation, and code a structure that looks like it. Remember, VHDL
& Verilog are modelling languages.
You really need to know the characteristics of the hardware block you
are targeting in order to code that will infer it. For example, most
modern FPGA's have synchronous block RAM's, so you must infer
registration on the read data, or you will end up with a bunch of FF's.
Some BRAM's require registered addresses, etc.
For example, the multiplier unit in a Spartan 3e has either two 9-bit
inputs and a 18-bit output, or two 18-bit inputs, and a 36-bit output.
You can munge around a bit with the data widths, but this is
essentially the structures. They have a single clock with no reset or
clock enable.
In VHDL, the code to infer this would be:
Mult: process( Clock )
begin
if( rising_edge(Clock) )then
Mult_Result <= Mult_In_A * Mult_In_B;
end if;
end process;
Note the lack of an asynchronous reset, or clock enable. If you add
either of these elements, you will end up with extra hardware.
About the only thing I haven't found a good way to model purely in HDL
are large ROM's, but it is usually simpler to just use a MIF file with
a core gen / megawizard created IP core.
-Seth
Article: 105729On 2006-07-30, Nevo <nevo_n@hotmail.com> wrote: > So I should copy and paste the templates from the doc into my verilog file? You should observe the structures they are creating and see how they apply to your problem, although you can use them verbatim if you want. The synthesizer doesn't require the same literal text, it's just going to look for patterns (eg an asynchronous, two-port RAM) and figure out how to adapt it to the FPGA's hardware. The XST doc will tell you what sorts of RAM you can get with various combinations of ports, clocking, synchronous vs asynchronous access, etc. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 105730
Hi Mikhail, OK. I have generated the programming file and downloaded to the FPGA. I feed a pure sine wave into an ADC on board, which connect to the input of the filters ( FIR and MAC). The output of the filters are connected to two DAC on board seperately so we can compare the output waveform at the same time. Therefore the output of the filters should be a sine wave too if the it is within the passband frequency range. But the signal coming out from MAC is not a continuouse function. It has some sort of sine function feature, but at certain point in time, it looks like the sign of the signal is changed. The output of the FIR filter is completely fine. That's where it puzzles me. The two filters are running in the exactly the same environment. It is not a clipping problem. I have tried to reduced the input signal amplitude and that didn't solve the problem. I haven't really try to simulate it yet. The whole project has too many inputs. It is not really an easy job to simulate the entire module. Sophi MM wrote: > When you say it doesn't work, what exactly do you mean? Have you tried > simulating it? > > /MikhailArticle: 105731
Coding style like this? wire mask_wr_in = (adr[2:1] == MASK) & wr; wire clear_wr_in = (adr[2:1] == CLEAR) & wr; always @(posedge clk or negedge rst_n) if(~rst_n) begin mask_wr <= #1 1'b0; clear_wr<= #1 1'b0; end else begin mask_wr <= #1 mask_wr_in; clear_wr <= #1 clear_wr_in; end At Fri, 28 Jul 2006 16:34:46 -0700£¬rickman wrote£º > RobJ wrote: >> "rickman" <spamgoeshere4@yahoo.com> wrote in message >> news:1154099086.215982.7080@m79g2000cwm.googlegroups.com... >> > While reviewing the code that the FPGA group has produced, I saw >> > something that looks bad. It is not likely to affect the >> > functionality, but it is not good coding style and may use extra >> > resources. >> > >> > They are using Verilog which is not my first HDL language and I am not >> > as familiar with it as I am VHDL. But because the case statement is >> > not fully specified the code below appears to me to produce more >> > complex logic than needed. >> > >> > always @ (negedge rst_n or posedge clk) begin >> > if (!rst_n)begin >> > mask_wr <= 1'b0; >> > clear_wr <= 1'b0; >> > end >> > else begin >> > if (wr == 1'b1)begin >> > case (adr [2:1]) >> > MASK: mask_wr <= 1'b1; >> > CLEAR: clear_wr <= 1'b1; >> > endcase >> > end >> > else begin >> > mask_wr <= 1'b0; >> > clear_wr <= 1'b0; >> > end >> > end >> > end >> > >> > The real code is controlling 20 or so signals and is very large so this >> > is very simplified. At first I didn't notice the enclosing "always" >> > statement and thought it would produce a latch. Now I realize that it >> > will make enabled registers when what is really desired is just >> > decoders followed by registers. I guess in the grand scheme of things >> > this is not a big issue. But wouldn't it make a more streamlined >> > result to code the logic separate from the register? Then the logic >> > would just be decodes of the address bus and the control signal and the >> > register would not have separate enables. >> > >> >> Rick - >> >> This looks fine to me. It's easy to read and will function correctly, plus >> the case statement and use of parameters make it easy to modify. Given what >> I've heard of your relationship with the FPGA group, I would not flag this >> if I were you. It would be nitpicking. > > I never said I was going to "flag" it. I was just asking for some help > understanding how Verilog worked. If it were VHDL I would know for > certain how the synthesizer would handle it. But I am pretty confident > that this will be less efficient than a properly constructed > description. > > That is how I code differently from a lot of people. Many designers > "program" in the HDL. I design my hardware in block diagrams and use > the language to describe my hardware. The above code certainly > functions correctly, but it would be just as clear, if not more so to > separate the logic and the register. A register description is very, > very simple and small. These can be put after the logic or they can be > lumped together in a register bunch at the end of the module. > > The above program coded as logic would have a separate assignment for > each signal. These assignments would not have any unspecified > conditions and so would implement very efficiently and of course no > latches. Expand the above code to 12 address lines and 25 signals and > you will see how inefficient this could get.Article: 105732
Hi Sophi, > OK. I have generated the programming file and downloaded to the FPGA. What is your input sampling rate? Have you put proper timing constraints? Have they been met? > I feed a pure sine wave into an ADC on board, which connect to the input > of the filters ( FIR and MAC). The output of the filters are connected > to two DAC on board seperately so we can compare the output waveform at > the same time. Have you tried swapping the channels, i.e. connecting the MAC filter to the DAC that was proved working with another filter? > Therefore the output of the filters should be a sine wave too if the it > is within the passband frequency range. But the signal coming out from > MAC is not a continuouse function. It has some sort of sine function > feature, but at certain point in time, it looks like the sign of the > signal is changed. This is where simulation would be useful... > I haven't really try to > simulate it yet. The whole project has too many inputs. It is not > really an easy job to simulate the entire module. You don't need to simulate the whole thing. Just take the filter, make a simple test bench that would apply necessary clock(s) and a test tone. Good simulators such as Active HDL can show buses as waveform, so you will immediately see if the thing works. In fact, I believe all you really need to see is the output ready signal being generated at the proper decimated rate... /MikhailArticle: 105733
Yep, that is pretty much what I would have written. I think this would be the simplest and clearest description of the circuit that is desired. But after pushing it around a bit, I did come up with an always statement (shown later in this thread) that was about the same amount of code and could be said to be pretty much as clear as your code. At that point it just becomes a matter of preference. Actually, I just looked a bit harder at your code and I don't understand the notation mask_wr <= #1 mask_wr_in; Without looking in one of my Verilog books, what is the "#1" for? luiguo wrote: > Coding style like this? > > wire mask_wr_in = (adr[2:1] == MASK) & wr; > wire clear_wr_in = (adr[2:1] == CLEAR) & wr; > > always @(posedge clk or negedge rst_n) > if(~rst_n) begin > mask_wr <= #1 1'b0; > clear_wr<= #1 1'b0; > end > else begin > mask_wr <= #1 mask_wr_in; > clear_wr <= #1 clear_wr_in; > end > > At Fri, 28 Jul 2006 16:34:46 -0700,rickman wrote: > > > RobJ wrote: > >> "rickman" <spamgoeshere4@yahoo.com> wrote in message > >> news:1154099086.215982.7080@m79g2000cwm.googlegroups.com... > >> > While reviewing the code that the FPGA group has produced, I saw > >> > something that looks bad. It is not likely to affect the > >> > functionality, but it is not good coding style and may use extra > >> > resources. > >> > > >> > They are using Verilog which is not my first HDL language and I am not > >> > as familiar with it as I am VHDL. But because the case statement is > >> > not fully specified the code below appears to me to produce more > >> > complex logic than needed. > >> > > >> > always @ (negedge rst_n or posedge clk) begin > >> > if (!rst_n)begin > >> > mask_wr <= 1'b0; > >> > clear_wr <= 1'b0; > >> > end > >> > else begin > >> > if (wr == 1'b1)begin > >> > case (adr [2:1]) > >> > MASK: mask_wr <= 1'b1; > >> > CLEAR: clear_wr <= 1'b1; > >> > endcase > >> > end > >> > else begin > >> > mask_wr <= 1'b0; > >> > clear_wr <= 1'b0; > >> > end > >> > end > >> > endArticle: 105734
Here is my function, which does some custom-made multipliers/division.
NCVerilog simulations for RTL so far shows no problem but design compiler
complains of
this warning.
"Warning: myfile.v:276: Variable 'result' may be read before being
assigned; the synthesized result may not match simulations. (ELAB-391)"
How do I fix this problem?
function [17:0] mult_ck34; // Multiplication for ck3, cl4
input [14:0] sum_row;
input [2:0] multpl_sel;
reg [22:0] result;
begin
case (multpl_sel)
3'b001,
3'b110: begin // 32 + 8 + 2 + 1 // X43>>3
result[20:0] = {{ {sum_row[14]}}, {sum_row}, {5'b0}} + // 32
{{3{sum_row[14]}}, {sum_row}, {3'b0}} + // 8
{{5{sum_row[14]}}, {sum_row}, {1'b0}} + // 2
{{6{sum_row[14]}}, {sum_row}}; // 1
result[22:21] = {2{result[20]}};
end
...
...
endcase
end
mult_ck34 = result[21:4];
endfunction
Article: 105735Hi, Look in Virtex-II user guide, "5V Tolerance in Virtex-II Devices", page 209. I think the same will apply to Spartan3 IO Cheers Sudhir yy wrote: > Hi, > is setting the Vcco of Spartan3 banks to +3.3V would allow the FPGA to > work with a 5V signaling environment like 5V PCI? Or there are some > other means to do this? > > Thanks.Article: 105736
I'm just guessing, but it may be complaining about the fact that if multpl_sel takes on any values other 1 or 6 at runtime, result[] will not get set. -- RonArticle: 105737
Hi
This will be storing your bitstream combined with the bootloader only,
the main program will be stored in the linear flash.
Yes, I saw that on friday too. So I have to download the bitstream with the bootloader in linear flash too.Is that right? In Impact I have only access to the lin. flash over a cpld. When I choose the cpld in Impact to write at, will the *.bit file be stored in the lin. flash?
Thanks for helping me cu Olli
Article: 105738Can GDB source level debugger work if the application is downloaded to the external SRAM? I tried but although it showed the source files but once I let it run, the program seems hang up!Article: 105739
Sudhir.Singh@email.com wrote: > Hi, > Look in Virtex-II user guide, "5V Tolerance in Virtex-II Devices", page > 209. I think the same will apply to Spartan3 IO > > Cheers > Sudhir > > > yy wrote: > > Hi, > > is setting the Vcco of Spartan3 banks to +3.3V would allow the FPGA to > > work with a 5V signaling environment like 5V PCI? Or there are some > > other means to do this? > > > > Thanks. Hi, I tried to search for the document that you're referring but i cant find it, do you have the reference no. of the document? I have read some other document: http://www.xilinx.com/products/virtex/techtopic/vtt002.pdf which tells it is needed to have an external resistor for 5V signalling. BTW, what does that document says about 5V signalling? Thanks.Article: 105740
I knew this attribute was for Xilinx only not Actel devices. Thanx ALuPin@web.de wrote: > Hi, > > try the following: > > signal ls_rom_out : std_logic_vector(... downto 0); > > attribute syn_romstyle : string; > attribute syn_romstyle of ls_rom_out : signal is "select_rom"; > > I do not know whether it can be applied with Actel devices ... >=20 > Rgds > Andr=E9Article: 105741
Dear Benjamin I think you should look at the following article: A PCI time digitizer for the new JET time-of-flight neutron spectrometer Sousa J, Batista AJN, Combo A, Pereira R, Cruz N, Carvalho P, Varandas CAF, Conroy S, Ericsson G, Kallne J FUSION ENGINEERING AND DESIGN 71 (1-4): 101-106 JUN 2004 You should find it interesting taking into account what you are trying to do. Regards A. Combo "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> wrote in message news:eacuhn$jh2$1@sunnews.cern.ch... > Ah, these are excellent points - Thanks everyone =) > > The original purpose was to measure the length of a pulse to some hundreds > of picoseconds. 2GS was chosen as a starting point, but ultimately faster > is better... So, perhaps naively I was hoping that the actual phase of > sample versus source clock was unimportant, but now that you mention it I > have to have a rethink.... > > Interesting. > > Cheers guys. > Ben > > > > > > > "John_H" <johnhandwork@mail.com> wrote in message > news:_39yg.6528$Oh1.4695@news01.roc.ny... >> Do you want a 2GS/s sampler of 2GB/s data or do you just want high >> resolution of a lower speed signal? I'm getting a minimum of 9 GS/s in a >> Spartan3E for a 600 MB/s signal (the sample rate isn't set as much as >> detected). Depending on requirements, there are alternatives to >> RocketIO. See also XAPP671 >> >> http://www.xilinx.com/bvdocs/appnotes/xapp671.pdf >> >> >> "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> >> wrote in message news:eaampt$pvr$1@sunnews.cern.ch... >>> Hi everyone, (especially those Xilinx chaps) :-) >>> >>> I've been having an interesting debate with a colleague here, regarding >>> Virtex 4 Rocket IO (and Virtex II for that matter). The challenge is to >>> make a really high speed signal sampler in the fabric of one of these >>> FPGAs by using the Rocket IO in a custom manner. I'm talking some GS/s >>> >>> We figure using a local clock of 100M, should be mutiplied by 20 inside >>> the rocket IO, giving 20 bits per 100M period that can be shuffled to >>> get some indication of the input waveform. i.e. a 2G sampler. >>> >>> Ok, ignoring the hugely important fact that FPGA has to be able to >>> process this, and that the PCB has to be well designed, and that the >>> input signal might have some new frequency and electrical constraints, >>> are there any pitfalls we've missed? btw: the idea comes from an >>> expansion Figure-7 of: >>> http://www.eetkorea.com/ARTICLES/2004JUN/2004JUN22_PLD_RFD_AN05.PDF >>> >>> Are there any potential flaws in these ideas anyone can see? >>> >>> Thanks in advance, >>> Ben >>> >> >> > >Article: 105742
"Ron" <News5@spamex.com> wrote in message
news:wfhzg.9752$DW3.7225@fe06.lga...
> I'm just guessing, but it may be complaining about the fact that if
> multpl_sel takes on any values other 1 or 6 at runtime, result[] will
> not get set.
>
> -- Ron
Thank you Ron, but the case statement has its default, which sets result[]
to 23'd0.
Thus I suspect it's caused by the bit-extension statement. How can I code it
to
avoid this loop and with a neat one-liner statement.
result[22:21] = {2{result[20]}};
Article: 105743
Here is my code. I need that every time inject_tv is called, it will
restart clock clk3_84m_0 for a unknown number of cycles, but with a
random delay. Clk3_84m_0 shall change only until next time the event
is called upon.
How can I achieve that?
Thanks in advance.
module mytest;
event start_clk_0;
always @ (start_clk_0)
begin
clk3_84m_0 <= 1'b0;
#({$random} % (`CLK_HALF_PERIOD)); // To create a random delay.
forever begin
#`CLK_HALF_PERIOD clk3_84m_0 <= 1'b1;
#`CLK_HALF_PERIOD clk3_84m_0 <= 1'b0;
end
end
task inject_tv;
input ...;
begin
...
...
if (condition)
-->start_clk_0;
...
..
end
endtask
initial
begin
delay(10000);
inject_tv(1);
delay(10000);
inject_tv(2);
delay(10000);
inject_tv(3);
end
endmodule;
Article: 105744Hello experts and newsgroup, I'm planning a new embedded design. The first MicroBlaze handles the communication to external Interfaces and receives DATA (approx. 3MB) which have to be stored in some kind of external memory. These DATA must be accessed by a second MicroBlaze for multiple calculations. Does Xilinx provide such a multiple access on external memory ? Which kind of Memory can you suggest ? Thanks a lot, by BENArticle: 105745
Hi, When I use PACE to assign package pins in ISE 7.1, instead of all my pins being displayed as usual, the only pins displayed are: I0 I1 I2 I3 I4 I5 I6 I7 O Which seems like some sort of buffer IO. I'd appreciate if anybody could tell me what is causing this and how can I get PACE to display all the correct IO pins present in my design. Thanks, AlastairArticle: 105746
Hello Freinds.
I am a newcomer to the field of programmable logic devices and I am
currently trying to teach myself VHDL. I hope to learn some VHDL before
the next semester starts.
My sole purpose as of now is not to actually synthesise stuff but just
to simulate the various designs that I may try to create. I am using
the xilinx ISE webpack 8.2 on a windows XP machine.
Below I am trying to implement a design called ones_cnt wherein the
counter just counts the number of ones in a 4 bit array and prints the
result in a binary format.To understand the concept of configuration
declarations I have declared multiple architectures and I am trying to
use the configuration declaration statement to select one the them.
Heres my code. Its a lil big may be but I hope you guys would have a
look.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ones_cnt is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
C : out STD_LOGIC_VECTOR (1 downto 0));
end ones_cnt;
architecture Algorithmic of ones_cnt is
begin
process(A)
variable NUM: INTEGER range 0 to 3;
begin
NUM := 0;
for I in 0 to 2 loop
if A(I) = '1' then
NUM := NUM + 1;
end if;
end loop;
case NUM is
when 0 => C <= "00";
when 1 => C <= "01";
when 2 => C <= "10";
when 3 => C <= "11";
end case;
end process;
end Algorithmic;
use work.all; ----- this is the line where the error is flaged!! see
below for details.
architecture STRUCTURAL of ones_cnt is
component MAJ3C
port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
end component;
component OPAR3C
port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
end component;
for all: MAJ3C use entity MAJ3(AND_OR);
for all: OPAR3C use entity OPAR3(AND_OR);
begin
COMPONENT_1: MAJ3C
port map (A,C(1));
COMPONENT_2: OPAR3C
port map (A,C(0));
end STRUCTURAL;
entity AND2 is
port (I1,I2: in BIT; O: out BIT);
end AND2;
architecture BEHAVIORAL of AND2 is
begin
O <= I1 and I2;
end BEHAVIORAL;
entity OR3 is
port (I1,I2,I3: in BIT; O: out BIT);
end OR3;
architecture BEHAVIORAL of OR3 is
begin
O <= I1 or I2 or I3;
end BEHAVIORAL;
use work.all;
entity MAJ3 is
port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
end MAJ3;
architecture AND_OR of MAJ3 is
component AND2C
port (I1,I2: in BIT; O: out BIT);
end component;
component OR3C
port (I1,I2,I3: in BIT; O: out BIT);
end component;
for all:AND2C use entity AND2(BEHAVIOR);
for all:OR3C use entity OR3(BEHAVIOR);
signal A1,A2,A3: BIT;
begin
G1: AND2C
port map (X(0),X(1),A1);
G2: AND2C
port map (X(0),X(2),A2);
G3: AND2C
port map (X(1),X(2),A3);
G4: OR3C
port map (A1,A2,A3,Z);
end AND_OR;
entity AND3 is
port(I1,I2,I3: in BIT;
O: out BIT);
end AND3;
architecture BEHAVIORAL of AND3 is
begin
O <= I1 and I2 and I3;
end BEHAVIORAL;
entity OR4 is
port(I1,I2,I3,I4: in BIT;
Z: out BIT);
end OR4;
architecture BEHAVIORAL of OR4 is
begin
Z <= X1 or X2 or X3 or X4;
end BEHAVIORAL;
use work.all
entity OPAR3 is
port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
end OPAR3;
architecture AND_OR of OPAR3 is
component AND3C
port (I1,I2,I3: in BIT; O: out BIT);
end component;
component OR4C
port (I1,I2,I3,I4: in BIT; O: out BIT);
end component;
for all:AND3C use entity AND3(BEHAVIORAL);
for all:OR4C use entity OR4(BEHAVIORAL);
signal A1,A2,A3,A4: BIT;
begin
G1: AND3C
port map (X(2),not X(1),not X(0),A1);
G2: AND3C
port map (not X(2),not X(1),X(0),A2);
G3: AND3C
port map (X(2),X(1),X(0),A3);
G4: AND3C
port map (not X(2),X(1),not X(0),A4);
G5: OR4C
port map (A1,A2,A3,A4,Z);
end AND_OR;
architecture MACRO of ones_cnt is
begin
C(1) <= MAJ3(A);
C(2) <= OPAR(A);
end MACRO;
configuration Trial of ones_cnt is
for STRUCTURAL
end for;
end Trial;
Heres the log report generated by the compiler:
Started : "Check Syntax".
Running vhpcomp
Compiling vhdl file "E:/Xlinx_ISE/workbench/ones_cnt.vhd" in Library
isim_temp.
Entity <ones_cnt> compiled.
Entity <ones_cnt> (Architecture <algorithmic>) compiled.
ERROR:HDLParsers:3014 - "E:/Xlinx_ISE/workbench/ones_cnt.vhd" Line 55.
Library unit work is not available in library isim_temp.
Parsing "AND2_stx.prj": 0.38
Process "Check Syntax" failed
I do not know where am I going here as my VHDL code seems to be ok but
may be I am missing some tool-specific information here like having
certain libraries declared or something like that. I am completely new
to this field and I would sincerely appreciate if someone guides me
through the very difficult phase of getting started which I suppose you
guys might have gone through too in your yesteryears. :)
Looking forward to hearing from you,
Best Regards,
Aijaz.
Article: 105747I have recieved some Verilog code with a Xilinx coregen module called BLKMEMDP_V6_1 and ASYNC_FIFO_V5_1. I presume these are old cores as I cant seem to find them in core generator. Which cores should I use as an equivalent. Cheers JonArticle: 105748
Hi, The information might not be useful but this may give you clue what’s going wrong...!! I experienced a problem with Flash Programmer present under Xilinx EDK. When I tried to program SREC through it, the Flash Programmer programs the FLASH on ML403 with SREC, but without parsing..!!!. If I compare the HEX view of my SREC file and the Flash Memory, they are same (something starting like S31…….) This is wrong..!! The flash programmer should parse the SREC file and program the instructions into the FLASH memory. The workaround is that you should create a BINARY image of your ELF and program it into FLASH using EDK Flash Programmer. You may need to explore GCC options if the sections of your ELF are scattered. In order to boot your software from FLASH, you need to modify your bootloader application, to make jump from BRAM to FLASH memory. - MateenArticle: 105749
New TechiTip added to our website for a 5p (GBP) or 10c (US) FPGA based charge pump power supply. You will find it here http://www.enterpoint.co.uk/techitips/Previous_TechiTips/5p_charge_pump.html. It's good for a bus switch power supply and for using N-Channel FETs in providing an above rail gate voltage application. We are using this circuit in the new board Tarfessock1 so you will all get to see the end results. It has a number of applications beyond this Techitip and we may do some follow ups if there is enough interest. John Adair Enterpoint Ltd. - Some To Be Home of Tarfessock1. The Cardbus Spartan-3E Development Board. http://www.enterpoint.co.uk
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