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Thanks Alvaro... very very useful. https://bis.web.cern.ch/bis/papers/pcijettof.pdf for those who are interested. Ben "Alvaro Combo" <alvaro@lei.fis.uc.pt> wrote in message news:eakirt$glj$1@koala.mat.uc.pt... > Dear Benjamin > > I think you should look at the following article: > > A PCI time digitizer for the new JET time-of-flight neutron spectrometer > > Sousa J, Batista AJN, Combo A, Pereira R, Cruz N, Carvalho P, Varandas > CAF, Conroy S, Ericsson G, Kallne J > > FUSION ENGINEERING AND DESIGN 71 (1-4): 101-106 JUN 2004 > > You should find it interesting taking into account what you are trying to > do. > > Regards > > A. Combo > > > "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> > wrote in message news:eacuhn$jh2$1@sunnews.cern.ch... >> Ah, these are excellent points - Thanks everyone =) >> >> The original purpose was to measure the length of a pulse to some >> hundreds of picoseconds. 2GS was chosen as a starting point, but >> ultimately faster is better... So, perhaps naively I was hoping that the >> actual phase of sample versus source clock was unimportant, but now that >> you mention it I have to have a rethink.... >> >> Interesting. >> >> Cheers guys. >> Ben >> >> >> >> >> >> >> "John_H" <johnhandwork@mail.com> wrote in message >> news:_39yg.6528$Oh1.4695@news01.roc.ny... >>> Do you want a 2GS/s sampler of 2GB/s data or do you just want high >>> resolution of a lower speed signal? I'm getting a minimum of 9 GS/s in >>> a Spartan3E for a 600 MB/s signal (the sample rate isn't set as much as >>> detected). Depending on requirements, there are alternatives to >>> RocketIO. See also XAPP671 >>> >>> http://www.xilinx.com/bvdocs/appnotes/xapp671.pdf >>> >>> >>> "Benjamin Todd" >>> <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> wrote in >>> message news:eaampt$pvr$1@sunnews.cern.ch... >>>> Hi everyone, (especially those Xilinx chaps) :-) >>>> >>>> I've been having an interesting debate with a colleague here, regarding >>>> Virtex 4 Rocket IO (and Virtex II for that matter). The challenge is >>>> to make a really high speed signal sampler in the fabric of one of >>>> these FPGAs by using the Rocket IO in a custom manner. I'm talking some >>>> GS/s >>>> >>>> We figure using a local clock of 100M, should be mutiplied by 20 inside >>>> the rocket IO, giving 20 bits per 100M period that can be shuffled to >>>> get some indication of the input waveform. i.e. a 2G sampler. >>>> >>>> Ok, ignoring the hugely important fact that FPGA has to be able to >>>> process this, and that the PCB has to be well designed, and that the >>>> input signal might have some new frequency and electrical constraints, >>>> are there any pitfalls we've missed? btw: the idea comes from an >>>> expansion Figure-7 of: >>>> http://www.eetkorea.com/ARTICLES/2004JUN/2004JUN22_PLD_RFD_AN05.PDF >>>> >>>> Are there any potential flaws in these ideas anyone can see? >>>> >>>> Thanks in advance, >>>> Ben >>>> >>> >>> >> >> > >Article: 105776
Mike Treseler wrote: > eric.amundsen@gmail.com wrote: > > > We would really like to use a DDR2 SRAM (for reasons I don't > > want to go into), but Mega-core doesn't support it. > > Anything wrong with this one? > http://www.altera.com/literature/ug/ug_ddr_sdram.pdf SRAM != SDRAM :-) TommyArticle: 105777
jvdh <johannes.vanderhorst@gmail.com> wrote: > I like the (off the shelf) simplicity of your suggeston :) > The way I see it, the main options would be changing the medium (esp to > fibre), or slowing the comms down - the later would probably be > preferable from a cost point of view... > But I'm first trying to confirm that it definitely is the transmission > delay that's messing me around. Isn't there an option to set the JTAG CLK speed in impact? Another option beside the USB Extender is to convert the levels to a RS422/485 signal and use a twisted pair cable. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 105778
Ben_M wrote: > Hello experts and newsgroup, > > I'm planning a new embedded design. > > The first MicroBlaze handles the communication to external Interfaces > and receives DATA (approx. 3MB) which have to be stored in some kind of > external memory. > > These DATA must be accessed by a second MicroBlaze for multiple > calculations. > > Does Xilinx provide such a multiple access on external memory ? > Which kind of Memory can you suggest ? > > > Thanks a lot, > by > BEN > Try mch_opb_[sdram|ddr] controllers that come with EDK. You should be able to connect two MB's directly to memory and an OPB channel for peripheral accesses to memory. /SArticle: 105779
Hi all, Did anyone use USB2.0 port of Spartan3E Starter Kit for his own purpose? If course this includes unsoldering of some pins, wirnig them to FPGA IOs and reprogramming the Cypress FX2. There is also JTAG port on-board to program FPGA and PROM. Thanks, GuruArticle: 105780
Mike Treseler wrote: > eric.amundsen@gmail.com wrote: > > > We would really like to use a DDR2 SRAM (for reasons I don't > > want to go into), but Mega-core doesn't support it. > > Anything wrong with this one? > http://www.altera.com/literature/ug/ug_ddr_sdram.pdf > > > We're not opposed > > to building our own interface, but we're trying to understand the > > possible reasons Altera doesn't support it. We've been told that > > basically there's just no demand, so that's why it's not there, but we > > fear that's not the whole story. > > If time is an issue, buy standard interfaces. > > -- Mike Treseler The Stratix II supports DDR2 as an interface to the NIOS2 processor, as indicated in the document pointed to by the link. You didn't indicate wether or not you were intending to use the NIOS2 or if you simply wanted to implement a DDR2 controller in the Stratix for connection to another processor. I would recommend tracking down an Altera FAE or seeing if there is a direct Altera application engineer in your area that can pay you a visit. As far as cores go, another place to look is at "open cores" (.org I think it is). I believe they provide cores that you can download and use free of charge. I am not sure what their URL is though.Article: 105781
Siva Velusamy wrote: > Ben_M wrote: > > Hello experts and newsgroup, > > > > I'm planning a new embedded design. > > > > The first MicroBlaze handles the communication to external Interfaces > > and receives DATA (approx. 3MB) which have to be stored in some kind of > > external memory. > > > > These DATA must be accessed by a second MicroBlaze for multiple > > calculations. > > > > Does Xilinx provide such a multiple access on external memory ? > > Which kind of Memory can you suggest ? > > > > > > Thanks a lot, > > by > > BEN > > > > Try mch_opb_[sdram|ddr] controllers that come with EDK. You should be > able to connect two MB's directly to memory and an OPB channel for > peripheral accesses to memory. > > /S Hello Siva, Do you mean connect all two MB and sdram controller to one OPB bus? Is it possible without arbitrator or you mean something else. I am working on a similar project and thinking of making an arbitrator myself. Thanks for your information. WayneArticle: 105782
jvdh wrote: > This might be slightly OT for an FPGA group, but maybe someone has run > into a similar problem before: > > I'd like to connect my FPGA, via JTAG, to my PC, 100m away. Due to a > hazardous environment, putting the PC any closer isn't feasible Can you clarify hazardous - is this electrically noisy, or soemthing else. If it is electrically noisy, RS485 may not be enough. > > I'm using a Xilinx parallel cable III, which I extended with RS485 > drivers to get to required distance, before converting back to TTL to > drive the original cable. > > Currently, Impact (correctly) finds the correct number of devices on > the JTAG chain on two different boards, but identification fails. > > A bit of exploration with a scope shows data flowing pretty much as > expected, with a clean wave arriving at the board. Another, rather > worrying, aspect is that the transmission delay through the systems is > about 800ns - rather a lot on a 200kHz communication system. > > Does someone perhaps know whether impact will get upset with the delay? > Is there away around it? (As far as I can see, my cable doesn't > respond to the speed setting in Impact) > > Any suggestions would be appreciated. > > johannes > > http://www.ee.sun.ac.za/~jvdh You could create a deliberate bench-delay, ( schmitt buffers and RC elements ) and see if that is ok in your lab. It should also let you test various download software's delay tolerances. - that helps isolate delay effects from other noise effects. You may need an isolated link system, RS485 has finite common mode limits - but isolation will add to your delay budget... I think analog devices have some high speed isolators ? -jgArticle: 105783
You might have more luck if you *requested* information instead of "requiring" it.Article: 105784
Ron wrote: > You might have more luck if you *requested* information instead of > "requiring" it.Article: 105785
aijazbaig1@gmail.com wrote: > Hello Freinds. > I am a newcomer to the field of programmable logic devices and I am > currently trying to teach myself VHDL. I hope to learn some VHDL before > the next semester starts. > My sole purpose as of now is not to actually synthesise stuff but just > to simulate the various designs that I may try to create. I am using > the xilinx ISE webpack 8.2 on a windows XP machine. > Below I am trying to implement a design called ones_cnt wherein the > counter just counts the number of ones in a 4 bit array and prints the > result in a binary format.To understand the concept of configuration > declarations I have declared multiple architectures and I am trying to > use the configuration declaration statement to select one the them. > > Heres my code. Its a lil big may be but I hope you guys would have a > look. > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > ---- Uncomment the following library declaration if instantiating > ---- any Xilinx primitives in this code. > --library UNISIM; > --use UNISIM.VComponents.all; > > entity ones_cnt is > Port ( A : in STD_LOGIC_VECTOR (2 downto 0); > C : out STD_LOGIC_VECTOR (1 downto 0)); > end ones_cnt; > > architecture Algorithmic of ones_cnt is > begin > process(A) > variable NUM: INTEGER range 0 to 3; > begin > NUM := 0; > for I in 0 to 2 loop > if A(I) = '1' then > NUM := NUM + 1; > end if; > end loop; > case NUM is > when 0 => C <= "00"; > when 1 => C <= "01"; > when 2 => C <= "10"; > when 3 => C <= "11"; > end case; > end process; > end Algorithmic; > > use work.all; ----- this is the line where the error is flaged!! see > below for details. > architecture STRUCTURAL of ones_cnt is > component MAJ3C > port (X: in BIT_VECTOR(2 downto 0); Z: out BIT); > end component; > component OPAR3C > port (X: in BIT_VECTOR(2 downto 0); Z: out BIT); > end component; > for all: MAJ3C use entity MAJ3(AND_OR); > for all: OPAR3C use entity OPAR3(AND_OR); > begin > COMPONENT_1: MAJ3C > port map (A,C(1)); > COMPONENT_2: OPAR3C > port map (A,C(0)); > end STRUCTURAL; > > entity AND2 is > port (I1,I2: in BIT; O: out BIT); > end AND2; > architecture BEHAVIORAL of AND2 is > begin > O <= I1 and I2; > end BEHAVIORAL; > > entity OR3 is > port (I1,I2,I3: in BIT; O: out BIT); > end OR3; > architecture BEHAVIORAL of OR3 is > begin > O <= I1 or I2 or I3; > end BEHAVIORAL; > > use work.all; > entity MAJ3 is > port (X: in BIT_VECTOR(2 downto 0); Z: out BIT); > end MAJ3; > architecture AND_OR of MAJ3 is > component AND2C > port (I1,I2: in BIT; O: out BIT); > end component; > component OR3C > port (I1,I2,I3: in BIT; O: out BIT); > end component; > for all:AND2C use entity AND2(BEHAVIOR); > for all:OR3C use entity OR3(BEHAVIOR); > signal A1,A2,A3: BIT; > begin > G1: AND2C > port map (X(0),X(1),A1); > G2: AND2C > port map (X(0),X(2),A2); > G3: AND2C > port map (X(1),X(2),A3); > G4: OR3C > port map (A1,A2,A3,Z); > end AND_OR; > > entity AND3 is > port(I1,I2,I3: in BIT; > O: out BIT); > end AND3; > architecture BEHAVIORAL of AND3 is > begin > O <= I1 and I2 and I3; > end BEHAVIORAL; > > entity OR4 is > port(I1,I2,I3,I4: in BIT; > Z: out BIT); > end OR4; > architecture BEHAVIORAL of OR4 is > begin > Z <= X1 or X2 or X3 or X4; > end BEHAVIORAL; > > use work.all > entity OPAR3 is > port (X: in BIT_VECTOR(2 downto 0); Z: out BIT); > end OPAR3; > architecture AND_OR of OPAR3 is > component AND3C > port (I1,I2,I3: in BIT; O: out BIT); > end component; > component OR4C > port (I1,I2,I3,I4: in BIT; O: out BIT); > end component; > for all:AND3C use entity AND3(BEHAVIORAL); > for all:OR4C use entity OR4(BEHAVIORAL); > signal A1,A2,A3,A4: BIT; > begin > G1: AND3C > port map (X(2),not X(1),not X(0),A1); > G2: AND3C > port map (not X(2),not X(1),X(0),A2); > G3: AND3C > port map (X(2),X(1),X(0),A3); > G4: AND3C > port map (not X(2),X(1),not X(0),A4); > G5: OR4C > port map (A1,A2,A3,A4,Z); > end AND_OR; > > architecture MACRO of ones_cnt is > begin > C(1) <= MAJ3(A); > C(2) <= OPAR(A); > end MACRO; > > configuration Trial of ones_cnt is > for STRUCTURAL > end for; > end Trial; > > Heres the log report generated by the compiler: > Started : "Check Syntax". > Running vhpcomp > Compiling vhdl file "E:/Xlinx_ISE/workbench/ones_cnt.vhd" in Library > isim_temp. > Entity <ones_cnt> compiled. > Entity <ones_cnt> (Architecture <algorithmic>) compiled. > ERROR:HDLParsers:3014 - "E:/Xlinx_ISE/workbench/ones_cnt.vhd" Line 55. > Library unit work is not available in library isim_temp. > Parsing "AND2_stx.prj": 0.38 > > Process "Check Syntax" failed > > > I do not know where am I going here as my VHDL code seems to be ok but > may be I am missing some tool-specific information here like having > certain libraries declared or something like that. I am completely new > to this field and I would sincerely appreciate if someone guides me > through the very difficult phase of getting started which I suppose you > guys might have gone through too in your yesteryears. :) > > Looking forward to hearing from you, > > Best Regards, > Aijaz. Hi Aijaz, I tried but I can't reproduce the error. Can you zip your project and send it to me? I am nowadays studying VHDL as well and I have some VHDL expert colleagues here. WayneArticle: 105786
quickwayne@gmail.com wrote: >>> >>>These DATA must be accessed by a second MicroBlaze for multiple >>>calculations. >>> >>>Does Xilinx provide such a multiple access on external memory ? >>>Which kind of Memory can you suggest ? >>> >>> >>>Thanks a lot, >>>by >>>BEN >>> >> >>Try mch_opb_[sdram|ddr] controllers that come with EDK. You should be >>able to connect two MB's directly to memory and an OPB channel for >>peripheral accesses to memory. >> >>/S > > > Hello Siva, > > Do you mean connect all two MB and sdram controller to one OPB bus? Is > it possible without arbitrator or you mean something else. I am working > on a similar project and thinking of making an arbitrator myself. > Thanks for your information. > > Wayne > MicroBlaze version 3 and above allow a direct connection from the I & D caches to memory. This channel is called XCL. This provides better performance since the protocol over this channel is optimized for cache accesses (cacheline bursts & target word first). The memory controllers that have this XCL interface are called mch memory controllers - mch_sdram/emc/ddr. So your configuration would like this: MB1 - i-XCL and d-XCL connected to channels 0 & 1 of mch_sdram MB2 - i-XCL and d-XCL connected to channels 2 & 3 of mch_sdram OPB and opb peripherals connected to OPB channel (4) of mch_sdram. The arbitration between the 5 ports (4 XCL, 1 OPB) is done inside the memory controller, so you wouldn't have to write any arbitration logic. In case you want to attach many many more masters to the OPB, even then you wouldn't have to write any arbitration logic, since it is included in the OPB logic itself. /SivaArticle: 105787
Jim Granville <no.spam@designtools.co.nz> wrote: ... > You may need an isolated link system, RS485 has finite common mode > limits - but isolation will add to your delay budget... > I think analog devices have some high speed isolators ? I use the ADUM1401 for that task, in connection with SPI transfers. Jtag shouldn't be too different. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 105788
Noway2 wrote: > Mike Treseler wrote: > > eric.amundsen@gmail.com wrote: > > > > > We would really like to use a DDR2 SRAM (for reasons I don't > > > want to go into), but Mega-core doesn't support it. > > > > Anything wrong with this one? > > http://www.altera.com/literature/ug/ug_ddr_sdram.pdf > > > > > We're not opposed > > > to building our own interface, but we're trying to understand the > > > possible reasons Altera doesn't support it. We've been told that > > > basically there's just no demand, so that's why it's not there, but we > > > fear that's not the whole story. > > > > If time is an issue, buy standard interfaces. > > > > -- Mike Treseler > > The Stratix II supports DDR2 as an interface to the NIOS2 processor, as > indicated in the document pointed to by the link. You didn't indicate > wether or not you were intending to use the NIOS2 or if you simply > wanted to implement a DDR2 controller in the Stratix for connection to > another processor. I would recommend tracking down an Altera FAE or > seeing if there is a direct Altera application engineer in your area > that can pay you a visit. > > As far as cores go, another place to look is at "open cores" (.org I > think it is). I believe they provide cores that you can download and > use free of charge. I am not sure what their URL is though. First, this is not being used with a NIOS2 processor, or any other type of processor. Basically need memory hanging off of a data path for data dependent storage/retrieval. Second, we've been working with our FAE, but so far have basically been told, with respect to our memory issues, that since DDR2 SRAM is so rarely used we're pretty much on our own. We're trying to get some third party design services on board to help us out here, but those wheels slowly. I will poke around open cores. EricArticle: 105789
Lattice has launched a new blog called "Frontier" at http://www.latticeblogs.typepad.com/ Frontier is a collaborative blog written by senior Lattice engineers. Our initial blog authors are David Rutledge, vice president of product development (and inventor of the original GAL device); Bertrand Leigh, manager of applications engineering; Mike Kendrick, manager of SW product planning; and Gordon Hands, director of strategic marketing. All of our authors are employees of Lattice Semiconductor. We hope you will want to take advantage of this opportunity to hear what our engineers are saying, start an open dialog and share ideas with some of our key innovators at Lattice. Your comments and questions are welcomed and appreciated and can influence Lattice products. Thanks. Bart Borosky, LatticeArticle: 105790
bart <bart.borosky@latticesemi.com> wrote: > Lattice has launched a new blog called "Frontier" at > http://www.latticeblogs.typepad.com/ > Frontier is a collaborative blog written by senior Lattice engineers. > Our initial blog authors are David Rutledge, vice president of product > development (and inventor of the original GAL device); Bertrand Leigh, > manager of applications engineering; Mike Kendrick, manager of SW > product planning; and Gordon Hands, director of strategic marketing. > All of our authors are employees of Lattice Semiconductor. > We hope you will want to take advantage of this opportunity to hear > what our engineers are saying, start an open dialog and share ideas > with some of our key innovators at Lattice. Your comments and questions > are welcomed and appreciated and can influence Lattice products. While for Xilinx parts I can go the the Digikey or Nuhorizont webpage (and even www.schukat.de carries some XC3Sparts) and get online quote and availablity, I don't know of such places for Lattice parts. Talking to distributor as a small number customer is mostly non rewarding, I try to avoid it. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 105791
> While for Xilinx parts I can go the the Digikey or Nuhorizont webpage (and > even www.schukat.de carries some XC3Sparts) and get online quote and > availablity, I don't know of such places for Lattice parts. > Hello Uwe, You might try a specialized distributor such as Mouser for smaller quantities of Lattice parts. It is my understanding that proto quantities are their specialty, so they are setup to have stock on hand of FPGAs and a very low minimum order qty (1pc.?). If you're interested in Mouser, they do stock Lattice FPGAs: http://www.mouser.com/latticesemi/ Hope this helps. Regards, Bart Borosky, LatticeArticle: 105792
I infer a Xilinx BRAM with a VHDL constant array. But when I change a single value in this array, ISE resynthesizes the entire design. There must be a quicker way. Brad Smallridge aivisionArticle: 105793
Hi /Mikhail, I think I will try to simulate the MAC filter on its own asap. I have tried every other possibility that might introduce problems that I can think of, including those ones in your previouse reply. Once again, thank you for your help and I will give you some feed back after the simulation is done. SophiArticle: 105794
heinerlitz@gmx.de wrote: > Hi, > I finally got to run the MIG created DDR2 for VIrtex4 devices > controller. However I have two problems with the controller: > > 1. I am observing the ERROR signal which is created by the dataCompare > module. It goes high every 8th read pulse. Could this be related to the > FIFO16 bug? I don't have the DDR2 source code with me at home, but I'm pretty sure that the FIFO16 use was limited to the write data and the address/command. The write data FIFO has 2 different clocks, but the FIFO read clock is 90 degrees out of phase with FIFO write clock, so I think it is not a problem. I had problems with the address/command FIFO. The FIFO would be empty, but the DDR2 controller thought that the FIFO had data, so it would repeatedly read the same address. Is there a way to fix the fifo in the design? It would be > easy to fix the fifo issue in my own design but as I havent written the > ddr controler i have no glue what the requirements of the fifo16 are > and how the issue should can be fixed in the best way. Inverting the > readclock (as I read somewhere) didnt work and I do not know if the > coregenerated fifos are fast enough and if they can be simply exchanged > (no fall through for example). I created a Block RAM FIFO with CoreGen; it was pretty simple;just look at the MIG verilog or VHDL code. The FIFO16 is instantiated directly and the parameters are specified in the code. Fall through is supported in CoreGen. > > 2. My other problem is of different nature. The simulation environment > which is supplied by xilinx does not work with some RAMs. I had no > problem simulating a 8bit Micron DDR2 chip however the 16bit chip I am > currently using does not work. THe whole testbench verilog files are > corrupted showing false instantiations (wrong names, wrong bit sizes) > has anybody experienced the same problems? I built a DIMM simulation out of 8-bit parts. Why not just use 2 8-bit parts instead of a 16-bit? Even if you're trying to simulate with real PCB delays, 2 parts could work. > > Both problems could be probably solved by disassembing the whole > design, but that takes hours, so If anybody has already a solution for > the above problems I would be very happy. I'm not happy with the whole calibration procedure that DDR2 MIG has. The IDELAY part that looks at the data strobes seems to work OK, but then they write a pattern to memory, read it back and try to figure out how many clocks to wait after the read command before the data is available and can be shifted into the read data FIFO. Sometimes (most of the time) that logic would make the wrong choice and miss some of the read data. I eventually hard coded the delay and it worked fine after that. --- Joe Samson Pixel VelocityArticle: 105795
Hello all, I intend the demultiplex the data coming to the FPGA on dual-edge clock using the DDR Input Buffers. However I could not find an appropriate explanation of instantiating the DDR Input buffer for this purpose. I am using the DCM to generate the CLK0 and CLK180 using the data reference clock that comes with the data at the Input boundary. Any of your comments/suggestions are sincerely appreicated. Kind regards, Venkat.Article: 105796
Hi You can find the document at this link http://direct.xilinx.com/bvdocs/userguides/ug002.pdf Page 209 You need to put an appropriate series resistor to limit the amount the current that flows through the clamp diodes. Hope this helps Cheers Sudhir yy wrote: > Sudhir.Singh@email.com wrote: > > Hi, > > Look in Virtex-II user guide, "5V Tolerance in Virtex-II Devices", page > > 209. I think the same will apply to Spartan3 IO > > > > Cheers > > Sudhir > > > > > > yy wrote: > > > Hi, > > > is setting the Vcco of Spartan3 banks to +3.3V would allow the FPGA to > > > work with a 5V signaling environment like 5V PCI? Or there are some > > > other means to do this? > > > > > > Thanks. > > Hi, > I tried to search for the document that you're referring but i cant > find it, do you have the reference no. of the document? > I have read some other document: > http://www.xilinx.com/products/virtex/techtopic/vtt002.pdf > which tells it is needed to have an external resistor for 5V > signalling. > BTW, what does that document says about 5V signalling? > > Thanks.Article: 105797
Hi I am viewing the RTL schematic generated by the Xilinx ISE (7.1 with SP$)tool for a vhdl statement <= '1' when (a = '1' and b = '0') else '0'; am seeing in the rtl schematics as 'C' as the output of an AND gate with input to the AND gate as 'A' , 'B'. no NOT gate is implemented on the 'B' input ? is it a BUG ? Thanks in advance bijoyArticle: 105798
Joseph Samson wrote:
> heinerlitz@gmx.de wrote:
> > Hi,
> > I finally got to run the MIG created DDR2 for VIrtex4 devices
> > controller. However I have two problems with the controller:
> >
> > 1. I am observing the ERROR signal which is created by the dataCompare
> > module. It goes high every 8th read pulse. Could this be related to the
> > FIFO16 bug?
>
> I don't have the DDR2 source code with me at home, but I'm pretty sure
> that the FIFO16 use was limited to the write data and the
> address/command. The write data FIFO has 2 different clocks, but the
> FIFO read clock is 90 degrees out of phase with FIFO write clock, so I
> think it is not a problem. I had problems with the address/command FIFO.
> The FIFO would be empty, but the DDR2 controller thought that the FIFO
> had data, so it would repeatedly read the same address.
In the xxx_ddr2_controller.vhd file, they register the empty signal of
the fifo. And
it should not be registred. If you remove this register level, it works
fine.
Also, they do use FIFO16 but when they use it with synchronous clock,
they
don't care about the flags, they use a separate counter to know how
many
data are present so there should be no problem.
Beware if you replace the command fifo. I've replaced it by a simple
SRL fifo
(to gain some space and 1 BRAM), and I was bitten ;) The fifo CANNOT
become
empty for a cycle then become not empty again, if the operation before
and after
the empty were both read in the same row, you'll get one more data than
you
asked for ...
Also, the timing parameters generated by the MiG tool are overly
conservative ...
(I think they messed up their formula). Check in simulation, you'll see
it waits quite
too loog (sometime twice too much ;)
Sylvain
Article: 105799Guru schrieb: > Hi all, > > Did anyone use USB2.0 port of Spartan3E Starter Kit for his own > purpose? > If course this includes unsoldering of some pins, wirnig them to FPGA > IOs and reprogramming the Cypress FX2. There is also JTAG port on-board > to program FPGA and PROM. > > Thanks, > > Guru there is no need to change any wiring. just rewrite the FX2 serial EEPROM to force it to load your own firmware and then you can use JTAG pins and user logic connected to BSCAN to implement USB to FPGA link Antti http://antti-brain.com
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