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aijazbaig1@gmail.com wrote: > I am a newcomer to the field of programmable logic devices and I am > currently trying to teach myself VHDL. I hope to learn some VHDL before > the next semester starts. > My sole purpose as of now is not to actually synthesise stuff but just > to simulate the various designs that I may try to create. I am using > the xilinx ISE webpack 8.2 on a windows XP machine. If you want just simulate VHDL, try Active HDL: http://www.aldec.com/products/active%2Dhdl/ It has a much better user interface and debugging capabilities than ISE and they sell an inexpensive student edition. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 105751
JJ schrieb: > If you need to sort a huge array of integer keys I favor the radix > sort, for 64 bit values, use 8 passes with 256 variable length output > buckets whose total size will be same as initial array.. The time will > go towards 16N memory cycles which may use the fastest rate of memory > access, potentially at DDR rates even. > > Its is just like sorting a telephone book where you take the initial > say random name list and put all the names beginning with 'a' into the > 'a' bucket and similar for other letters. In this case you have 256 > letters. On 2nd pass inspect 2nd letter. Every time you have say 16 'a' > words you bag them and put them into the 'a' pile. You want to do > mostly reads and mostly writes as bursts rather than interleaving reads > & writes. Blockrams can be used as your letter bags. Actually that would be bucket sort. The disadvantage of bucket sort is that you need to manage many buckets of varying size. This is either complicated or wastes a lot of memory. With radix sort you start by sorting counterintuitively by the LAST letter of the name (or the least significant byte) to avoid all that hassle. Each pass can be done by counting sort with an internal block ram with 256 entries for counting. In a V4 you can probably even hold 64k entries so you can get along with 4 passes of 16-bits each. See section 9.3 of Cormen, Leiserson and Rives "Introduction to Algorithms". Smaller datasets can be sorted in hardware by systolic priority queues as fast as you can input the data. Kolja Sulimma.Article: 105752
IIRC each and every pin of a virtex4-LX supports the required 750MHz. Kolja Sulimma Vivek Menon schrieb: > Hi John, > I am doubtful if anything can be done on ADC08D1500 as it supports a > Virtex4 LX15 that does not have Rocket I/O capability.Article: 105753
On a sunny day (Mon, 31 Jul 2006 13:03:34 +0100) it happened "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in <1154347406.26713.0@proxy02.news.clara.net>: >New TechiTip added to our website for a 5p (GBP) or 10c (US) FPGA based >charge pump power supply. When I was young we used to call this a 'Villard' circuit... http://en.wikipedia.org/wiki/Voltage_multiplier A 'charge pump' connacts and disconnects the capacitors with swithes. http://en.wikipedia.org/wiki/Charge_pump http://www.maxim-ic.com/appnotes.cfm/appnote_number/725 Nevertheless a nice solution you have there.Article: 105754
"Mr. Ken" <Mr. Ken@asdf> wrote in message
news:44cd91a0$1@news.starhub.net.sg...
> Here is my function, which does some custom-made multipliers/division.
> NCVerilog simulations for RTL so far shows no problem but design compiler
> complains of
> this warning.
>
> "Warning: myfile.v:276: Variable 'result' may be read before being
> assigned; the synthesized result may not match simulations. (ELAB-391)"
>
> How do I fix this problem?
>
>
>
> function [17:0] mult_ck34; // Multiplication for ck3, cl4
> input [14:0] sum_row;
> input [2:0] multpl_sel;
> reg [22:0] result;
> begin
> case (multpl_sel)
> 3'b001,
> 3'b110: begin // 32 + 8 + 2 + 1 // X43>>3
> result[20:0] = {{ {sum_row[14]}}, {sum_row}, {5'b0}} + // 32
> {{3{sum_row[14]}}, {sum_row}, {3'b0}} + // 8
> {{5{sum_row[14]}}, {sum_row}, {1'b0}} + // 2
> {{6{sum_row[14]}}, {sum_row}}; // 1
> result[22:21] = {2{result[20]}};
> end
> ...
> ...
> endcase
> end
>
> mult_ck34 = result[21:4];
>
> endfunction
>
I'd take the bit extension out of the case statement, as follows:
mult_ck34 = {result[20], result[20:4]};
Rob
Article: 105755Hello Frank. Thanks a lot for the advice. I would certainly try using the active HDL. Furthermore, I would appreciate if you look at my code and let me know if there is anything wrong with the semantics and/or the syntax or the design flow or anything. Is it just that I can't ISE to work with it? And is active HDL an all inclusive package? I mean do I need to have separate software packages to generate waveform testbenches and VHDL testbenches? Hoping to hear from you, Best Regards, Aijaz Baig. Frank Buss wrote: > aijazbaig1@gmail.com wrote: > > > I am a newcomer to the field of programmable logic devices and I am > > currently trying to teach myself VHDL. I hope to learn some VHDL before > > the next semester starts. > > My sole purpose as of now is not to actually synthesise stuff but just > > to simulate the various designs that I may try to create. I am using > > the xilinx ISE webpack 8.2 on a windows XP machine. > > If you want just simulate VHDL, try Active HDL: > http://www.aldec.com/products/active%2Dhdl/ > It has a much better user interface and debugging capabilities than ISE and > they sell an inexpensive student edition. > > -- > Frank Buss, fb@frank-buss.de > http://www.frank-buss.de, http://www.it4-systems.deArticle: 105756
I agree the technique is nothing new. Just a cheap way to do it. How cheap does depend on how you cost your FPGA pin. The other good thing is the size is good even compared to a charge pump with integrated caps. The tracking ability to Vccio is also useful and not so easy to do in an integrated charge pump. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message news:eakthv$2se$1@news.datemas.de... > On a sunny day (Mon, 31 Jul 2006 13:03:34 +0100) it happened "John Adair" > <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in > <1154347406.26713.0@proxy02.news.clara.net>: > >>New TechiTip added to our website for a 5p (GBP) or 10c (US) FPGA based >>charge pump power supply. > > When I was young we used to call this a 'Villard' circuit... > http://en.wikipedia.org/wiki/Voltage_multiplier > > A 'charge pump' connacts and disconnects the capacitors with swithes. > http://en.wikipedia.org/wiki/Charge_pump > http://www.maxim-ic.com/appnotes.cfm/appnote_number/725 > > Nevertheless a nice solution you have there.Article: 105757
Block Ram Generator and Fifo Generator, I think. HTH, Jim http://home.comcast.net/~jimwu88/tools/ maxascent wrote: > I have recieved some Verilog code with a Xilinx coregen module called > BLKMEMDP_V6_1 and ASYNC_FIFO_V5_1. I presume these are old cores as I cant > seem to find them in core generator. Which cores should I use as an > equivalent. > > Cheers > > JonArticle: 105758
Austin Lesea schrieb: > Ben, > > The problem with using the MGT receiver as a sampler, is that it wants > to "recover" the embedded clock signal in the data. > > If you can gain access to the input sliced data, after it has been > clocked into the serial to parallel converter, the only question is: > "what was the clock to the serial to parallel shift register?" > > Look at page 34 of > http://direct.xilinx.com/bvdocs/userguides/ug076.pdf > > The receiver depends on recovery of an input clock to then > shift/transfer/unscramble/decode the received data. > > The paths are all there to bypass the 8B10B, etc. but how to you solve > the chicken and egg problem of no clock -- no data? > > Page 68 discusses the receiver clock options, and if the receiver can't > or won't lock to the sampled data based on the clock reference, then I > think the serial recovered clock is just a multiple of the refclk as you > describe. But the receiver "knows" it has no lock, and how does this > affect the rest of the operation? See page 153. The option RXDIGRX forces the deserializer to the local reference clock. Years ago I mentioned the lack of this option in Virtex2-Pro to Peter Alfke and he promised to forward the request to the people in charge. Apparently he was successfull ;-) Kolja SulimmaArticle: 105759
This might be slightly OT for an FPGA group, but maybe someone has run into a similar problem before: I'd like to connect my FPGA, via JTAG, to my PC, 100m away. Due to a hazardous environment, putting the PC any closer isn't feasible I'm using a Xilinx parallel cable III, which I extended with RS485 drivers to get to required distance, before converting back to TTL to drive the original cable. Currently, Impact (correctly) finds the correct number of devices on the JTAG chain on two different boards, but identification fails. A bit of exploration with a scope shows data flowing pretty much as expected, with a clean wave arriving at the board. Another, rather worrying, aspect is that the transmission delay through the systems is about 800ns - rather a lot on a 200kHz communication system. Does someone perhaps know whether impact will get upset with the delay? Is there away around it? (As far as I can see, my cable doesn't respond to the speed setting in Impact) Any suggestions would be appreciated. johannes http://www.ee.sun.ac.za/~jvdhArticle: 105760
Hello, I would like to try the Ethernet Wrapper IP core together with the ml403 board and I have a problem making it operational. I have generated core form generator after that update the constraint file so that all (I think) RXs, TXs and PHY reset nets are connected to the pads. After programing the FPGA I can see that PHY has been reseted and connection has been established but when I send date to the board I have no respond. In the example design which I'm using is loopback module which connects TXs lines with RXs and makes address swapping so I should get what I'm sending but in fact the board does not send anything. Where I'm making mistake or what I haven't done which is necessary? Regards, BartekArticle: 105761
Mr. Ken wrote:
> Here is my code. I need that every time inject_tv is called, it will
> restart clock clk3_84m_0 for a unknown number of cycles, but with a
> random delay. Clk3_84m_0 shall change only until next time the event
> is called upon.
>
> How can I achieve that?
>
Why not assign a random value to a variable and then use a for loop
to insert that number of much smaller (picosecond) delays.
for example:
`timescale 1 ns / 1 ps
. . .
integer i;
reg [16:0] r_shift;
. . .
r_shift <= $random;
for (i = 0;i < r_shift;i = i + 1) #0.001;
. . .
to get a shift of 0 to 131 nS
> Thanks in advance.
>
>
> module mytest;
>
> event start_clk_0;
> always @ (start_clk_0)
> begin
> clk3_84m_0 <= 1'b0;
> #({$random} % (`CLK_HALF_PERIOD)); // To create a random delay.
> forever begin
> #`CLK_HALF_PERIOD clk3_84m_0 <= 1'b1;
> #`CLK_HALF_PERIOD clk3_84m_0 <= 1'b0;
> end
> end
>
>
>
> task inject_tv;
> input ...;
> begin
> ...
> ...
>
> if (condition)
> -->start_clk_0;
>
> ...
> ..
> end
> endtask
>
> initial
> begin
> delay(10000);
> inject_tv(1);
> delay(10000);
> inject_tv(2);
> delay(10000);
> inject_tv(3);
> end
>
>
> endmodule;
Article: 105762"Mateen" <mateen.hasan@yahoo.com> wrote in message news:ee9d396.6@webx.sUN8CHnE... > I experienced a problem with Flash Programmer present under Xilinx EDK. When I tried to program SREC through it, the Flash Programmer programs the FLASH on ML403 with SREC, but without parsing..!!!. If I compare the HEX view of my SREC file and the Flash Memory, they are same (something starting like S31...) This is wrong..!! It's not wrong, it's simply inefficient in terms of using FLASH space. The Xilinx bootloader reads S-records from FLASH and puts the code into SDRAM. /MikhailArticle: 105763
jvdh wrote > This might be slightly OT for an FPGA group, but maybe someone has run > into a similar problem before: > > I'd like to connect my FPGA, via JTAG, to my PC, 100m away. Due to a > hazardous environment, putting the PC any closer isn't feasible > > I'm using a Xilinx parallel cable III, which I extended with RS485 > drivers to get to required distance, before converting back to TTL to > drive the original cable. Could you switch to using a USB cable, extended via off-the-shelf fiber optic USB extenders?Article: 105764
"Olli" <Emperor_@gmx.de> wrote in message news:ee9d396.5@webx.sUN8CHnE... > > So I have to download the bitstream with the bootloader in linear > flash too.Is that right? No, you have to put it into the Platform Flash. If you put it into the linear flash the FPGA won't be able to read it on power-up by itself meaning that an external microcontroller of some sort would be required. I am not sure if this option has been designed in the ML403's CPLD. Check the documentation, it might be possible. > In Impact I have only access to the lin. flash over a cpld. When I choose the > cpld in Impact to write at, will the *.bit file be stored in the lin. flash? No. In Impact you have direct access to Platform Flash. Forget about the CPLD for now. The Platform Flash can be programmed from XPS with Device Configuration/Download Bitstream as well, but for better understanding of what you are doing I would recommend using Impact. To program the Linear Flash you have to go to Device Configuration/Program Flash Memory in XPS. /MikhailArticle: 105765
Hello everybody, 1. I would like to know if anyone's aware of AC2600-HDK platform board available from Atmel. Check link: http://www.arasan.com/products/prod_overview/AC2600-HDK-Flyer-1-0.pdf Has anyone worked with this board?? I am looking for similar boards with Xilinx FPGAs in them. Any suggestions on more boards?? 2. I am also on the lookout for boards with ARM cores available in evaluation kits. Since I am new to this segment of products, can someone suggest a board depending on their experience. Thanks in advance, VivekArticle: 105766
I like the (off the shelf) simplicity of your suggeston :) The way I see it, the main options would be changing the medium (esp to fibre), or slowing the comms down - the later would probably be preferable from a cost point of view... But I'm first trying to confirm that it definitely is the transmission delay that's messing me around. Thanks! Tim wrote: > jvdh wrote > > This might be slightly OT for an FPGA group, but maybe someone has run > > into a similar problem before: > > > > I'd like to connect my FPGA, via JTAG, to my PC, 100m away. Due to a > > hazardous environment, putting the PC any closer isn't feasible > > > > I'm using a Xilinx parallel cable III, which I extended with RS485 > > drivers to get to required distance, before converting back to TTL to > > drive the original cable. > > Could you switch to using a USB cable, extended via off-the-shelf fiber > optic USB extenders?Article: 105767
Hi, I finally got to run the MIG created DDR2 for VIrtex4 devices controller. However I have two problems with the controller: 1. I am observing the ERROR signal which is created by the dataCompare module. It goes high every 8th read pulse. Could this be related to the FIFO16 bug? Is there a way to fix the fifo in the design? It would be easy to fix the fifo issue in my own design but as I havent written the ddr controler i have no glue what the requirements of the fifo16 are and how the issue should can be fixed in the best way. Inverting the readclock (as I read somewhere) didnt work and I do not know if the coregenerated fifos are fast enough and if they can be simply exchanged (no fall through for example). 2. My other problem is of different nature. The simulation environment which is supplied by xilinx does not work with some RAMs. I had no problem simulating a 8bit Micron DDR2 chip however the 16bit chip I am currently using does not work. THe whole testbench verilog files are corrupted showing false instantiations (wrong names, wrong bit sizes) has anybody experienced the same problems? Both problems could be probably solved by disassembing the whole design, but that takes hours, so If anybody has already a solution for the avove problems I would be very happy. thks, regards HeinerArticle: 105768
Falk Brunner wrote: > mpierrotb schrieb: > > > If yes, is there a solution, to manage the two process ( fixed > > acquisition and SDRAM refresh cycle) ? > > I guess you need a inbetween controller with some amount of buffer (FIFO). > > Regards > Falk I think also the OP might be confused about refreshing SDRAM. Normally rather than refreshing the entire RAM every 64 miliseconds, a single row is refreshed every 15 microseconds (sometimes 7.5 microseconds). This takes only a very small portion of the SDRAM data bandwidth and would not require a very deep FIFO. In fact for a streaming application like his, you would normally use a small FIFO anyway to gather up a burst's worth of data before writing to the SDRAM. 30 MHz is very slow compared to the available data bandwidth of the SDRAM (even single data rate RAM) so the length of the DMA would not affect the required FIFO depth either. He could also "cheat" if using single data-rate RAM's and not refresh during DMA. His assertion that the 2 seconds of burst length exceeds the refresh period ignores the fact that the RAM is refreshed by the DMA access itself. This would not be the case with DDR memory, which requires regular refreshing to provide its internal DLL a chance to update (per the JEDEC spec., not all chips actually do this...).Article: 105769
aijazbaig1@gmail.com wrote: > Furthermore, I would appreciate if you look at my code and let me > know if there is anything wrong with the semantics and/or the syntax or > the design flow or anything. Is it just that I can't ISE to work with > it? Take a look at the VHDL handbook: http://www.hardi.com/vhdl.htm On page 23 it says "The libraries WORK and STD and also the package STD.STANDARD are always accessible.". So looks like you don't need to "use" it. Sometimes useful, too: EBNF of VHDL: http://tams-www.informatik.uni-hamburg.de/vhdl/tools/grammar/vhdl93-bnf.html I can't reproduce your error message, but there are lots of little errors, like wrong port names, missing semicolon, incomplete port mappings etc. And looks like you can't use "port map (not actual_part)", but you have to use a signal to invert it and to connect it to another port. Another important thing, if you want to be portable: Don't use "IEEE.STD_LOGIC_ARITH.ALL", because it is NOT standard: http://ghdl.free.fr/ghdl/IEEE-library-pitfalls.html > And is active HDL an all inclusive package? I mean do I need to have > separate software packages to generate waveform testbenches and VHDL > testbenches? Yes, all inclusive: http://www.aldec.com/education/students/ -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 105770
rickman wrote: > Actually, I just looked a bit harder at your code and I don't > understand the notation > mask_wr <= #1 mask_wr_in; > Without looking in one of my Verilog books, what is the "#1" for? Delay by 1 time step. (The step size is defined with the 'timescale directive.) Although Verilog does not offer delta delays like VHDL it is possible to get almost the same behavior using blocked signal assignments (the "<=" operator). And then there is no need for manually written delays. Furthermore it is dangerous, because one can easily code a behavior that would never happen in functional simulation (Verilog has an event queue) nor after synthesis. IMHO it is much better to write good Verilog code than using these delays. See Cliff Cummings "Verilog Coding styles that kill" - which describes Verilog coding very similar to VHDL code. RalfArticle: 105771
I posted this last week, but it has yet to show up on google groups, so I fear my news server isn't as healthy as I would like. So I apologize if this gets double posted. I'm involved with a project where we are trying to figure out if a Stratix II will work for us. Our big question mark right now is memory. We would really like to use a DDR2 SRAM (for reasons I don't want to go into), but Mega-core doesn't support it. We're not opposed to building our own interface, but we're trying to understand the possible reasons Altera doesn't support it. We've been told that basically there's just no demand, so that's why it's not there, but we fear that's not the whole story. First, we're very concerned about simultaneous switching outputs / noise. I'm not familiar enough with Quartus to determine if there is an SSO calculator (like there is in ISE). We need to hang several memory banks off a single part at 200 MHz, so this is a big concern. Second, is the 1.8V HSTL driver in the Altera part capable of supporting the bi-directional specs of a DDR2 SRAM at 200 MHz. I'm sure that this answer is buried somewhere in the Stratix docs, but so far I have been unsuccessful in uncovering it - any help here? Thanks, Eric Amundsen Special Purpose Processor Development Group Mayo Foundation, Rochester MN 507-538-5457; Fax 507-284-9171Article: 105772
One option to produce code with less lines would be this :
always @(posedge clk or negedge rst_n) begin
mask_wr <= !rst_n ? 1'b0 : (adr[2:1] == MASK) ;
clear_wr <= !rst_n ? 1'b0 : (adr[2:1] == CLEAR) ;
end
This way you reduce 16 lines of code to 4
-Deepak Lala
rickman wrote:
> John_H wrote:
> > "rickman" <spamgoeshere4@yahoo.com> wrote in message
> > news:1154101628.534694.304340@s13g2000cwa.googlegroups.com...
> >
> > > Two FFs and four logic elements (x15 in the real circuit). You have to
> > > use a LUT to drive the D input and you have to use a LUT to drive the
> > > enable input. Of course you can feedback the output to the input and
> > > not use the clock enable, but that will also use more LUTs depending on
> > > if you have the extra inputs or not on the LUTs you are using. But
> > > this will be up to the tool and many times I see the tool generating
> > > logic to feed the clock enable.
> > >
> > > It is not a big deal. I tend to think of things like this when I code
> > > in an HDL just so I know my logic generation is lean. Originally I had
> > > not seen the enclosing always statement and was thinking it was
> > > generating a latch. Once I started looking at it I realize the latch
> > > was not an issue but thought about the extra logic being generated. I
> > > tend to separate my registers from my logic just to allow me to
> > > optimize this sort of thing.
> >
> > You're taking the code structure as a literal guide for synthesis. There
> > will be two FFs and two LUTs without a clock enable. Synthesis typically
> > knows what simple logic breaks down to and how to best implement it. If you
> > go into the technology view of your synthesizer to look at one of the flops,
> > expect to see only one LUT driving it, no clock enable involved.
>
> With this simple example you are right, it will require a single
> 4-input LUTs even if you don't use the CE. The logic functions only
> has four inputs and so can be done in a single 4-input LUT. They are
> wr, the two address bits and the feedback from the given register. But
> if there is one more address line the feedback will push it to a pair
> of LUTs. Like I said, it is not a huge difference, but with the large
> number of signals in the real code, this could have been done very
> slightly different and would have been optimal.
>
> I realized that a simple change would not be any more typing and would
> fully specify the assignments to eliminate the need for the feedback
> signal. At least if this works like VHDL it would work correctly.
> Like I said, I am not up to speed in Verilog anymore.
>
> always @ (negedge rst_n or posedge clk) begin
> if (!rst_n)begin
> mask_wr <= 1'b0;
> clear_wr <= 1'b0;
> end
> else begin
> mask_wr <= 1'b0;
> clear_wr <= 1'b0;
> if (wr == 1'b1)begin
> case (adr [2:1])
> MASK: mask_wr <= 1'b1;
> CLEAR: clear_wr <= 1'b1;
> endcase
> end
> end
> end
>
> Rather than specify the default condition in the ELSE of the if
> condition, it is specified first as the default. Then any signal that
> is not assigned in the case statement will still be defined. The above
> is the intended function rather than holding the previous state of the
> signal. But then like I said in another post, I don't code behavior
> and let the tools determine the logic, I describe logic which has the
> behavior I want.
Article: 105773Ben_M wrote: > Hello experts and newsgroup, > > I'm planning a new embedded design. > > The first MicroBlaze handles the communication to external Interfaces > and receives DATA (approx. 3MB) which have to be stored in some kind of > external memory. > > These DATA must be accessed by a second MicroBlaze for multiple > calculations. > > Does Xilinx provide such a multiple access on external memory ? > Which kind of Memory can you suggest ? > > > Thanks a lot, > by > BEN I assume you are implementing the two Microblaze devices within a single FPGA, in which case it becomes a simple matter of a separate memory interface and an internal bus arbiter of some description. Although you say one Microblaze is responsible for communication to external interfaces, there's no reason you can't have a bus mastering scheme provided the data rate is not too high (hint: use internal buffers). Another alternative is a dualported RAM (so you would have an interface from EACH microblaze), but these don't usually come in the sort of size you need, to say nothing of the synchronisation issues to be resolved.. As to the memory type What is the data rate to memory required? Average? Burst? What power consumption can you live with? Do you have a SDRAM controller core? Or do you intend to write one? Can you live with the logic it will take? or DDR? (although that seems way over the top for 3MByte of data). There are a number of solutions, but it's hard to answer without knowing these things; These questions are fundamental to choosing the memory type you should use. Cheers PeteSArticle: 105774
eric.amundsen@gmail.com wrote: > We would really like to use a DDR2 SRAM (for reasons I don't > want to go into), but Mega-core doesn't support it. Anything wrong with this one? http://www.altera.com/literature/ug/ug_ddr_sdram.pdf > We're not opposed > to building our own interface, but we're trying to understand the > possible reasons Altera doesn't support it. We've been told that > basically there's just no demand, so that's why it's not there, but we > fear that's not the whole story. If time is an issue, buy standard interfaces. -- Mike Treseler
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