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GaLaKtIkUs=99 schrieb: > Hi all, > I would like to know before upgrade if EDK8.1i is compatible with > ISE8.2i. >=20 > Thanks in advance NO Antti http://antti-brain.comArticle: 105326
Hi all, Is there some hardware RTL book like "Code Complete" by Steve McConnell? Thanks! DavyArticle: 105327
hi i am new whit this technology. so anyone have or know about a good tutorial of fpga vhdl etc... i bougth the spartan-3E starter kit thanks DavidArticle: 105328
> > Timing sim runs don't always catch things either. If it's a timing problem > then static timing analysis is what you need to solve the problem. Quartus > is already providing that info, but since you said you tried running it > slower (not sure how slow or if it was slow enough per the static timing > analysis) so it might not be a timing problem either which would then leave > it as some form of Quartus bug which is why submitting a bug report to > Altera would help. > As KJ writes, running static timing analysis is the best way to check for timing issues. Running the clock slower won't help you if you have a "Hold" violation, so you really want to make sure your design is fully constraint (Consider using the "Timing Constraint Checker" from the "Process | Start | Start Timing Constraint Check"), and then review the Timing Analysis Report, specially the Hold panels. If you see paths with Hold Slacks under 200ps, check if such paths are between different clocks (even if clocks are in phase). Unless you added some amount of Clock Uncertainty, you may be ignoring Jitter effects. If the clocks are different, you may also be seing some small error due to on-die variation, which is not modeled (which is why you should always add clock uncertainty on paths between different clocks). For more information, check: http://www.altera.com/literature/hb/qts/qts_qii53004.pdf or if you have the V6.0 full edition and you have some experience with SDC, you can also give the new TimeQuest Timing Analyzer a try: http://www.altera.com/literature/hb/qts/qts_qii53018.pdf -David Karchmer AlteraArticle: 105329
Argh! I wish I had thought to ask first! Double-argh! When will Xilinx become more responsible with their version upgrades!Article: 105330
Quartus II is reporting a clock hold time violation in a circuit which
may be described by the following diagram:
-------- --------
d FF q--[logic]--d FF q
-clk | -clk |
| -------- | --------
| |
--o------------------
I understand that the problem is that the input d of the second FF
changes too early after the common clock edge. However, somewhere else
in the same circuit I have the following
-------- --------
d FF q-----------d FF q
-clk | -clk |
| -------- | --------
| |
--o------------------
and quartus II does _not_ report any hold time violation here, and
obviously enough, the situation is even worse.
Something similar appears if I build a divide by 2:
a) directly (inverted q to d) or
b)using a 1 bit wide lpm_counter.
In the first case, I get a hold time violation and everything is ok in
the second case.
Perhaps someone can provide some insight into the following questions:
1. Is something inherently wrong with the first schematic? I even
thought it was always good idea to resynchronize signals in a similar
way.
2. In case this approach is ok, why does quartus II report clock hold
time problems?
3. If applicable, what should I tell the quartus II timing analyzer to
get rid of this error?
Thanks,
Pere
Article: 105331try the "Xilinx Virtex-II Pro FF672 Kit" from Avnet it's about $1000 (DS-KIT-2VP7FF672-NE) then get ahold of some "P160 Analogue" modules from Avnet they're $275 each (DS-KIT-P160-ANALOG1) ...About 1/3rd the price of the N.S. Ben "Vivek Menon" <vivek.menon79@gmail.com> wrote in message news:1153402839.398685.201060@h48g2000cwc.googlegroups.com... > Hi everyone, > I am looking to buy a board that has the following features: > 1. High-speed ADC > 2. Xilinx Virtex-2Pro or Virtex-4 FPGA with Rocket I/O capability > > I looked at the Xilinx development boards (the matrix_Xdev_board > brochure) and could not find one with Rocket I/O and the ADC. The > closest product I have with a high-speed ADC and an FPGA is National > Semiconductor's ADC08D1500 Dev board(arnd $3800). However, I want to > Rocket I/O as well to communicate with other FPGA boards and sensors or > peripherals connected to it. > > Please let me know if you know of a product that has these features. > Thanks in advance, > Vivek >Article: 105332
Did you check whether the reset is performed or not in hardware ? Rgds Andr=E9 > Hi, > I build a DDR2 controller using the Mig 1.5. > > In functional simulation everything works without problems (as > alwayys). In the hardware implementation it does not work. I used the > synthesizable testbench which is provided by the Mig. My design is > driven by a 200Mhz Refclock and 125MHz system clock. I used chipscope > and oscilloscope to figure out the following: > -All clocks (200, 90, 50) work properly. Also clk0 which controlls most > part of the ddr2controller module. > -I can messure the correct RAM clock on the PCB > -After the reset WDF FIFO is empty and the internal writeWDF signal > toggles untill the WDF almost full signal goes active. It stays high > forever. > - The other signals on the PCB (or on chip using chipscope) especially > (ras, cas, we, cs) do not toggle at all. > > SO data is never written to the ram and never read out. The FIFO just > runs full. > > Did anybody experience similar problems and can help? > The xilinx design only uses synchronous resets. These are regarded like > normal signals by the router and hence do not meet the timing (high fan > out probably). Is this ok? How are resets treated in FPGAs anyway? I > always use asynchronous reset so they dont interfere with timing > issues. Can i tell XST in anyway that it should treat reset signals > properly? How to tell XST to make a reset tree synthesis? > Could it be due to the FIFO16 bug? I dont think so, as it doesnt run at > all. The controller should at least try to access the RAM several > times, right?Article: 105333
rsg schrieb: > Argh! I wish I had thought to ask first! Double-argh! When will Xilinx become more responsible with their version upgrades! when searchin back in c.a.f. I found that in EDK 8.2 SP2 was targeted September 2006, but - well I would assume the product itself (EDK 8.2) should be released first? If Xilinx is going to release EDK 8.2 SP2 in sep 2006, when does then EDK 8.2 become available !? And EDK 8.2 SP1 ? Ok, I know EDK 8.2 is actually ready, but Xilinx Website still says that latest EDK version is 8.1 !? I guess Xilinx webmaster is on the vaccation again. There are two words I have for the Xilinx webmaster, unfortunatly not translateable: "na mylo!". Ok its is transalateable => means that the target person should be boiled for the sole purpose of gaining soap. :) smile I am not that frustrated, but the way Xilinx website and marketing is out-of sync with the products and services is not really funny. AnttiArticle: 105334
heinerlitz@gmx.de schrieb: > Hi, > I build a DDR2 controller using the Mig 1.5. > > In functional simulation everything works without problems (as check that the iodelay calibrate block get locked if not it will disable everything else AnttiArticle: 105335
The circuits look fine, my guess is that you made a clock that isn't using the global routing and based on the luck of the draw one circuit meets hold time and the other doesn't. If you are making a clock using the general logic make sure you put onto a dedicated clock net before use. That way it will meet hold time by architecture instead of luck. Jay oopere wrote: > Quartus II is reporting a clock hold time violation in a circuit which > may be described by the following diagram: > > -------- -------- > d FF q--[logic]--d FF q > -clk | -clk | > | -------- | -------- > | | > --o------------------ > > I understand that the problem is that the input d of the second FF > changes too early after the common clock edge. However, somewhere else > in the same circuit I have the following > > -------- -------- > d FF q-----------d FF q > -clk | -clk | > | -------- | -------- > | | > --o------------------ > > and quartus II does _not_ report any hold time violation here, and > obviously enough, the situation is even worse. > > Something similar appears if I build a divide by 2: > a) directly (inverted q to d) or > b)using a 1 bit wide lpm_counter. > In the first case, I get a hold time violation and everything is ok in > the second case. > > Perhaps someone can provide some insight into the following questions: > > 1. Is something inherently wrong with the first schematic? I even > thought it was always good idea to resynchronize signals in a similar > way. > > 2. In case this approach is ok, why does quartus II report clock hold > time problems? > > 3. If applicable, what should I tell the quartus II timing analyzer to > get rid of this error? > > Thanks, > PereArticle: 105336
hi,friends:
I am a fresh man in IC design.How can I start my study in system
design?I need ur suggestions.Can u commend some book for me?How to
write the system specification=EF=BC=9FHow to construct the system model?How
to verify in system level?What tool and language should I use=EF=BC=9F
And now,I use FPGA/CPLD to implement my design,I also want to
know some methods about static timing analyze of FPGA/CPLD.
Thanks a lot.
Article: 105337Hi group, here's a question: Can I synthesise a component described in Verilog, obtain an EDIF, then write a VHDL wrapper around it so as to integrate it into a greater VHDL project. yours in ignorance, RobinArticle: 105338
> Hi all, > I downloaded code for a vga generator from xess design examples. I just > want to verify that my board is functioning properly. The vga generator You might want to ask the question in http://groups.yahoo.com/group/xsboard-users/ Best regardsArticle: 105339
Robin Bruce schrieb: > Hi group, here's a question: > > Can I synthesise a component described in Verilog, obtain an EDIF, then > write a VHDL wrapper around it so as to integrate it into a greater > VHDL project. > > yours in ignorance, > > Robin you should yes. most of the tools allow any mix of verilog-vhdl, but you can also use edif as interim format anttiArticle: 105340
Hi John, I don't understand the following memory allocation issue you mentioned: "Every time 16 words are read in, that cell is added to a free list. On avg, you write 1 of the 256 letter cells for every cell you read in. Memory cost is therefore N+N/16 for 16 word deep buffers. " For example, all 1 million keywords starts with same one of 256 letters? Could you please give more details? Or any references in Knuth volumn 3 book? Thank you. Weng JJ wrote: > heinerlitz@gmx.de wrote: > > Hello, > > > > we have a Virtex4 FPGA and are looking for availlable hardware sorting > > algorithms. I couldnt find anything @opencores.org however I guess that > > it has been worked on this subject. > > > > The Virtex4 supports 2 PowerPCs and lots of Block RAMs so everything > > seems to be there. Are there any projects and what speeds could be > > estimated for sorting 64 bit integers? > > > > thx Heiner > > It all depends on what type of data you have, is it already sorted > almost correctly, or soso, or fully random. look at Knuths texts for > the algorithms. > > If you need to sort a huge array of integer keys I favor the radix > sort, for 64 bit values, use 8 passes with 256 variable length output > buckets whose total size will be same as initial array.. The time will > go towards 16N memory cycles which may use the fastest rate of memory > access, potentially at DDR rates even. > > Its is just like sorting a telephone book where you take the initial > say random name list and put all the names beginning with 'a' into the > 'a' bucket and similar for other letters. In this case you have 256 > letters. On 2nd pass inspect 2nd letter. Every time you have say 16 'a' > words you bag them and put them into the 'a' pile. You want to do > mostly reads and mostly writes as bursts rather than interleaving reads > & writes. Blockrams can be used as your letter bags. > > Its get more interesting when you figure how to manage the buckets. > BlockRams can be usefull for holding blocks of each letter. 1 Blockram > with 256 64b words would only hold 1 word buffer for each of the 256 > buckets. So 16 Blockrams would hold 256 buckets of 16 words deep. You > want them to be as deep as possible to reduce the cost of bucket > management. You could think of these Blockram buckets as soft 256 Fifos > (16 word deep) into main memory. > > Only when each letter bucket fills do you need to have to write it out > and find a new place to write it. One way to do that is to assume the > input data is matched by a similar sized output array which is broken > into 16 word cells. Add to that a link list to manage the cells, then > its is a matter of managing 256 link list heads and a simple table > that will need 1 word per cell. > > If you get really good at this, with small buffers for inputs and > outputs, you can effectively do this inplace in main memory, though > many will use separate in and out buffers. Every time 16 words are read > in, that cell is added to a free list. On avg, you write 1 of the 256 > letter cells for every cell you read in. Memory cost is therefore > N+N/16 for 16 word deep buffers. > > Ofcourse you should proto this in C/whatever and observe its operation. > The HDL code will look similar. > > > John Jakson > transputer guyArticle: 105341
Doing an Internet search helps things sometimes. David wrote: > hi > i am new whit this technology. > so anyone have or know about a good tutorial of fpga vhdl etc... > i bougth the spartan-3E starter kit > thanks > > DavidArticle: 105342
Hi, I using Xilinx System Generator tool and need to use DCM for Virtex-II Pro board. But after searching on internet I could not find any relevant material. Any kind of help will be highly appreciated. JunaidArticle: 105343
On 20 Jul 2006 07:41:49 -0700, "David" <aresolimpico@gmail.com> wrote: >hi >i am new whit this technology. >so anyone have or know about a good tutorial of fpga vhdl etc... >i bougth the spartan-3E starter kit >thanks > >David Try this: http://www.engr.sjsu.edu/crabill/ Bob Perlman Cambrian Design Works http://www.cambriandesign.comArticle: 105344
Hi Junaid, You should probably use the Architecture Wizard to instantiate the DCM for V2Pro. Vivek junaidabidi wrote: > Hi, > I using Xilinx System Generator tool and need to use DCM for Virtex-II > Pro board. But after searching on internet I could not find any > relevant material. Any kind of help will be highly appreciated. > > JunaidArticle: 105345
Vivek How many channels of high speed do need? The ADC08D1500 we have been looking at as a possibility of doing a module and maybe I can get fitted in sooner than later. We are running a batch of modules of the right level of technology soon. Give us some detail we just might be able to come up with something. John Adair Enterpoint Ltd. Vivek Menon wrote: > Hi everyone, > I am looking to buy a board that has the following features: > 1. High-speed ADC > 2. Xilinx Virtex-2Pro or Virtex-4 FPGA with Rocket I/O capability > > I looked at the Xilinx development boards (the matrix_Xdev_board > brochure) and could not find one with Rocket I/O and the ADC. The > closest product I have with a high-speed ADC and an FPGA is National > Semiconductor's ADC08D1500 Dev board(arnd $3800). However, I want to > Rocket I/O as well to communicate with other FPGA boards and sensors or > peripherals connected to it. > > Please let me know if you know of a product that has these features. > Thanks in advance, > VivekArticle: 105346
For information on the DCM, please see the Virtex-II Pro users manual and the Libraries Guide, both available in the documentation section of the Xilinx website. "junaidabidi" <junaidabidi@gmail.com> wrote in message news:1153414879.965745.165300@b28g2000cwb.googlegroups.com... > Hi, > I using Xilinx System Generator tool and need to use DCM for Virtex-II > Pro board. But after searching on internet I could not find any > relevant material. Any kind of help will be highly appreciated. > > Junaid >Article: 105347
Jarrod, I am having the same problem. I am trying to put in an FPU core from coregen into EDK and have it interface to the APU. So far, I haven't been able to figure it out, and Xilinx support isn't very helpful with this. I am wondering if you got any further. If you have any more infomation it would be very helpful if you could post it. Thanks Dmitriy Bekker Jet Propulsion LaboratoryArticle: 105348
John Adair wrote: > .... Currently the spec on the card is as follows: > > Dual Spartan-3E (Device 1 notionallly fixed covering Cardbus interface etc), > Device2 programmable from Device1 or SPI prom. > Device 2 = XC3S1200 or XC3S1600 ..... > SDRAM + second SPI Flash on Device2 All that fits on a cardbus card?? :-) What size, speed, and buswidth of the SDRAM? The ideal would be the largest RLDRAM-II device possible, but failing that, as large and fast as possible. Any price estimates yet? Regards, TommyArticle: 105349
Hi - I don't know if anyone else has mentioned it, but please make sure you have lots of grounds, well spread out, on the external module connector(s). Bob Perlman Cambrian Design Works http://www.cambriandesign.com On Thu, 20 Jul 2006 10:48:42 +0100, "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote: >We have mentioned Tarfessock1 before and now at the last point where we can >add features for the board. You know have the last chance to ask for things >you might want in this Cardbus format card so do ask. Currently the spec on >the card is as follows: > >Dual Spartan-3E (Device 1 notionallly fixed covering Cardbus interface etc), >Device2 programmable from Device1 or SPI prom. >Device 2 = XC3S1200 or XC3S1600 >4 ch DAC >8 ch A/D >O/P JTAG - looks like parallel port + cable3 for programming outside target >boards. Supported by Device1. >1 serial RS232 interface outside world for MicroBlaze support etc. 1 >internal serial (TTL) also possible to Device2. >4 ch RS485 serial controllable half duplex. >SDRAM + second SPI Flash on Device2 >Approx 70 5V tolerant I/O to outside world. >Switched 3.3V O/P to supported external modules that don't need to be >powered all the time (i.e. for running in the wild on laptop battery etc). > >We are using a 120 pin connector to support all these features and there >will be breakout board/s available to better pitches. > >We are currently still on schedule for a September launch. > >John Adair >Enterpoint Ltd. - Soon to be Home of Tarfessock1. The Spartan-3E Cardbus >Development Board. >http://www.enterpoint.co.uk >
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