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Weng Tianxiang wrote: > Hi John, > I don't understand the following memory allocation issue you mentioned: > "Every time 16 words are read > in, that cell is added to a free list. On avg, you write 1 of the 256 > letter cells for every cell you read in. Memory cost is therefore > N+N/16 for 16 word deep buffers. " > > For example, all 1 million keywords starts with same one of 256 > letters? > > Could you please give more details? Or any references in Knuth volumn 3 > book? > Well its not that dificult to write a small C program to explore this. Get a small rand function, like R250 and fill up a 1M word array and make a ptr table to every 16th word and make 256 empty head ptrs. Set up 256 empty 16 word fifos. Arrange the C code to use an FSM in a loop so that every iteration, data moves from the array to 1 of the 256 buffers for 16 cycle bursts. If any of the buckets should fill, copy them to a write back buffer. During the 16 word read intervals, insert write backs. Its would be much easier to just use 2x as much Blockram and let the buffers be 32 words deep. While all buffers less than 16 deep, keep reading in bursts. When any buffer crosses 16, write out the previous 16 during a read interval.. Basically you have a DMA engine that is always reading or writing 16 words blocks so DRAM can be efficient. You can change the 16 for another burst size by changing the bucket depths. Use consts ofcourse. It doesn't really matter if all the letters are evenly distributed or even all mostly the same. That only changes the routing of bucket fifos into the output stream. The input data of 64K 16 word entries all starts on 1 link list is going to be replaced by 64K 16 word blocks spread on 256 distinct lists, even if most might actually be on 1 list for uneven letters. On the next pass, the engine will iterate through each of these 256 input lists and write back sort of inplace back to tha same list. I could see 2 memory systems in play, the data reads and writes to the 1M array, and a separate system to do the header link list management. Every write back of a bucket needs for the link list FSM to track the 256 headers. The HDL FSM will be pretty much the same structure. Ofcourse writing a program on a NG post is much easier than writing it for real, but really this isn't rocket science. This is about a days worth of C coding & testing. Perhaps a basic text on link lists might be more useful than Knuth since thats is really all this is. John Jakson transputer guyArticle: 105351
Thanks . Josep Dur=E1n wrote: > > Hi all, > > I downloaded code for a vga generator from xess design examples. I just > > want to verify that my board is functioning properly. The vga generator > > > You might want to ask the question in >=20 > http://groups.yahoo.com/group/xsboard-users/ >=20 >=20 > Best regardsArticle: 105352
Hi John, I am doubtful if anything can be done on ADC08D1500 as it supports a Virtex4 LX15 that does not have Rocket I/O capability. Vivek John Adair wrote: > Vivek > > How many channels of high speed do need? > > The ADC08D1500 we have been looking at as a possibility of doing a > module and maybe I can get fitted in sooner than later. We are running > a batch of modules of the right level of technology soon. > > Give us some detail we just might be able to come up with something. > > John Adair > Enterpoint Ltd. > > Vivek Menon wrote: > > Hi everyone, > > I am looking to buy a board that has the following features: > > 1. High-speed ADC > > 2. Xilinx Virtex-2Pro or Virtex-4 FPGA with Rocket I/O capability > > > > I looked at the Xilinx development boards (the matrix_Xdev_board > > brochure) and could not find one with Rocket I/O and the ADC. The > > closest product I have with a high-speed ADC and an FPGA is National > > Semiconductor's ADC08D1500 Dev board(arnd $3800). However, I want to > > Rocket I/O as well to communicate with other FPGA boards and sensors or > > peripherals connected to it. > > > > Please let me know if you know of a product that has these features. > > Thanks in advance, > > VivekArticle: 105353
I have set up the JTAG chain as you said, all 3 devices, generated the ACE file, and it doesn't work again, red 'err' led is on, green 'done' led stays off: Device #0 was xcf32p Device #1 xc95144lx Device #2 xc4vsx35 I assigned the configuration bit file to the device#2, generated the ACE file and downloaded it properly to the CF card. When I put the card on the ML402 board, turned it on, red led 'err' is on. I tried simple configuration - simple design that should just turn the led DS6 on. Thanks Dan Ed McGettigan wrote: > Dan wrote: > > Ed McGettigan wrote: > > > > Are you sure that you set up the >JTAG chain properly in iMPACT when you > > generated the ACE file? The >chain should be defined as > > > > XCF32P -> XC4VSX35 -> XC95144XL > > > > How do I set up the JTAG chain in iMPACT? What I see on the iMPACT is: > > > > xc4vsx35 myfile.bit -> XCCACE-TQ144I > > Since you haven't described the full chain for iMPACT, the software isn't > creating a valid ACE file for your chain to bypass the other devices. > > When you are in the iMPACT main window you need to either select the toolbar > icon for "Add Device" or right mouse button click to "Add a device". You > need to create the same chain in the tool as exists on the board first, then > you can go ahead and assign your bit file to the SX35 and generate an ACE > file. > > EdArticle: 105354
Symon wrote: > "Frank Buss" <fb@frank-buss.de> wrote in message > news:q00un4e7pes4$.dq3b878hyk9z.dlg@40tude.net... > >>Antti wrote: >> >> >>>if non xilinx optimized 32 Bit softcore RISC can run at 200MHz, not >>>bad. Sure the test setup was using only BRAMs for code-data storage and >>>had only single FSL link as connection to external world, still a >>>"screaming-streaming" softcore that takes 2% of logic and runs at >>>200MHz is pretty cool I think. Can you post the resource usage mapping ? >> >>If you need only 2% it would be really cool to implement 50 parallel cores >>in one FPGA. >> > > ... cool and hot! :-) > > Antti, > Any idea where the timing improvement is coming from? Ben mentioned the > othyer day that the carry chain is 20ps / LUT; I guess that doesn't hurt! > Cheers, Syms. The other test, is to verify on silicon that this a) Does actually operate to 200MHz b) See how far it can overclock :) -jgArticle: 105355
I also tried to edit the svf file in order to add //NEW CODE SEGMENT: Loading device with a 'bypass' instruction SIR 14 TDI (3fff) SMASK (3fff) ; RUNTEST 2434000 TCK ; as per http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguageID=1&getPagePath=23146&BV_SessionID=@@@@1939425689.1153421274@@@@&BV_EngineID=cccjaddiggjkkmgcefeceihdffhdfjf.0 unfortunatelly no results, still can't configure the board.Article: 105356
EEngineer wrote: > I have set up the JTAG chain as you said, all 3 devices, generated the > ACE file, and it doesn't work again, red 'err' led is on, green 'done' > led stays off: > > Device #0 was xcf32p > Device #1 xc95144lx > Device #2 xc4vsx35 > > I assigned the configuration bit file to the device#2, generated the > ACE file and downloaded it properly to the CF card. When I put the card > on the ML402 board, turned it on, red led 'err' is on. > > I tried simple configuration - simple design that should just turn the > led DS6 on. You still don't have the right order you need to swap your device 1 and 2. The chain information is in the ML402 documentation. See page 31 http://www.xilinx.com/bvdocs/userguides/ug080.pdf Ed -- Xilinx Inc.Article: 105357
What should be the size of the ACE file, I always get 1674KB when iMPACT generates it, versus all the 8 demos, they are all of the exactly same size: 1686KB?Article: 105358
I have changed the order: Device #0 was xcf32p Device #1 xc4vsx35 Device #2 xc95144lx Assigned the configuration bit file again to the xc4vsx35 device, generated ACE, put it on CF, again could not configure the board. Thanks, Dan Ed McGettigan wrote: > EEngineer wrote: > > I have set up the JTAG chain as you said, all 3 devices, generated the > > ACE file, and it doesn't work again, red 'err' led is on, green 'done' > > led stays off: > > > > Device #0 was xcf32p > > Device #1 xc95144lx > > Device #2 xc4vsx35 > > > > I assigned the configuration bit file to the device#2, generated the > > ACE file and downloaded it properly to the CF card. When I put the card > > on the ML402 board, turned it on, red led 'err' is on. > > > > I tried simple configuration - simple design that should just turn the > > led DS6 on. > > > You still don't have the right order you need to swap your device 1 and 2. > > The chain information is in the ML402 documentation. See page 31 > http://www.xilinx.com/bvdocs/userguides/ug080.pdf > > Ed > -- > Xilinx Inc.Article: 105359
Try the text "RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability." A sample chapter on FSM can be found in http://academic.csuohio.edu/chu_p/ Hope this helps. S.C. Davy wrote: > Hi all, > > Is there some hardware RTL book like "Code Complete" by Steve > McConnell? > > Thanks! > DavyArticle: 105360
Hey all,
I'm currently bringing up Linux on a Xilinx XUP demo board and I could
use some assistance. For those who are unfamiliar, the XUP has a
Virtex II Pro with 2 hard-core PPC405 processors. I have been
following the EMPART tutorial to get things going
(http://www.cs.washington.edu/research/lis/empart/xup_ppc_linux.shtml)
and am ~almost~ there.
I have the basic system up and running and things look good EXCEPT: I
can not seem to map into a custom IP hanging off the OPB bus.
Actually, I can't manage to communicate with any peripherals at all off
the OPB bus.
As per the EMPART tutorial's recommendations, here's how I attempt IP
access:
fd = open("/dev/mem", O_RDWR);
ptr = MAP_FAILED; // Initialize to bad value
ptr = (int *) mmap(0, 256, PROT_READ|PROT_WRITE, MAP_SHARED, fd,
USER_LOGIC_BASEADDR);
if(ptr==MAP_FAILED) {
printf("Err: cannot access address!\n");
return -1;
}
*ptr = 0xA;
The mmap call appears to work, and returns a pointer to virtual memory
that supposedly references the physical address my IP is located at.
However, when I try to read or write to this pointer I just get a
rather ambiguous "bus error".
In attempt to diagnose the problem, I have tried simple file i/o calls
to /dev/mem via the fd variable specifically lseek and read() /
write(). These also fail. lseek works, but then when I try to read or
write it returns 0.
It is noteworthy, however, that when I make a stand-alone project in
Xilinx EDK and acces my custom IP from there everything works fine.
So, anyone have any suggestions? Could this have to do w/ the PPC405's
MMU or something? Anyone have any experience here?
Thanks much for your help,
--scott
Article: 105361"Antti" <Antti.Lukats@xilant.com> wrote in message news:1153409257.506579.321890@i42g2000cwa.googlegroups.com... > rsg schrieb: > > I guess Xilinx webmaster is on the vaccation again. There are two words > I have for the Xilinx webmaster, unfortunatly not translateable: "na > mylo!". Nu zachem tak uzh srazu... Seriously, I don't think it's a job for one person, so maybe he/she is a little overwhelmed... /MikhailArticle: 105362
Antti wrote: > heinerlitz@gmx.de schrieb: > > >>Hi, >>I build a DDR2 controller using the Mig 1.5. >> >>In functional simulation everything works without problems (as > > > check that the iodelay calibrate block get locked if not it will > disable everything else > > Antti > 1. Check the map report to make sure that all your IOs go to the pins that you want. 2. I found that the controller doesn't start up correctly from power-on, but it can be reset by driving the SYS_RESET_IN signal high, then low. 3. If you can look at the command signals (RAS, CAS, WE) going to the SDRAM, you should be able to see the INIT commands. After init, the controller issues many read commands and looks at the strobe signals to calibrate the iodelay. This should be obvious from the scope if you can look at a datastrobe or two. 4. After the iodelay is calibrated, the controller writes a pattern to memory then tries to read it back. If you have a chipscope, look at COMP_DONE. When it is high, the memory is ready to use. I took this signal out to the top of the hierarchy and have it as a register bit that my PPC can look at to see the health of the memory. 5. Consider fixing the FIFO16s, at least the ones that hold the memory addresses. The ones that hold the write data are clocked by the MClk and MClk90, so they may be OK. --- Joe Samson Pixel VelocityArticle: 105363
> Is there some hardware RTL book like "Code Complete" by Steve > McConnell? I don't think so, but that would be super cool if there was. Have you considered writing one? My impression is that hardware people don't like to write much, and even if they do, they don't have time to sit down and document all of the important "big issues" that new people need to learn in order to be effective. But if anyone writes a book like this it will fly off the shelves!Article: 105364
Hi JJ, Thank you. WengArticle: 105365
Hi Eric, It is not because hardware engineers are lazy, but most of what they have written for any interesting projects are properties of their companies that prevent them from disclosing, not mention writing a book. SunMicro system published their CPU core with 350K code lines. If there is a retired Sun engineer who had involved in the design and will write something about the CPU project, I would like to be the first one to order his book. Nobody can read a CPU design with 350K code lines and at the same time without comments and introductions. Weng Eric wrote: > > Is there some hardware RTL book like "Code Complete" by Steve > > McConnell? > > I don't think so, but that would be super cool if there was. Have you > considered writing one? > > My impression is that hardware people don't like to write much, and > even if they do, they don't have time to sit down and document all of > the important "big issues" that new people need to learn in order to be > effective. > > But if anyone writes a book like this it will fly off the shelves!Article: 105366
Eric wrote:
> But if anyone writes a book like this it will fly off the shelves!
A few hundred copies would fly off the shelves.
There's probably about 10,000 digital designers
in the US. Not all of those do hardware description
and not all of those write their own RTL.
Those are not numbers that would excite
a major publisher.
Writing and editing a book is two long years
of work, whatever the subject.
-- Mike Treseler
Article: 105367Hi Everybody, I want to take this opportunity to let you know about the x8 PCI Express solution from Altera. To try and put things into perspective, Altera is trying to enable customers be successful by offering complete PCI Express solutions. For x8 PCI Express applications the solution consists of: Stratix II GX FPGA (The FPGA is shipping now) The x8 IP Core (The IP core is a released product now) Altera PCI Express Development Kit, Stratix II GX Edition The PCI Express Development board (with the Stratix II GX FPGA), included in kit mentioned above, with the up to x8 IP core was taken to the PCI SIG and it passed 100% of the interop and 100% of the mandatory Gold tests. The kit is open for orders right now and should be shipping to our customers in the next 3-4 weeks. Please feel free to contact the Altera Sales representatives/FAEs in your region if you want to see a demo of the x8 solution immediately (before we start shipping it in the next coming weeks) or if you have any other questions on this PCI Express solution. Here are a few links that I think might be useful to you: http://www.altera.com/products/devkits/altera/kit-pciexpress_s2gx.html http://www.altera.com/products/ip/iup/pci-express/m-alt-pcie8.html http://www.altera.com/technology/high_speed/protocols/pci_exp/pro-pci_exp.h= tml Regards, Aashish Antti wrote: > GaLaKtIkUs=99 schrieb: > > > Hi all, > > We are about to implement a PCIe x8 core but don't want to make it on > > Virtex-4 FX devices, so the PHY layer should be realized by external > > chips. So the question is: is it possible to use 8 external x1 PHY > > devices (for example Philips PX1011A or TI XIO1100) to form a x8 PHY? > > at least PLDA fully supports PCIe 8 lane by using 2 times quad PCIe > PHYs >=20 > Antti > http://antti-brain.comArticle: 105368
Too bad the author is a proponent of the ancient style of separate clocked and combinatorial processes in VHDL. He even uses a third process for registered outputs. I think he needs to discover what variables can do for you in a clocked process. AndyArticle: 105369
Antti wrote: > Hi > > Very first Virtex-5 test reports, tested with OpenFire (32bit Risc, > MicroBlaze clone) targetting V5VLX50-3 (fastest speed grade) > > System clock constrained to 200MHz Hi Antti, Well, perhaps I'm going to get myself in trouble but what the heck: You inspired me to see how fast I can get Nios II in stratix II (2S60-3 chip). The system was minimal w/ 64K ram undoubtedly not much different from yours. On the first try it hit a hair over 200MHz (requested 200MHz). For the second try I asked for 225Mhz and it came out at 211. This is Quartus/Nios II 6.0 SP1. Note: no seed-sweeping or other optimization was performed. Checked the standard 'go-fast' tick-boxes in Quartus and pressed compile (was about a 25-minue compile on my average desktop). Just some 90nm food for thought. Jesse Kempa Altera jkempa --at-- altera --dot-- comArticle: 105370
Mike Treseler wrote: > Eric wrote: > > > But if anyone writes a book like this it will fly off the shelves! > > A few hundred copies would fly off the shelves. > > There's probably about 10,000 digital designers > in the US. Not all of those do hardware description > and not all of those write their own RTL. > Those are not numbers that would excite > a major publisher. > Writing and editing a book is two long years > of work, whatever the subject. > > -- Mike Treseler And even in a metro hub like Boston, MIT Cambridge area, a good book store inside the Microcenter hardly ever sold any of these Hardware books to any of us, the books were really too expensive at $70-$150 & up so were mostly browsed (and dated). They dumped them at $10 a pop instead and now stick to the VB, Java, Web, & ofcourse "Code Complete" stuff that does move. Softbooks in Marlboro also moved on sigh. When you visit DAC & other big hardware design events, you can often talk directly with several fine publishers, they are often quite eager to talk to would be authors too. They also have all the relevant and upcoming books in their booths with a modest show discount too. I get the impression that unless you are writing for the college market, the payback for the author would never cover the time spent. And by the time you are ready to write, the subject is already changed. John Jakson transputer guyArticle: 105371
I believe that separating the FSM into a combinational logic and a register is the first guideline for coding state machines in "Reuse methodology manual" by Keating. Mike G. > Andy wrote: > Too bad the author is a proponent of the ancient style of separate > clocked and combinatorial processes in VHDL. He even uses a third > process for registered outputs. > > I think he needs to discover what variables can do for you in a clocked > process. > > AndyArticle: 105372
On Thu, 20 Jul 2006 17:07:53 -0700, Mike Treseler <mike_treseler@comcast.net> wrote: >> But if anyone writes a book like this it will fly off the shelves! > >A few hundred copies would fly off the shelves. [...] >Those are not numbers that would excite >a major publisher. >Writing and editing a book is two long years >of work, whatever the subject. Agreed. However... it seems to me that comp.lang.verilog/vhdl and comp.arch.fpga represents a useful pool of expertise. It's not part of *my* skill-set to do this, but I wonder if someone could consider setting-up a Wiki (freely-editable website) that could be used as a readily accessible repository of this kind of stuff? It would take a while before we got a reasonable collection of material in it, but a couple of evenings' work by each of a few dozen skilled people might make for a great collection of ideas and tips. And who knows, at some point it might provide the source material for a real paper-and-ink book that you could take on vacation to read at the beach :-) The Tcl/Tk Wiki is an alive-and-kicking example: see http://wiki.tcl.tk/0 Here are some ramblings that convince me it's an idea worth pursuing: Our VHDL and Verilog courses teach language essentials and coding style, and discuss some generally-applicable design techniques such as FSMs, but to keep them generic (and a reasonable length!) we don't discuss how to design any specific kind of hardware. But we have often been asked to create a course covering "the art of good RTL design" or somesuch. What these customers seem to want is something like "thirty years of design experience in a three-day class". It's never been feasible for us to do that, because the exact content would be so specific to the particular needs of any one customer. But an open, peer-moderated, frequently-updated repository sounds like a good idea to me. I don't mean a library of complete ready-cooked designs like opencores.org; rather, I'm thinking of a collection of "design patterns" and shared experience. Any takers? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 105373
kempaj@yahoo.com wrote: > Antti wrote: > >>Hi >> >>Very first Virtex-5 test reports, tested with OpenFire (32bit Risc, >>MicroBlaze clone) targetting V5VLX50-3 (fastest speed grade) >> >>System clock constrained to 200MHz > > > Hi Antti, > > Well, perhaps I'm going to get myself in trouble but what the heck: You > inspired me to see how fast I can get Nios II in stratix II (2S60-3 > chip). The system was minimal w/ 64K ram undoubtedly not much different > from yours. On the first try it hit a hair over 200MHz (requested > 200MHz). For the second try I asked for 225Mhz and it came out at 211. > This is Quartus/Nios II 6.0 SP1. > > Note: no seed-sweeping or other optimization was performed. Checked the > standard 'go-fast' tick-boxes in Quartus and pressed compile (was about > a 25-minue compile on my average desktop). > > Just some 90nm food for thought. Interesting. Of course the OpenFire can probably target either Xilinx, or Altera, (no license restrictions saying 'only our chips' ) so numbers on OpenFire in 2S60-3 would be interesting - care to run those ? [ may as well give both the compile times, and reported MHz.. ] -jgArticle: 105374
Also, look at the multi-cycle hold in the help section of Quartus. "oopere" <oopere@netscape.net> wrote in message news:1153408027.691966.40970@i3g2000cwc.googlegroups.com... > Quartus II is reporting a clock hold time violation in a circuit which > may be described by the following diagram: > > -------- -------- > d FF q--[logic]--d FF q > -clk | -clk | > | -------- | -------- > | | > --o------------------ > > I understand that the problem is that the input d of the second FF > changes too early after the common clock edge. However, somewhere else > in the same circuit I have the following > > -------- -------- > d FF q-----------d FF q > -clk | -clk | > | -------- | -------- > | | > --o------------------ > > and quartus II does _not_ report any hold time violation here, and > obviously enough, the situation is even worse. > > Something similar appears if I build a divide by 2: > a) directly (inverted q to d) or > b)using a 1 bit wide lpm_counter. > In the first case, I get a hold time violation and everything is ok in > the second case. > > Perhaps someone can provide some insight into the following questions: > > 1. Is something inherently wrong with the first schematic? I even > thought it was always good idea to resynchronize signals in a similar > way. > > 2. In case this approach is ok, why does quartus II report clock hold > time problems? > > 3. If applicable, what should I tell the quartus II timing analyzer to > get rid of this error? > > Thanks, > Pere >
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