Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On 2 Aug 2006 12:14:50 +0200, Symon <symon_brewer@hotmail.com> wrote: >Whoops, you're of course quite correct. (Must not post > before 1st coffee of the day!) [...] >Thanks for correcting that no problem... language confusion seems to go with the territory in EDA-land. Swapping among Verilog, VHDL, SystemVerilog, Tcl, e, C, C++ and so on, the usual question is "where does the semicolon go TODAY?". The charitable excuse is that there are more languages to worry about these days; the real reason is that my memory ain't what it used to be! -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 105876
Okay, thanks a lot for your answer, I'll check the details ! Bye BEN PeteS schrieb: > Ben_M wrote: > > Hello experts and newsgroup, > > > > I'm planning a new embedded design. > > > > The first MicroBlaze handles the communication to external Interfaces > > and receives DATA (approx. 3MB) which have to be stored in some kind of > > external memory. > > > > These DATA must be accessed by a second MicroBlaze for multiple > > calculations. > > > > Does Xilinx provide such a multiple access on external memory ? > > Which kind of Memory can you suggest ? > > > > > > Thanks a lot, > > by > > BEN > > I assume you are implementing the two Microblaze devices within a > single FPGA, in which case it becomes a simple matter of a separate > memory interface and an internal bus arbiter of some description. > > Although you say one Microblaze is responsible for communication to > external interfaces, there's no reason you can't have a bus mastering > scheme provided the data rate is not too high (hint: use internal > buffers). > > Another alternative is a dualported RAM (so you would have an interface > from EACH microblaze), but these don't usually come in the sort of size > you need, to say nothing of the synchronisation issues to be resolved.. > > As to the memory type > > What is the data rate to memory required? > Average? > Burst? > > What power consumption can you live with? > > Do you have a SDRAM controller core? Or do you intend to write one? > Can you live with the logic it will take? or DDR? (although that seems > way over the top for 3MByte of data). > > There are a number of solutions, but it's hard to answer without > knowing these things; > These questions are fundamental to choosing the memory type you should > use. > > Cheers > > PeteSArticle: 105877
"john" <conphiloso@hotmail.com> wrote in message
news:1154456339.077044.118270@s13g2000cwa.googlegroups.com...
> Hi,
>
> I posted in multiple groups becuase the fuzzy nature of the question.
The correct way to do that is to cross-post. That way people who subscribe
to all these groups don't have to read and re-read your question and get
frustrated (like Marco no doubt just did).
> plus its my right to post question in any group I want.
> IF U DONT WANT TO ANSWER IT THEN DO NOT BOTHER OK!
Yeah, yeah, we all have rights. There's no need to shout... :)
Cheers,
-Ben-
Article: 105878Hi I am using the eval version of chipscope 8.2 with a Virtex 2 Pro. I have a problem when I configure the FPGA I get the following message INFO: Found 0 Core Units in the JTAG device Chain. I have looked at Xilinx answer record 19337 and everything appears to be ok, although it is for ver 6.3 Does anyone have any ideas? Cheers JonArticle: 105879
Hi, I have a ISE7.1 project containing the PCI .ngo file. This completes correctly. Ugrading to ISE8.2i the .tcl script file generated for Leonardo now includes this .ngo as a source file which Leonardo fails to read. How does one solve this using the integrated flow? Thanks AnthonyArticle: 105880
Kolja Sulimma wrote: > Ray Andraka wrote: > > John_H wrote: > > > A DDS can be used to get a programmable rate that is not an integer > > multiple of the clock frequency and that has a linear relationship > > between the program value and the output frequency. The DDS is > > basically just an accumulator to which a fixed increment is added on > > each clock cycle. The square-wave output is taken from the MSB of the > > accumulator. (It will have jitter of up to a clock cycle depending on > > the increment value). > > I prefer Bresenhams algorithm for frequency generation. > The N-bit accumulator has a frequency error of up to 1/2^N. > Bresenhams algorithm is exact for the question "generate N pulses in M > clock cycles". I also has minimum jitter (up to half a clock cycle). > The hardware implementation is simple and small. > > Kolja Sulimma I have't heard of that... could you post some links? Thanks, JWArticle: 105881
Dear all, I'm in the early stages of designing a board with a Virtex-4 FX on it which we are planning to use for development involving RocketIO. The other guys on the team have stated that it would be "really useful" to have the clock for the RocketIO fed from a programmable oscillator. We have a Virtex-II FX development board that has a similar arrangement, using a ICS8442 low jitter LVDS frequency synthesizer. Does anyone have any suggestions or advice? Can/Should I use the same device? Is this a wild goose chase? TIA PeterArticle: 105882
I have an IP core made up of verilog files as well as vhdl files. How do I set my mpd file for the bitstream generation in XPS? I tried putting OPTION HDL =MIXED OPTION STLYE = HDL but it doesnt work . Anyone done this before. Thanks, NiteshArticle: 105883
Hi, I'm a beginner in FPGA development and I am trying to develop an image processing application on a Xilinx ml403 development board. I'm not able to use the cy7c67300 USB controller and all the examples I found either dedicated to other boards or not helping at all. Does anyone can help with a ready to use example for that board? Thanks in advance, ElenaArticle: 105884
Użytkownik PeteS napisał: > Górski Adam wrote: > >>Uzytkownik subint napisal: >> >>>Hi, >>> I am using a ddr(mt46v32m16fn -6) ddr and Virtex4 (lx60) fpga. >>>And i am using the controller generated by the MIG1.5 tool. When i run >>>this controller in the real hardware i am getting zeros in the result >>>bus(read_data_fifo_out)... Dont know where i am wrong. >>> I am monitored all my controller signals using the chipscope >>>and they are all working fine for me. But the ddr is not giving >>>anything back... >>> Can u guys please tell me what is the minimum frequency at >>>which i can operate the ddr controller. >>>regards >>>subin >>> >> >>Proper frequency range for your memory is from 77MHz to 166MHz. >> >>Adam > > > The Spec minimum for DDR is 83.33MHz (See the JEDEC data sheet: > http://download.micron.com/pdf/misc/JEDEC79R2.pdf > ) Maybe, but for this chip is about 77MHz ( 13ns cycle length ) AdamArticle: 105885
Kolja Sulimma wrote: > Ray Andraka wrote: > >>John_H wrote: > > >>A DDS can be used to get a programmable rate that is not an integer >>multiple of the clock frequency and that has a linear relationship >>between the program value and the output frequency. The DDS is >>basically just an accumulator to which a fixed increment is added on >>each clock cycle. The square-wave output is taken from the MSB of the >>accumulator. (It will have jitter of up to a clock cycle depending on >>the increment value). > > > I prefer Bresenhams algorithm for frequency generation. > The N-bit accumulator has a frequency error of up to 1/2^N. > Bresenhams algorithm is exact for the question "generate N pulses in M > clock cycles". I also has minimum jitter (up to half a clock cycle). > The hardware implementation is simple and small. > > Kolja Sulimma Hmm, Hadn't thought of that. I've used Bresenham's algorithm for other things, but not for frequency generation. Should work quite well though. A DDS also solves the N pulses in M clock cycles, but only for the case M=2^k where k is the number of bits in the accumulator. I.e. the DDS produces N pulses in 2^k clocks where k is the width of the accumulator and N is the increment value. In the end, I think for M a power of two, the math reduces to the same thing whether you use Bresenham's or a DDS.Article: 105886
Hello Duane.
Thanks for the feedback. I have tried to rewrite the program and
correct the errors which were there in the original one.The program
here is the same one as before i.e. it counts the number of ones in the
bit stream. The only problem im facing now I can't really understand
the library inclusion stuff in modelsim. If my physical name differs
from the logical name then in the workspace window I actually see two
libraries named after them whereas if the names are the same then
theres just this one library called work(provided both of them have
been called 'work'). Additionally it seems possible to create a working
model without having to include it in a project. It is done by creating
a directory and mapping the local primary library i.e. work to it which
seems a little too strange to me. ...so to load those files you have
to "load that directory"
Heres the code:
library work;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.ALL;
entity ones_cnt is
Port ( A : in BIT_VECTOR (2 downto 0);
C : out BIT_VECTOR (1 downto 0));
end ones_cnt;
architecture Algorithmic of ones_cnt is
begin
process(A)
variable NUM: INTEGER range 0 to 3;
begin
NUM := 0;
for I in 0 to 2 loop
if A(I) = '1' then
NUM := NUM + 1;
end if;
end loop;
case NUM is
when 0 => C <= "00";
when 1 => C <= "01";
when 2 => C <= "10";
when 3 => C <= "11";
end case;
end process;
end Algorithmic;
entity AND2 is
port (I1,I2: in BIT; O: out BIT);
end AND2;
architecture BEHAVIORAL of AND2 is
begin
O <= I1 and I2;
end BEHAVIORAL;
entity OR3 is
port (I1,I2,I3: in BIT; O: out BIT);
end OR3;
architecture BEHAVIORAL of OR3 is
begin
O <= I1 or I2 or I3;
end BEHAVIORAL;
--use work.all;
entity MAJ3 is
port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
end MAJ3;
architecture AND_OR of MAJ3 is
component AND2C
port (I1,I2: in BIT; O: out BIT);
end component;
component OR3C
port (I1,I2,I3: in BIT; O: out BIT);
end component;
for all:AND2C use entity Work.AND2(BEHAVIORAL);
for all:OR3C use entity Work.OR3(BEHAVIORAL);
signal A1,A2,A3: BIT;
begin
G1: AND2C
port map (X(0),X(1),A1);
G2: AND2C
port map (X(0),X(2),A2);
G3: AND2C
port map (X(1),X(2),A3);
G4: OR3C
port map (A1,A2,A3,Z);
end AND_OR;
entity AND3 is
port(I1,I2,I3: in BIT;
O: out BIT);
end AND3;
architecture BEHAVIORAL of AND3 is
begin
O <= I1 and I2 and I3;
end BEHAVIORAL;
entity OR4 is
port(I1,I2,I3,I4: in BIT;
O: out BIT);
end OR4;
architecture BEHAVIORAL of OR4 is
begin
O <= I1 or I2 or I3 or I4;
end BEHAVIORAL;
entity INV is
port (I : in BIT; O : out BIT);
end INV;
architecture BEHAVIORAL of INV is
begin
O <= not I;
end BEHAVIORAL;
entity OPAR3 is
port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
end OPAR3;
architecture AND_OR of OPAR3 is
component AND3C
port (I1,I2,I3: in BIT; O: out BIT);
end component;
component OR4C
port (I1,I2,I3,I4: in BIT; O: out BIT);
end component;
component INV1
port (I: in BIT; O: out BIT);
end component;
for all:AND3C use entity Work.AND3(BEHAVIORAL);
for all:OR4C use entity Work.OR4(BEHAVIORAL);
for all:INV1 use entity Work.INV(BEHAVIORAL);
signal A1,A2,A3,A4,NA0,NA1,NA2: BIT;
signal T0,T1,T2,T_out: BIT;
begin
T0 <= X(0);T1 <= X(1);T2 <= X(2);
I1:INV1
port map(T0,NA0);
I2:INV1
port map(T1,NA1);
I3:INV1
port map(T2,NA2);
G1: AND3C
port map (T2,NA1,NA0,A1);
G2: AND3C
port map (NA2,NA1,T0,A2);
G3: AND3C
port map (T2,T1,T0,A3);
G4: AND3C
port map (NA2,T1,NA0,A4);
G5: OR4C
port map (A1,A2,A3,A4,T_out);
end AND_OR;
architecture STRUCTURAL of ones_cnt is
component MAJ3C
port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
end component;
component OPAR3C
port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
end component;
for all: MAJ3C use entity MAJ3(AND_OR);
for all: OPAR3C use entity OPAR3(AND_OR);
begin
COMPONENT_1: MAJ3C
port map (A,C(1));
COMPONENT_2: OPAR3C
port map (A,C(0));
end STRUCTURAL;
configuration Trial of ones_cnt is
for STRUCTURAL
end for;
end Trial;
This code compiles properly and I do see the waveform that I am
supposed to see. I would like to know more about the libraries and the
.ini file and the _info file that gets placed into a folder called
'work' . I guess this work folder which doesn't contain anything except
this _info file which is like a pointer to the actual source files or
the directory where the simulator can find the files i.e. the local
directory.
Hope to hear from you,
Aijaz Baig.
Duane Clark wrote:
> aijazbaig1@gmail.com wrote:
> > Hello Freinds.
> > I am a newcomer to the field of programmable logic devices and I am
> > currently trying to teach myself VHDL. I hope to learn some VHDL before
> > the next semester starts.
> > My sole purpose as of now is not to actually synthesise stuff but just
> > to simulate the various designs that I may try to create. I am using
> > the xilinx ISE webpack 8.2 on a windows XP machine.
> > Below I am trying to implement a design called ones_cnt wherein the
> > counter just counts the number of ones in a 4 bit array and prints the
> > result in a binary format.To understand the concept of configuration
> > declarations I have declared multiple architectures and I am trying to
> > use the configuration declaration statement to select one the them.
> >
> > Heres my code. Its a lil big may be but I hope you guys would have a
> > look.
> >
>
> > ...
> > use work.all; ----- this is the line where the error is flaged!! see
> > below for details.
>
>
> > ...
> > Heres the log report generated by the compiler:
> > Started : "Check Syntax".
> > Running vhpcomp
> > Compiling vhdl file "E:/Xlinx_ISE/workbench/ones_cnt.vhd" in Library
> > isim_temp.
>
> I don't know where the library name isim_temp came from. Did you specify
> that somewhere? The default name is normally "work" and it is generally
> best to leave it that way.
>
> If you really want to use a different name for some reason, then in the
> line above that generates the error, you would want to change it to:
> use isim_temp.all;
>
> As mentioned, generally you always want to compile entities into a
> directory named work. There is certainly no reason for a beginner to do
> differently. Then, if the entities you are using are part of the current
> project, the "use work.all;" will get them fine.
>
> If you also want to use entities that were compiled elsewhere, that is
> libraries, then you will have a file that provides a mapping. In
> Modelsim, the file is named modelsim.ini, or project_name.mpf. I don't
> know about the simulator you are using, but if it is not Modelsim, it
> will have some similar process. There, it will map a library name used
> in the current directory to the work directory where your library
> actually is located:
> [Library]
> sse_mezz_lib = ../../sse_mezz/sseio_hdl/work
> Notice that the library files are also compiled into a directory named
> work, but it is a work directory in a different location from the
> current project.
Article: 105887please don't post in multiple newsgroup and relax yourself. Marco "john" <conphiloso@hotmail.com> wrote in message news:1154456339.077044.118270@s13g2000cwa.googlegroups.com... > Hi, > > I posted in multiple groups becuase the fuzzy nature of the question. > The question belongs to labview people, VHDL people and hardware FPGA > people plus its my right to post question in any group I want. IF U > DONT WANT TO ANSWER IT THEN DO NOT BOTHER OK! > Regards > Marco T. wrote: >> "john" <conphiloso@hotmail.com> wrote in message >> news:1154445373.826354.312250@75g2000cwc.googlegroups.com... >> > Hello, >> > National instruments has introduced new module in their labview 8 for >> > programming the xilinx FPGA chips. It converts the labview programs >> > into VHDL . It can borrow image processing libraries from the labview >> > too. I was wondering that if somebody has used this module form labview >> > >> > can give me details about it. >> > Thanks >> > Regards >> > John >> > >> >> please don't post in multiple newsgroup. >> >> Marco >Article: 105888
jimwalsh142@hotmail.com wrote:
> Kolja Sulimma wrote:
> I have't heard of that... could you post some links?
Bresenham invented famous algorithms for efficiently drawing lines and circles on bitmaps.
The point here is to realized that the line drawing algorithm can be used for any kind of scaling with factors less than one.
Bresenhams algorithm computes when you need to go up when drawing a line X pixels to the right and Y pixels up.
This is the same problem as producing Y pulses in X clock cycles. Or scaling a bitmap by a factor Y/X. Or....
The algorithm is really simple:
eps = X;
while(true) {
wait_for_clock_edge();
eps -= Y;
if (eps < 0) {
generate_pulse();
eps += X;
}
}
Kolja Sulimma
Article: 105889Peter We use the ICS8442 and it has a very good jitter specification which is good for applications like RocketIO. When you are looking at this kind of specification there are not many devices as good as the ICS8442 especially if you want to use LVDS. The device is fairly layout sensative so do take care in that area of it but that's not unusual in this type of device. John Adair Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 Development Board. http://www.enterpoint.co.uk "Peter Mendham" <petermendham@NOCANNEDMEAT.computing.dundee.ac.uk> wrote in message news:eaq928$5j8$1@dux.dundee.ac.uk... > Dear all, > > I'm in the early stages of designing a board with a Virtex-4 FX on it > which we are planning to use for development involving RocketIO. The > other guys on the team have stated that it would be "really useful" to > have the clock for the RocketIO fed from a programmable oscillator. We > have a Virtex-II FX development board that has a similar arrangement, > using a ICS8442 low jitter LVDS frequency synthesizer. Does anyone have > any suggestions or advice? Can/Should I use the same device? Is this a > wild goose chase? > > TIA > > PeterArticle: 105890
"Ray Andraka" <ray@andraka.com> wrote in message news:xu3Ag.84846$ZW3.49952@dukeread04... <snip> > A DDS also solves the N pulses in M clock cycles, but only for the case > M=2^k where k is the number of bits in the accumulator. I.e. the DDS > produces N pulses in 2^k clocks where k is the width of the accumulator > and N is the increment value. In the end, I think for M a power of two, > the math reduces to the same thing whether you use Bresenham's or a DDS. This is getting a little off topic but it's such fun: I like to change the nature of the DDS and perform an N pulses in M clocks without the 2^k restriction by normally adding N in a k-bit accumulator but adding N-M in the one cycle when the accumulator overflows. The N or N-M value selection can be programmed as two constants and easily selected between the two within the accumulator. The result is typically much better available resolution. Most fractional values have an N/M solution using k values much lower than 32 bits that give accuracy significantly better than 1/4 ppb. Beyond finding the near perfect ratios (which is algoritmically straight-forward but extra software) not all N/M values have a better solution than N/2^k such that large values of k are sill desired for generic solutions. The accumulator output range is [N-M,+N) for an accumulator that selects between the two add constants. If the range [-M,0) is preferred, Acc+N and Acc+N-M adders can be muxed to the accumulator registers based on the +N add's carry output making things like lookup tables easier to deal with. In both cases, one of the strong uses of a DDS - indexing into a lookup table with the DDS MSbits - is twisted by a range that's no longer [0,2^k). In those cases the lookup table could be adjusted to the desired range or the modified DDS range multiplied by 2^p/M for a p-bit lookup. Because of some of the extra hardware or reduced lookup resolution, this approach is most desireable when lower jitter solutions are desired for a PLL-filtered output, keeping the jitter at the higher frequencies where they can be filtered out. There are still a few frequency values that will be problematic so it's not a complete fix. - John_HArticle: 105891
I almost always use integer subtypes for counters, so it would not
simulate as 'U'. I used a simple example to show a point about
combinatorial vs registered logic, not about reset; you can code async
or sync reset for registers using variables the same way you do for
signals.
Andy
mikegurche@yahoo.com wrote:
> You can assignee an initial value when a variable or signal is
> declared, e.g.,
>
> signal mysig: std_logic := '0';
>
> This will be the initial value when simulation starts. According to
> VHDL LRM, if there is no initial value, the first value defined in the
> data type will be used. Since std_logic is defined as ('U', 'X', '0',
> ...) in 1164 package. The 'U' value (for uninitialized) will be the
> default value.
>
> Since the initial value cannot always be synthesized, this approach
> should not be used in synthesis. It is better to use an explicit reset
> mechanism to initialize a sequential circuit.
>
> Mike G.
>
>
> Weng Tianxiang wrote:
> > Hi Mike,
> > Thank you for your response.
> > Now what is the first value after system asynchronous reset for first
> > loop?
> >
> > Thank you.
> >
> > Weng
> >
> > Mike Treseler wrote:
> > > Weng Tianxiang wrote:
> > >
> > > > In the following statement:
> > > > var := (var - 1) mod var_limit;
> > > > var is not assigned any value before it is used. var_limit is a
> > > > constant, of course.
> > > > Anything is wrong?
> > >
> > > No.
> > > For simulation, the present value is used
> > > to calculate and save the expression value.
> > > For synthesis, this is infers a register to save
> > > the value for the next process loop.
> > >
> > > -- Mike Treseler
Article: 105892"Marco T." <marc@blabla.com> wrote in message news:eaqhva$s8$1@nnrp.ngi.it... > please don't post in multiple newsgroup and relax yourself. > > Marco >>> please don't post in multiple newsgroup. >>> >>> Marco Marco - Why bother? What good do you do? Multiple newsgroups are required for this question, he simply didn't cross-post "properly." Who besides you cares? I just hate to see someone steered away from any newsgroup because of bad experiences. Why try to use a newsgroup where people are condesending or hostile? That's the last I'll comment in this thread. I just wish I could help with the original question. - John_HArticle: 105893
Andy wrote:
> I almost always use integer subtypes for counters, so it would not
> simulate as 'U'.
I prefer integers for counters also.
Up to 31 bits, that is :)
-- Mike Treseler
Article: 105894aijazbaig1@gmail.com wrote: > Hello Duane. > Thanks for the feedback. I have tried to rewrite the program and > correct the errors which were there in the original one. The program > here is the same one as before i.e. it counts the number of ones in the > bit stream. The only problem im facing now I can't really understand > the library inclusion stuff in modelsim. If my physical name differs > from the logical name then in the workspace window I actually see two > libraries named after them whereas if the names are the same then > there is just this one library called work (provided both of them have > been called 'work'). You can have two or more names refer to the same library. That is not at all uncommon. It should work fine. > Additionally it seems possible to create a working > model without having to include it in a project. It is done by creating > a directory and mapping the local primary library i.e. work to it which > seems a little too strange to me. ...so to load those files you have > to "load that directory" I am not completely sure what you mean here. You mean that you are putting a library mapping for work in the [Library] section of the project? The mapping of the current work library is implied (assuming you named the directory "work"), so there is no need to put a mapping in the Modelsim ini file, and I would suggest not doing so. But if you put the work directory somewhere else, then the logical mapping in the Modelsim ini file should enough. I don't really know what you mean by "loading" a directory.Article: 105895
Anthony wrote:
> Hi, I have a ISE7.1 project containing the PCI .ngo file. This completes correctly. Ugrading to ISE8.2i the .tcl script file generated for Leonardo now includes this .ngo as a source file which Leonardo fails to read. How does one solve this using the integrated flow? Thanks Anthony
Is ISE synthesis inadequate in this case?
Could you drop leo?
-- Mike Treseler
Article: 105896G=F3rski Adam wrote: > Uzytkownik PeteS napisal: > > > G=F3rski Adam wrote: > > > >>Uzytkownik subint napisal: > >> > >>>Hi, > >>> I am using a ddr(mt46v32m16fn -6) ddr and Virtex4 (lx60) fpga. > >>>And i am using the controller generated by the MIG1.5 tool. When i run > >>>this controller in the real hardware i am getting zeros in the result > >>>bus(read_data_fifo_out)... Dont know where i am wrong. > >>> I am monitored all my controller signals using the chipscope > >>>and they are all working fine for me. But the ddr is not giving > >>>anything back... > >>> Can u guys please tell me what is the minimum frequency at > >>>which i can operate the ddr controller. > >>>regards > >>>subin > >>> > >> > >>Proper frequency range for your memory is from 77MHz to 166MHz. > >> > >>Adam > > > > > > The Spec minimum for DDR is 83.33MHz (See the JEDEC data sheet: > > http://download.micron.com/pdf/misc/JEDEC79R2.pdf > > ) > > Maybe, but for this chip is about 77MHz ( 13ns cycle length ) > > Adam Micron does a good job of supporting lower speeds than the spec, but if the OP wants the system to work (guaranteed) for various parts across temperature, it's best to follow the spec. FWIW, I've made DDR run at 66MHz before (using Micron parts). Cheers PeteSArticle: 105897
Hi Jim, This is really simple stuff to do in programmable logic. You can do it with an adder, plus a comparator if your duty cycles is not 50/50. Simple in uC too, maybe even cheaper, but 10ns is probably a little too fast for a uC. While they can be much more complex and are not working at the same frequency range, you can steal some ideas from music synthesizers and such. - For a simple solution, check out this link: http://www.fpga4fun.com/MusicBox.html. - A more complex one is the implementation of the SID chip (MOS-6852?) [see jester_sid_voice.vhd.], found in the classic C-64 computers: http://www.fpga.nl/index.html?jester.html Now, If that's too much for you, I am sure someone in the NG can provide you some working code if you ask politely :) ok, I have two other things to say: 1. Instead of paying 99 USD for a CPLD, you could pay 99-150 USD and get a very nice FPGA board, maybe even one with a *hint* PLL *hint*! Play with it, and use it in future projects. 2. Ignore that BS you read in sci.elec.design, Altera Quartus rocks. And no, it has no difficulties inferring tri-state buffers :) and wellcome to the wonderful world of FPGAs! -Burns jimwalsh142@hotmail.com wrote: > Hi All, > > I'm trying to develop a programmable pulse generator, essentially a > single pulse of variable width repeated at a given rate. I posted a > similar question a few weeks ago on sci.elec.design and someone > suggested that this would make a nice CPLD project. As I'm keen to > learn about programmable logic devices I decided to buy a development > kit (Altera 7000 series) and try implementing the pulse generator. > > My ideal specification would be pulse widths from 10ns to 10us > incremented in 10ns steps at repetition rates between 1 to 10 kHz. The > evaluation board has a 25MHz clock so I'm limited to 40ns increments > but that's ok for now. > > I've been playing around with various counters etc but am struggling > to create anything useful, would be great if someone more experienced > could give me a few hints!? > > Thanks, > > Jim WArticle: 105898
hello everybody, are there any _simple_ ways of generating a sine waveform, maybe from a reference pulse/saw/triangle signal? (Thanks to Ray :) I know that there are more complicated ways of doing this, but for now i am interested in the simplest possible way for getting something that looks like a sine. actually, i am also interested on algorithms for generating any type of periodic signals (both low and high on harmonics) that works well in FPGAs. Jitter and variations are ok (in fact, they are welcome up to some degree). (for the record, it will be used for sound synthesis) regards, -BurnsArticle: 105899
burn.sir@gmail.com wrote: > are there any _simple_ ways of generating a sine waveform, maybe from a > reference pulse/saw/triangle signal? What about lookup-tables? After D/A conversion one should get a sine-like signal. Ralf
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z