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Hi, I'm using ISE 8.2.01i and Synplify 8.6.1 as synthesis tool. For one of my project, I can synthesize but when I try to launch implementation it stops quite imediatly WITHOUT ANY ERROR MESSAGE !!! Does anyone already have such a problem? Thanks for your help.Article: 105951
Hi Cliffor, I appreciate your response very much and you are an experienced expert in the field. I am a newbie in the field and really like to learn more. But I am determined to learn all those things you have mentioned better. What books can you suggest for me to buy and read about the fields? I have a book "Data Compression Book" by Mark Nelson. I want to learn two arithmatic algorithm too. Thank you. Weng Clifford Heath wrote: > Weng Tianxiang wrote: > > Your method is interesting, but is far from what I am looking for. > > It is too slow. > > I found that almost all Huffman encoding applications are static as in > > FAX, electronic books, ZIP files, JPEG, MPEG and so on. > > You are wrong there. ZIP files and most EBooks use some variant of LZ > encoding using a suffix tree (which might be feasible in hardware), > followed by Huffman coding - static *or* dynamic - on the resultant > symbols. Zip in particular uses the deflate algorithm, which can emit > either static or dynamically-generated Huffman data on each block. > But AFAIK, the Huffman table is *not* updated with each symbol. There > was a kid on sci.crypt a while back banging on about a per-symbol > dynamic Huffman technique he'd invented, perhaps look there. > > JPEG and MPEG use a DCT (and optionally in MPEG, motion compensation) > before applying further compression. The DCT is *not* huffman by > another name, its a discrete cosine transform. > > Also, look for information on Suffix Trees (used in Lempel-Zif > encoding), and you might find it can be done in a limited way in > hardware. The tree is built incrementally, and looks kinda like > Logan's trie, except that the first symbol of a sequence is at > the leaf, with the last symbol at the root. Kinda... > > In general, though Huffman coding was thought to be "optimal" two > decades ago, newer techniques have been shown to be better. For > example, arithmetic coding (needs two passes over the data though), > and the Burrows-Wheeler transform (used in bzip). > > There should be enough terms for you to go googling and perhaps find > a more suitable algorithm than Huffman. Don't forget - compression is > simply the process of removing whatever is predictable from a data > stream. The better you understand your data, the better an algorithm > can predict it, and the better your compressor can be. > > Good luck! > > Clifford Heath.Article: 105952
Hi group,
using a 128x32 bit simple dual port memory with independent
read and write clock results in following fmax for both
clocks (dout is registered):
Cyclone (I) 256 MHz, Cyclone II 210 MHz (restricted)
That's a little bit strange. Especially since the fmax for
the memories in the data sheet is the other way round:
Cyclone (I) 200 MHz and Cyclone II 250 MHz.
BTW: according to the errata sheet this configuration does not
need any restructuring from Quartus.
The numbers for simple dual port with a single clock are:
Cyclone (I) 256 MHz, Cyclone II 235 MHz (restricted)
I'm using Quartus 6.0.
Will this change with a new Quartus version?
Martin
Article: 105953Are you using chipscope to configure the FPGA ? I have sometimes faced the same problem, it works when I configure using Impact then use chipscope. Hope this helps.Article: 105954
maxascent schrieb: > Hi > > I am using the eval version of chipscope 8.2 with a Virtex 2 Pro. I have a > problem when I configure the FPGA I get the following message > > INFO: Found 0 Core Units in the JTAG device Chain. > > I have looked at Xilinx answer record 19337 and everything appears to be > ok, although it is for ver 6.3 > > Does anyone have any ideas? > > Cheers > > Jon sometimes it is possible to have ICON generated for wrong FPGA family that might pass synthesis, but then ChipScope will not see the cores. AnttiArticle: 105955
fbs.consulting@gmail.com schrieb:
> Hello All,
>
> I'm on a project which has ballooned in scope such that it calls for
> implementing the MicroBlaze (originally it called for a straight
> forward PicoBlaze, but that's a long story ...)
>
> I have successfully created custom peripherals and have implemented the
> code to control them from my device MMI. Thus, I'm mildly savvy wrt
> Xilinx EDK. However, I cannot get my SPI (EEPROM) peripheral to play
> nice-nice with the rest of the project.
>
> The transfer will begin successfully via XSpi_Transfer(...) but SS
> (CS) never de-asserts. The only work around I have come up with is
> XSpi_Reset(...), but that is pretty ugly and will more than likely
> present problems further down the road. I have a suspicion that I am
> not initalizing the SPI status handler or the interrupt controller
> correctly. I'd be the first to admit that I haven't dealt with
> interrupts since a really crappy lab on them in undergrad ....
>
> I apologize in advance if I haven't furnished enough information to
> help me. I'm more of a squishy analog hardware type. Any advice or
> application notes that are applicable would be greatly appreciated.
>
> Thanks,
> Matt
see at end. defenetly working code that reads ST serial flash ID code
using OPB_SPI
no interrupts though, but you should be able to use the code to verify
the basic SPI
operations
Antti
// SPI
Xuint16 Control;
Xuint8 SpiBuffer[32];
int NumBytesSent;
int NumBytesRcvd;
void SPI_init() {
XSpi_mSetSlaveSelectReg(SPI_BASEADDR, 0xFFFFFFFF);
Control =
XSP_CR_MANUAL_SS_MASK | XSP_CR_MASTER_MODE_MASK | XSP_CR_ENABLE_MASK |
XSP_CR_TRANS_INHIBIT_MASK;
XSpi_mSetControlReg(SPI_BASEADDR, Control);
}
int SPI_transfer(int count) {
//
int i;
NumBytesSent = 0;
NumBytesRcvd = 0;
/*
* Set up the device in loopback mode and enable master mode
*/
XSpi_mSetSlaveSelectReg(SPI_BASEADDR, 0xFFFFFFFF);
/*
* Fill up the transmitter with data, assuming the receiver can
hold
* the same amount of data.
*/
for (i=0;i<count;i++) {
XSpi_mSendByte(SPI_BASEADDR, SpiBuffer[i]);
}
/*
* Enable the device
*/
XSpi_mSetSlaveSelectReg(SPI_BASEADDR, 0xFFFFFFFD); // flash
Control &= ~XSP_CR_TRANS_INHIBIT_MASK;
XSpi_mSetControlReg(SPI_BASEADDR, Control);
/*
* Wait for the transmit FIFO to transition to empty before
checking
* the receive FIFO, this prevents a fast processor from seeing the
* receive FIFO as empty
*/
while (!(XSpi_mGetStatusReg(SPI_BASEADDR) & XSP_SR_TX_EMPTY_MASK));
/*
* Transmitter is full, now receive the data just looped back until
* the receiver is empty.
*/
while ((XSpi_mGetStatusReg(SPI_BASEADDR) & XSP_SR_RX_EMPTY_MASK) ==
0)
{
SpiBuffer[NumBytesRcvd++] = XSpi_mRecvByte(SPI_BASEADDR);
}
/*
* If no data was sent or the data that was sent was not received,
* then return an error
*/
// Control &= ~XSP_CR_ENABLE_MASK;
// XSpi_mSetControlReg(SPI_BASEADDR, Control);
Control |= XSP_CR_TRANS_INHIBIT_MASK;
XSpi_mSetControlReg(SPI_BASEADDR, Control);
return 0;
}
int SPI_query() {
// READ ID Command:
SpiBuffer[0] = 0x9F;
SPI_transfer(4);
xil_printf("\n\rFlash Id: %2X%2X%2X\n\r",
SpiBuffer[1],SpiBuffer[2],SpiBuffer[3]);
}
Article: 105956burn.sir@gmail.com a écrit : > Thats a nice one. It works really well with floating points: > http://www.musicdsp.org/archive.php?classid=1#10 > > the problem is the frequency parameter calculation (your "magic" 8 > here). > > maybe I can use a clock-enable to vary frequency and do some sort of > interpolation on top of that? > You have to use some maths to calculate this but I didn't have time to do it, and it was enough for me like that. The magic '8' just came out as I typed my reply, it probably isn't very good. NicolasArticle: 105957
John_H wrote: > "The missing higher harmonics are much larger than you can [bury] in noise." > > What in the heck are you asking for here? Dirty sinewaves have harmonics. > You suggest you want 72dB (i.e. full) supression of harmonics. Then the > missing harmonics are too high? What lower amplitude - in dB full scale - > do you need your missing harmonics to be so they aren't too high? > > I'd love to help but it sounds like you don't have a clue what you really > want. If you do, I certainly haven't gotten a clue what your true need is. Dear John, Lets have a more constructive discussion instead of insulting each other. Lets assume I already have a running counter with the right frequency. >From this, I can get triangle waves of different amplitudes and frequencies, to construct a sinewave. Or I can take any bit of the counter, which gives me a pulse wave that i can filter to get a sinewave. There are also other solutions involving unstable feedback loos and such. All of these cost a lot of hardware, specially if you need 1000+ sine generators to do additive synthesis. I was hoping someone could come up with a quick and dirty variation that doesn't take so much area. Some of the guys on this NG suggested some very interesting ways of generating sine-like waveforms which i am looking into right now. [BIG thanks guys!] Now lookup tables have some other problems. To understand this, you must first put away your engineering hat and put on your sound technician/psycho-acoustic hat because some of the lingo is not mathematically correct: Unless you can do some fancy interpolation, your LUT will generate really bad waveforms at the lower frequencies. The way brain interprets your sine (which if it was perfect, would be a first harmonic with no overtones) with a slight frequency modulation (which gives you a lot of unnatural overtones). Or the brain thinks it hears the remaining of a heavily filtered signal and tries to insert its best-guest overtones and sometimes even a fundamental frequency. [this is subject to research and somewhat disputed]. Of course, you could try to bury the "missing" or "extra" harmonics in noise so the brain doesn't freak out. But that has proven out to be hard. Maybe thats why listening to badly compressed music or speech will make your head hurt. So basically, relative to the amount of memory it requires, the LUT solution doesn't work so well. regards, - BurnsArticle: 105958
burn.sir@gmail.com wrote: ... > Lets assume I already have a running counter with the right frequency. > >From this, I can get triangle waves of different amplitudes and > frequencies, to construct a sinewave. Or I can take any bit of the > counter, which gives me a pulse wave that i can filter to get a > sinewave. There are also other solutions involving unstable feedback > loos and such. > All of these cost a lot of hardware, specially if you need 1000+ sine > generators to do additive synthesis. I was hoping someone could come up > with a quick and dirty variation that doesn't take so much area. Some > of the guys on this NG suggested some very interesting ways of > generating sine-like waveforms which i am looking into right now. [BIG > thanks guys!] You talk of audio frequencies. For a DDS, then Sine Lookup is probably the most expensive part. But yoiu can use one Sine Look up for a lot of generatore, when you time multiplex it. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 105959
<kempaj@yahoo.com> schrieb im Newsbeitrag news:1153444893.488445.68140@m73g2000cwd.googlegroups.com... > > Antti wrote: >> Hi >> >> Very first Virtex-5 test reports, tested with OpenFire (32bit Risc, >> MicroBlaze clone) targetting V5VLX50-3 (fastest speed grade) >> >> System clock constrained to 200MHz > > Hi Antti, > > Well, perhaps I'm going to get myself in trouble but what the heck: You > inspired me to see how fast I can get Nios II in stratix II (2S60-3 > chip). The system was minimal w/ 64K ram undoubtedly not much different > from yours. On the first try it hit a hair over 200MHz (requested > 200MHz). For the second try I asked for 225Mhz and it came out at 211. > This is Quartus/Nios II 6.0 SP1. > > Note: no seed-sweeping or other optimization was performed. Checked the > standard 'go-fast' tick-boxes in Quartus and pressed compile (was about > a 25-minue compile on my average desktop). > > Just some 90nm food for thought. > > Jesse Kempa > Altera > jkempa --at-- altera --dot-- com > Hi Jesse, thanks for the numbers! hum - after looking back at c.a.f. I found Xilinx references from April 2006 claiming that MicroBlaze ver 4.0 can achive 200MHz in Virtex-4 Silicon. Was a bit surprising to me at least, as to my knowledge getting an MicroBlaze system to run in Virtex-4 evan at 100MHz isnt so simple at all. Well that goes with full peripherals design. A local memory only design may actually run way higher. I just found my NIOS2 verilog code, maybe I run some NIOS2 benchmarks in Virtex-5, just for fun :) Antti PS Stratix-3, Cyclone-3, MAX-3 announcements are still expected late this year or are those dates shifted !? Hopefully MAX3 fixes what Altera missed with MAX2.Article: 105960
Okay. Do you want pure sinewaves to better than 16-bit resolution using only 12-bit values? Uwe Bonnes points out that one lookup arrangement can work for multiple sinewave generations. You can use a coarse lookup for a first step and produce a pure-sine result using a little math. sine(a+b)=sin(a)cos(b)+sin(b)cos(a) and, for very small b, sin(a+b)=sin(a)+b*cos(a) which leaves you with the need to convert your "b" delta from a 2^n phase difference to radians. If I remember my investigations properly, you can get 18 bits pure sine accuracy with the single lookup with 2 multiplies even at extremely low audio frequencies. To get past the psychoacoustic issues, you can generate your 12-bit values by taking your more-precise sine values and delta-sigma modulate the result providing very good audio. You should be able to get this to run with a large number of independent sine generators. You can even run multiple DDS generators using a BlockRAM to store both the accumulator value and the phase increment value. For 36 bits, you can get 256 independent DDS generators running to produce independent phase values for your sine lookups. You can do a huge amount of work in FPGAs when the needed frequencies are low. If you're only running at 30 MHz, you can do significantly more work by increasing the clock rate in your part. You should be able to run nearly 2k 18-bit accurate sinewaves through one sine-interpolated sinewave LUT structure. 300 clocks per sample, ~30 MHz external clock, ~180 MHz internal clock give ~1800 pipelined mechanisms. Insults weren't intended. The frustrations in real engineering come from loosely defined specifications. If the true needs are communicated, engineers can deliver "precise" solutions that give the necessary psychoacoustic results. <burn.sir@gmail.com> wrote in message news:1154624516.903851.277420@h48g2000cwc.googlegroups.com... > John_H wrote: >> "The missing higher harmonics are much larger than you can [bury] in >> noise." >> >> What in the heck are you asking for here? Dirty sinewaves have >> harmonics. >> You suggest you want 72dB (i.e. full) supression of harmonics. Then the >> missing harmonics are too high? What lower amplitude - in dB full >> scale - >> do you need your missing harmonics to be so they aren't too high? >> >> I'd love to help but it sounds like you don't have a clue what you really >> want. If you do, I certainly haven't gotten a clue what your true need >> is. > > > > Dear John, > > > Lets have a more constructive discussion instead of insulting each > other. > > > Lets assume I already have a running counter with the right frequency. >>From this, I can get triangle waves of different amplitudes and > frequencies, to construct a sinewave. Or I can take any bit of the > counter, which gives me a pulse wave that i can filter to get a > sinewave. There are also other solutions involving unstable feedback > loos and such. > > All of these cost a lot of hardware, specially if you need 1000+ sine > generators to do additive synthesis. I was hoping someone could come up > with a quick and dirty variation that doesn't take so much area. Some > of the guys on this NG suggested some very interesting ways of > generating sine-like waveforms which i am looking into right now. [BIG > thanks guys!] > > > Now lookup tables have some other problems. To understand this, you > must first put away your engineering hat and put on your sound > technician/psycho-acoustic hat because some of the lingo is not > mathematically correct: > > Unless you can do some fancy interpolation, your LUT will generate > really bad waveforms at the lower frequencies. The way brain interprets > your sine (which if it was perfect, would be a first harmonic with no > overtones) with a slight frequency modulation (which gives you a lot of > unnatural overtones). Or the brain thinks it hears the remaining of a > heavily filtered signal and tries to insert its best-guest overtones > and sometimes even a fundamental frequency. [this is subject to > research and somewhat disputed]. > > Of course, you could try to bury the "missing" or "extra" harmonics in > noise so the brain doesn't freak out. But that has proven out to be > hard. Maybe thats why listening to badly compressed music or speech > will make your head hurt. > > > So basically, relative to the amount of memory it requires, the LUT > solution doesn't work so well. > > > regards, - Burns >Article: 105961
burn.sir@gmail.com wrote: > All of these cost a lot of hardware, specially if you need 1000+ sine > generators to do additive synthesis. I was hoping someone could come up > with a quick and dirty variation that doesn't take so much area. Some > of the guys on this NG suggested some very interesting ways of > generating sine-like waveforms which i am looking into right now. [BIG > thanks guys!] > > > Now lookup tables have some other problems. To understand this, you > must first put away your engineering hat and put on your sound > technician/psycho-acoustic hat because some of the lingo is not > mathematically correct: > > Unless you can do some fancy interpolation, your LUT will generate > really bad waveforms at the lower frequencies. The way brain interprets > your sine (which if it was perfect, would be a first harmonic with no > overtones) with a slight frequency modulation (which gives you a lot of > unnatural overtones). Or the brain thinks it hears the remaining of a > heavily filtered signal and tries to insert its best-guest overtones > and sometimes even a fundamental frequency. [this is subject to > research and somewhat disputed]. > > Of course, you could try to bury the "missing" or "extra" harmonics in > noise so the brain doesn't freak out. But that has proven out to be > hard. Maybe thats why listening to badly compressed music or speech > will make your head hurt. > > > So basically, relative to the amount of memory it requires, the LUT > solution doesn't work so well. > > > regards, - Burns > Ahh, that is the missing part of the problem statement. You hadn't indicated before that you needed to make a bunch of these. Since it is audio, the sample frequencies are low compared to the possible clock speeds of modern FPGAs. Let's say you work at 44.1KHz, since that is a fairly standard audio sample rate. If you clock your FPGA at a very conservative 44.1 MHz, you can time multiplex 1000 generators using one set of hardware (and pipelined, current FPGAs can easily run at 5x that clock rate with some careful design). With that in mind, the cost of implementing a generator is not nearly the big deal it would be with a design that instanced 1000 copies. There are numerous ways to generate a sine. IIR methods work OK if you are generating a sine at a specific frequency, but they are not very good for using over a bunch of frequencies or when it has to be programmable, or when it has to have many different frequencies time multiplexed from the same hardware. Instead, I'd focus on an NCO implementation using a DDS, modified DDS, Bresenham's or other algorithm to generate the linear phase, followed by one of several possible converters for conversion of the phase to a sinusoid. Others have mentioned look-ups, which you have rejected because of the size needed for adequate phase resolution at low frequencies. You can use multiple tables for a progressive improvement. The phase ramp itself with the two MSBs modified provides a first order (triangular) approximation to the sine. You can then use tables as corrections to the triangle approximation rather than the sine itself to reduce the width of the table data. You can also use linear interpolation between table entries to improve on the apparent resolution of the table. Alternatively, and this might be the best bet for your application, you can use CORDIC to obtain an arbitrarily high phase resolution and magnitude precision. Since you can multiplex 1000's of channels through one instance, the area associated with the CORDIC is not a significant problem (CORDIC compares favorably in area to a complex multiplier built in the fabric, but generally takes more area than one built using dedicated fast multipliers in the FPGA, especially if only the real output is needed). You could also filter the triangle wave, but it is not going to give you good results over an extended frequency range, which you would need since the filter would be time-shared.Article: 105962
Austin Lesea schrieb: > Jim, > > Been down that road (making any software source public). Nope. Dead > end. I have more useful things to attend to right now. > > There are already many vendors that support JTAG, and the BSDL files are > their for them (or you). Feel free to buy and use their software > instead of ours. I am sure it can be made better than ours, and provide > more features than ours does. > > I would not want to appear to be competing with these vendors, nor > making their business any less profitable. > > Austin Hi Austin, I partially agree - making something open-source doesnt necessarily improve anything. But having programming-jtag cable driver support done properly should not be of very low importance for Xilinx. If people are frustrated with the JTAG cables and drivers and programming software, then it of course has influence on later decisions. Cable IV did never get proper support and as legacy will never get. So only official cable is USB Cable. And this cable is not accesible for the users any more at all. So no wonder a replacement firmware and CPLD code for it has already been made public (under GPL). Xilinx is big enough company to hire people good enough to master the low level driver programming. But no, Xilinx is still using the 'cheap solution' and has the jungo-windriver stuff inbetween. Its not so complicated todo it properly without jungo stuff. To my understanding jungo is only good for small-medium companies that need to get something working fast and cant afford to hire programmers capable to write to good quality OS hardware drivers. And no, I am not looking for that job. But I know the driver internals. My last commercial driver was Teletext kernel mode driver for some early windows (286 based machine?) - the board had an XC3030 on it. The driver programming is way simpler now and not so cirit=EDcal has PC horsepower is increased a lot. So not so impossible for a company like Xilinx to get it done properly. But no, the Cable IV still works in Cable III compat mode on most PCs I have seen. For no understandable reason and no solution. AnttiArticle: 105963
"Vivek Menon" <vivek.menon79@gmail.com> wrote in message news:1154616408.500264.170760@i42g2000cwa.googlegroups.com... > Can you please elaborate? Xilinx protects its IP and will not release synthesizable HDL (or perhaps the source has never been HDL in the first place). Instead you get a netlist file, which you need to add to your project. If you create new source file in ISE with a wizard it's done for you automatically. Otherwise you need to make sure that the macro search path is set properly, so that ISE can find the netlist. /MikhailArticle: 105964
ok..ny idea why the logic gets trimmed out?? Vivek MM wrote: > "Vivek Menon" <vivek.menon79@gmail.com> wrote in message > news:1154616408.500264.170760@i42g2000cwa.googlegroups.com... > > Can you please elaborate? > > Xilinx protects its IP and will not release synthesizable HDL (or perhaps > the source has never been HDL in the first place). Instead you get a netlist > file, which you need to add to your project. If you create new source file > in ISE with a wizard it's done for you automatically. Otherwise you need to > make sure that the macro search path is set properly, so that ISE can find > the netlist. > > /MikhailArticle: 105965
> ok..ny idea why the logic gets trimmed out?? Usually this means that none of the outputs is used in the design. Could be some mismatch in the component declaration maybe... It's hard to say without seeing the design... Try a minimalist design including the core only and nothing else... /MikhailArticle: 105966
Xilinx website still has links to it http://www.realfast.se/RFIPP/HWSW/system/system.shtml but all reference to the Sierra RTOS now point to "page not found" any idea what happened? AnttiArticle: 105967
> Do you have bytes or do you have bits? > The BlockRAMs are 18 kbit (double for Virtex-5, 1/4 for Virtex/-E, > Spartan-2/E). It's interesting. I have bytes. Actually when using Base System Builder I use 64KB (I hope Xilinx by B means bytes) of instruction and data LMB. My instruction and data address space is from 0000 to ffff. Considering that it's harvard architecture I assume that I have 64KBytes of instruction and data which use the two different ports of the BRAMs. It's a little bit confusing to me. Because I checked my system_init.vhd file and it seems that I have 16 Kbits (2KBytes) of memory on each BRAM. I used to think that it assigns each 2KBytes of my instructions and data (overall it becomes 4KB) to each BRAM. That exceeds the amount of memory on each BRAM. By the way what happens to the remaining 2Kbits if each BRAM has 18Kbits space?Article: 105968
Xesium schrieb: > > Do you have bytes or do you have bits? > > The BlockRAMs are 18 kbit (double for Virtex-5, 1/4 for Virtex/-E, > > Spartan-2/E). > > It's interesting. I have bytes. Actually when using Base System Builder > I use 64KB (I hope Xilinx by B means bytes) of instruction and data > LMB. My instruction and data address space is from 0000 to ffff. > Considering that it's harvard architecture I assume that I have > 64KBytes of instruction and data which use the two different ports of > the BRAMs. It's a little bit confusing to me. Because I checked my > system_init.vhd file and it seems that I have 16 Kbits (2KBytes) of > memory on each BRAM. I used to think that it assigns each 2KBytes of my > instructions and data (overall it becomes 4KB) to each BRAM. That > exceeds the amount of memory on each BRAM. By the way what happens to > the remaining 2Kbits if each BRAM has 18Kbits space? the 'parity bits' are never used in the EDK BRAM blocks, so those are effectivly "vasted". AnttiArticle: 105969
I am sorry for posting this as I have already posted it on the comp.soft-sys.matlab. I have a MatLab 7.2/Simulink 6.4/Xilinx System Generator 8.1.01 software installation. My problem is that the Xilinx Simulink blockset is entirely unstable. For example, when I try to change the properties of any Xilinx block, the Java runtime often crashes and takes MatLab with it. All other non-Xilinx blocks run perfectly fine. I tried to have MatLab use the system-wide Java installation but that didn't solve the problem. It is worth noting that when I installed the System Generator 8.1, it refused to accept the comcli.dll library that comes with MatLab 7.2 so I had to download an old dll from mathworks.com to avoid the error message. After setup, I reverted back to the original comcli.dll library because MatLab refused to run with the one I download from the website. The error message MatLab reports when it crashes is titled "Microsoft Visual C++ Runtime Library Error". The contents of the message are not clear. Any thoughts would be greatly appreciated. Thank you,Article: 105970
I receive the following error:
<SNIP>
ERROR:HDLParsers:3281 - "C:/Work/Hdl/dsp/qrdc.vhd" Line 89. rtl_ar is
not an architecture body for counterup in library work.
</SNIP>
Wrong! "rtl_ar" IS an architecture body stupid ISE!
Here is line 89:
<SNIP>
count_ins : entity work.counterup(rtl_ar)
generic map (
dwidth_g => CNT_WIDTH_C,
cntinit_g => 0
)
port map (
clk => clk,
rst_n_a => rst_n_a,
en => cnt_en,
clr => cnt_clr,
q => cnt_q
);
</SNIP>
I am able to compile qrdc.vhd under synthesis/implementation, but it
fails when I try to compile my test-bench "qrdc_tb.vhd" under ISE
simulator.
Any ideas? Note, all of the files are in my working library, but from
various directories, above and below my project root (i.e.
"../dsp/qrdc.vhd").
Thanks,
-B
Article: 105971Xesium wrote: > > Do you have bytes or do you have bits? > > The BlockRAMs are 18 kbit (double for Virtex-5, 1/4 for Virtex/-E, > > Spartan-2/E). > > It's interesting. I have bytes. Actually when using Base System Builder > I use 64KB (I hope Xilinx by B means bytes) of instruction and data > LMB. My instruction and data address space is from 0000 to ffff. > Considering that it's harvard architecture I assume that I have > 64KBytes of instruction and data which use the two different ports of > the BRAMs. It's a little bit confusing to me. Because I checked my > system_init.vhd file and it seems that I have 16 Kbits (2KBytes) of > memory on each BRAM. I used to think that it assigns each 2KBytes of my > instructions and data (overall it becomes 4KB) to each BRAM. That > exceeds the amount of memory on each BRAM. By the way what happens to > the remaining 2Kbits if each BRAM has 18Kbits space? Hi Xesium, If you use BSB to generate your design, the default setting is actually not a Harvard architecture system. So no extra 2KB. :) If you need Harvard architecture, from my experience, you need add a separate BRAM controller and BRAMs. WayneArticle: 105972
I am trying to simulate RocketIO MGT in VCS. When I do vcs -lmc-swift-template GT_SWIFT it says it couldn't find libswift.so library. I am using Red Hat Enterprise Linux WS release 3. What files/directories should I look for to confirm if the SmartModel Library is installed in VCS? or any better way to find if VCS is setup properly for SmartModel simulation. Thanks, Sovan.Article: 105973
On Thu, 03 Aug 2006 17:21:52 -0700, sovan wrote: > I am trying to simulate RocketIO MGT in VCS. When I do > vcs -lmc-swift-template GT_SWIFT > it says it couldn't find libswift.so library. I am using Red Hat > Enterprise Linux WS release 3. What files/directories should I look for > to confirm if the SmartModel Library is installed in VCS? or any better > way to find if VCS is setup properly for SmartModel simulation. > > Thanks, > Sovan. You have to install the models. There is a script in $XILINX/smartmodel/lin/image/sl_admin.csh that will generate the models. You are running RHEL so the script should just work. For those who are running unsupported distros the script needs to be slightly modified. Just before the platform check add the line set platform = "x86_linux"Article: 105974
They have re-designed their web site. Hope you read Swedish. http://www.realfast.se/RFIPP/products/sierra/sierra.shtml Antti wrote: > Xilinx website still has links to it > > http://www.realfast.se/RFIPP/HWSW/system/system.shtml > > but all reference to the Sierra RTOS now point to "page not found" any > idea what happened? > > Antti
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